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PHD38N02LT
N-channel TrenchMOS logic level FET
Product profile1.1 General descriptionLogic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
1.3 Applications Linear regulator for Double-Data Rate (DDR) memory
1.4 Quick reference data Pinning information[1] It is not possible to make a connection to pin 2.
PHD38N02LT
N-channel TrenchMOS logic level FET
Rev. 02 — 2 February 2007 Product data sheet Low on-state resistance n 2.5 V gate drive VDS≤20V n ID≤ 44.7A RDSon≤16 mΩ n Ptot≤ 57.6W
Table 1. Pinning gate (G)
SOT428 (DPAK) drain (D) [1] source (S) mounting base; connected to drain (D)
mbb076
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET Ordering information Limiting values
Table 2. Ordering informationPHD38N02LT DPAK plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
SOT428
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage 25°C≤Tj≤ 175°C - 20 V
VDGR drain-gate voltage (DC) 25°C≤Tj≤ 175 °C; RGS =20kΩ -20 V
VGS gate-source voltage - ±12 V drain current Tmb =25 °C; VGS=5 V; see Figure 2 and3 - 44.7 A
Tmb= 100 °C; VGS=5 V; see Figure2 - 31.6 A
IDM peak drain current Tmb =25 °C; pulsed; tp≤10 μs; see Figure3 - 179 A
Ptot total power dissipation Tmb =25 °C; see Figure1 - 57.6 W
Tstg storage temperature −55 +175 °C junction temperature −55 +175 °C
Source-drain diode source current Tmb =25°C - 44.7 A
ISM peak source current Tmb =25 °C; pulsed; tp≤10μs - 179 A
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET Thermal characteristics[1] Mounted on a printed-circuit board; verticalinstillair.
Table 4. Thermal characteristicsRth(j-mb) thermal resistance from junctionto mounting base see Figure4 - - 2.6 K/W
Rth(j-a) thermal resistance from junction to ambient
SOT428 minimum footprint - 75 - K/W
SOT404 minimum footprint [1]- 50 - K/W
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET Characteristics
Table 5. Characteristics =25 °C unless otherwise specified.
Static characteristicsV(BR)DSS drain-source breakdown
voltage= 250 μA; VGS =0V =25°C 20 --V= −55°C 18 --V
VGS(th) gate-source threshold voltage ID= 250 μA; VDS =VGS; see Figure 9 and10 =25°C 0.5 1.0 1.5 V= 175°C 0.3 - - V= −55°C - - 1.8 V
IDSS drain leakage current VDS =20V; VGS =0V =25°C - 0.05 1.0 μA= 175°C - - 500 μA
IGSS gate leakage current VGS= ±12 V; VDS=0V - 10 100 nA
RDSon drain-source on-state
resistance
VGS =5V; ID=25 A; see Figure 6 and8 =25°C - 13.5 16 mΩ= 175°C - 24.3 28.8 mΩ
Dynamic characteristicsQG(tot) total gate charge ID=25 A; VDS =10V; VGS =5V;
see Figure 11 and12 15.1 - nC
QGS gate-source charge - 4.5 - nC
QGD gate-drain charge - 4.2 - nC
Ciss input capacitance VGS =0V; VDS=20 V; f=1 MHz;
see Figure14 800 - pF
Coss output capacitance - 260 - pF
Crss reverse transfer capacitance - 190 - pF
td(on) turn-on delay time VDS =10V; ID=25 A; VGS =10V;= 5.6Ω -ns rise time - 12.5 - ns
td(off) turn-off delay time - 30 - ns fall time -23 - ns
Source-drain diodeVSD source-drain voltage IS=25 A; VGS=0 V; see Figure13 - 0.98 1.2 V
NXP Semiconductors PHD38N02LT
N-channel TrenchMOS logic level FET
