PHD101NQ03LT ,TrenchMOS(tm) logic level FETPHB/PHD101NQ03LTTrenchMOS™ logic level FETRev. 02 — 25 February 2003 Product data1. DescriptionN-ch ..
PHD12NQ15T ,N-channel TrenchMOS(tm) transistor
PHD14NQ20T ,TrenchMOS (tm) standard level FET
PHD14NQ20T ,TrenchMOS (tm) standard level FET
PHD18NQ10T ,N-channel TrenchMOS(tm) transistorFEATURES SYMBOL QUICK REFERENCE DATA• ’Trench’ technology d• Low on-state resistance V = 100 VDSS• ..
PHD18NQ10T ,N-channel TrenchMOS(tm) transistorLimiting values in accordance with the Absolute Maximum System (IEC 134)SYMBOL PARAMETER CONDITIONS ..
PLL102-04SC , Low Skew Output Buffer
PLL102-05SC , Low Skew Output Buffer
PLL102-05SC , Low Skew Output Buffer
PLL102-05SC , Low Skew Output Buffer
PLL103-06XC , DDR SDRAM Buffer with 2 DDR or 3 SDRAM DIMMS
PLL1700E ,Multi-Clock GeneratorMAXIMUM RATINGSMCKO 10 11 MCKOSupply Voltage (+V , +V , +V ) . +6.5VDD DDP DDBSupply Voltage Differ ..
PHD101NQ03LT
TrenchMOS(tm) logic level FET
PHB/PHD101NQ03LT renchMOS™ logic level FET
Rev. 02 — 25 February 2003 Product data DescriptionN-channel logic level field-effect power transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHB101NQ03L T in SOT404 (D2 -PAK)
PHD101NQ03LT in SOT428 (D-P AK).
Features Low gate charge Low on-state resistance.
Applications Optimized as a control FET in DC to DC convertors
Pinning information[1] It is not possible to make connection to pin 2 of the SOT404 and SOT428 packages.
Table 1: Pinning - SOT404, SOT428 simplified outline and symbol gate (g)
SOT404 (D2 -PAK) SOT428 (D-PAK) drain (d) [1] source (s) mounting base,
connected to drain (d)
MBK116
MBK091Top view
MBB076
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET Quick reference data Limiting values
Table 2: Quick reference dataVDS drain-source voltage (DC) 25≤Tj≤ 175°C - 30 V drain current (DC) Tmb =25 °C; VGS =5V - 75 A
Ptot total power dissipation Tmb =25°C - 166 W junction temperature - 175 °C
RDSon drain-source on-state resistance Tj =25 °C; VGS=10 V; ID=25A 4.5 5.5 mΩ =25 °C; VGS =5V; ID=25A 5.8 7.0 mΩ
Table 3: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDS drain-source voltage (DC) 25≤Tj≤ 175°C - 30 V
VDGR drain-gate voltage (DC) 25≤Tj≤ 175 °C; RGS =20kΩ -30 V
VGS gate-source voltage (DC) - ±20 V
VGSM gate-source voltage tp≤50 μs; pulsed;
duty cycle 25%;Tj≤ 150°C ±25 V drain current (DC) Tmb =25 °C; VGS =5V; Figure 2 and3 -75 A
Tmb= 100 °C; VGS =5V; Figure2 -75 A
IDM peak drain current Tmb =25 °C; pulsed; tp≤10 μs; Figure3 - 240 A
Ptot total power dissipation Tmb =25 °C; Figure1 - 166 W
Tstg storage temperature −55 +175 °C junction temperature −55 +175 °C
Source-drain diode source (diode forward) current (DC) Tmb =25°C - 75 A
ISM peak source (diode forward) current Tmb =25 °C; pulsed; tp≤10μs - 240 A
Avalanche ruggednessEDS(AL)S non-repetitive drain-source
avalanche energy
unclamped inductive load; ID =43A;= 0.19 ms; VDD≤15 V; RGS =50Ω;
VGS=10 V; starting Tj =25°C 185 mJ
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET Thermal characteristics
7.1 Transient thermal impedance
Table 4: Thermal characteristicsRth(j-mb) thermal resistance from junction to mounting base Figure4 - - 0.9 K/W
Rth(j-a) thermal resistance from junction to ambient
SOT428 mountedona PCB;
SOT428 minimum footprint;
verticalin stillair 75 - K/W
SOT404 and SOT428 mountedona PCB;
SOT404 minimum footprint;
verticalin stillair 50 - K/W
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET Characteristics
Table 5: Characteristics =25 °C unless otherwise specified
Static characteristicsV(BR)DSS drain-source breakdown voltage ID= 0.25 mA; VGS =0V =25°C 30 --V= −55°C 27 --V
VGS(th) gate-source threshold voltage ID=1 mA; VDS =VGS; Figure9 =25°C 1 1.9 2.5 V= 175°C 0.6 - - V= −55°C - - 2.9 V
IDSS drain-source leakage current VDS =30V; VGS =0V =25°C - 0.05 1 μA= 175°C - - 500 μA
IGSS gate-source leakage current VGS= ±20 V; VDS=0V - 10 100 nA
RDSon drain-source on-state resistance VGS =5V; ID =25A; Figure 7 and8 =25°C - 5.8 7 mΩ= 175°C - 10.5 12.6 mΩ
VGS =10V; ID =25A; Figure7 =25°C - 4.5 5.5 mΩ
Dynamic characteristicsQg(tot) total gate charge ID=50 A; VDD =15V; VGS =5V; Figure13 -23 - nC
Qgs gate-source charge - 10.5- nC
Qgd gate-drain (Miller) charge - 8 - nC
Ciss input capacitance VGS =0V; VDS=25 V; f=1 MHz; Figure11 - 2180- pF
Coss output capacitance - 600 - pF
Crss reverse transfer capacitance - 225 - pF
td(on) turn-on delay time VDD =15V; ID=25 A; VGS= 4.5V;= 5.6 Ω; resistive load
-23 - ns rise time -90 - ns
td(off) turn-off delay time - 37 - ns fall time -33 - ns
Source-drain diodeVSD source-drain (diode forward) voltageIS=25 A; VGS =0V; Figure12 - 0.85 1.2 V
trr reverse recovery time IS=10 A; dIS/dt= −100 A/μs; VGS =0V - 37 - ns recovered charge - 33 - nC
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET
Philips Semiconductors PHB/PHD101NQ03LT
TrenchMOS™ logic level FET