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PESD5V0U1BA-PESD5V0U1BB-PESD5V0U1BL
Ultra low capacitance bidirectional ESD protection diodes
Product profile1.1 General descriptionUltra low capacitance bidirectional ElectroStatic Discharge (ESD) protection diodes in
small Surface-Mounted Device (SMD) plastic packages designed to protect one data line
from the damage caused by ESD.
1.2 Features
1.3 Applications
1.4 Quick reference data
PESD5V0U1BA;
PESD5V0U1BB; PESD5V0U1BL
Ultra low capacitance bidirectional ESD protection diodes
Rev. 01 — 25 April 2007 Product data sheet
Table 1. Product overviewPESD5V0U1BA SOD323 SC-76 very small
PESD5V0U1BB SOD523 SC-79 flat lead ultra small
PESD5V0U1BL SOD882 - leadless ultra small Bidirectional ESD protection of one line n Ultra low leakage current: IRM =5nA Ultra low diode capacitance:Cd= 2.9pFn ESD protection of up to 10 kV IEC 61000-4-2; level4 (ESD) Computers and peripherals n Communication systems Audio and video equipment n Portable electronics Cellular handsets and accessories n Subscriber Identity Module (SIM) card
protection 10/100/1000 Ethernet n FireWire Local Area Network (LAN) equipment n High-speed data lines
Table 2. Quick reference dataTamb =25 °C unless otherwise specified.
Per diodeVRWM reverse standoff voltage - - 5 V diode capacitance f=1 MHz; VR=0V - 2.9 3.5 pF
NXP Semiconductors PESD5V0U1BA/BB/BL
Ultra low capacitance bidirectional ESD protection diodes Pinning information[1] The marking bar indicates the cathode.
Ordering information Marking
Table 3. Pinning
SOD323; SOD523 cathode1 [1] cathode2
SOD882 cathode1 [1] cathode2
001aab540
sym0451
Transparent
top view
sym0451
Table 4. Ordering informationPESD5V0U1BA SC-76 plastic surface-mounted package; 2 leads SOD323
PESD5V0U1BB SC-79 plastic surface-mounted package; 2 leads SOD523
PESD5V0U1BL - leadless ultra small plastic package; 2 terminals;
body 1.0× 0.6× 0.5 mm
SOD882
Table 5. Marking codesPESD5V0U1BA AA
PESD5V0U1BB B3
PESD5V0U1BL AN
NXP Semiconductors PESD5V0U1BA/BB/BL
Ultra low capacitance bidirectional ESD protection diodes Limiting values[1] Device stressed with ten non-repetitive ESD pulses.
[2] Measured from pin 1 to pin2.
Table 6. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Per device junction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Tstg storage temperature −65 +150 °C
Table 7. ESD maximum ratings
Per diodeVESD electrostatic discharge
voltage
IEC 61000-4-2
(contact discharge)
[1][2] -10 kV
MIL-STD-883 (human
body model) kV
Table 8. ESD standards compliance
Per diodeIEC 61000-4-2; level4 (ESD) >15kV (air); >8kV (contact)
MIL-STD-883; class 3 (human body model) >4kV
NXP Semiconductors PESD5V0U1BA/BB/BL
Ultra low capacitance bidirectional ESD protection diodes Characteristics
Table 9. CharacteristicsTamb =25 °C unless otherwise specified.
Per diodeVRWM reverse standoff voltage - - 5 V
IRM reverse leakage current VRWM=5V - 5 100 nA
VBR breakdown voltage IR=5 mA 5.5 7 9.5 V diode capacitance f=1MHz=0V - 2.9 3.5 pF=5V - 1.9 - pF
rdif differential resistance IR=1 mA - - 100 Ω
NXP Semiconductors PESD5V0U1BA/BB/BL
Ultra low capacitance bidirectional ESD protection diodes
NXP Semiconductors PESD5V0U1BA/BB/BL
Ultra low capacitance bidirectional ESD protection diodes Application informationThe PESD5V0U1Bx series is designed for the bidirectional protection of one signal line
from the damage caused by ESD pulses. The PESD5V0U1Bx series may be used on
lines where the signal polarities are either positive or negative with respect to ground.
Circuit board layout and protection device placementCircuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT)
and surge transients. The following guidelines are recommended: Place the PESD5V0U1Bx as close to the input terminal or connector as possible. The path length between the PESD5V0U1Bx and the protected line should be
minimized. Keep parallel signal paths to a minimum. Avoid running protected conductors in parallel with unprotected conductors. Minimize all Printed-Circuit Board (PCB) conductive loops including power and
ground loops. Minimize the length of the transient return path to ground. Avoid using shared transient return paths to a common ground point. Ground planes should be used whenever possible. For multilayer PCBs, use ground
vias.
