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PUMD30PHILIPSN/a3000avaiNPN/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = open
PEMD30PHIN/a4000avaiNPN/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = open


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PEMD30-PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kOhm, R2 = open
Product profile1.1 General description
NPN/PNP double Resistor-Equipped Transistors (RET)in Surface-Mounted Device (SMD)
plastic packages.
1.2 Features
1.3 Applications
1.4 Quick reference data
PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors;
R1 = 2.2 kΩ, R2 = open
Rev. 01 — 31 March 2006 Product data sheet
Table 1. Product overview
PEMD30 SOT666 - PEMB30 PEMH30
PUMD30 SOT363 SC-88 PUMB30 PUMH30 100 mA output current capability n Reduces component count Built-in bias resistors n Reduces pick and place costs Simplifies circuit design Low current peripheral driver n Cost-saving alternative for BC847BPN
and BC847BVN Control of IC inputs n Switching loads
Table 2. Quick reference data
Per transistor; for the PNP transistor with negative polarity
VCEO collector-emitter voltage open base - - 50 V output current - - 100 mA bias resistor 1 (input) 1.54 2.2 2.86 kΩ
Philips Semiconductors PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kΩ, R2 = open Pinning information Ordering information Marking
[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 3. Pinning GND (emitter) TR1 input (base) TR1 output (collector) TR2 GND (emitter) TR2 input (base) TR2 output (collector) TR1 001aab555 4 23
006aaa269
Table 4. Ordering information
PEMD30 - plastic surface-mounted package; 6 leads SOT666
PUMD30 SC-88 plastic surface-mounted package; 6 leads SOT363
Table 5. Marking codes
PEMD30 2U
PUMD30 *B3
Philips Semiconductors PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kΩ, R2 = open Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow soldering is the only recommended soldering method. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Per transistor; for the PNP transistor with negative polarity
VCBO collector-base voltage open emitter - 50 V
VCEO collector-emitter voltage open base - 50 V
VEBO emitter-base voltage open collector - 5 V output current - 100 mA
ICM peak collector current single pulse;≤ 1ms 100 mA
Ptot total power dissipation Tamb≤25°C
SOT363 [1]- 200 mW
SOT666 [1][2]- 200 mW
Per device
Ptot total power dissipation Tamb≤25°C
SOT363 [1]- 300 mW
SOT666 [1][2]- 300 mW
Tstg storage temperature −65 +150 °C junction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Table 7. Thermal characteristics
Per transistor
Rth(j-a) thermal resistance from
junction to ambient
in free air
SOT363 [1]- - 625 K/W
SOT666 [1][2]- - 625 K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient
in free air
SOT363 [1]- - 416 K/W
SOT666 [1][2]- - 416 K/W
Philips Semiconductors PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kΩ, R2 = open Characteristics
Table 8. Characteristics
Tamb =25 °C unless otherwise specified.
Per transistor; for the PNP transistor with negative polarity
ICBO collector-base cut-off
current
VCB =50V; IE=0A - - 100 nA
ICEO collector-emitter cut-off
current
VCE =30V; IB=0A --1 μA
VCE =30V; IB =0A;= 150°C
--50 μA
IEBO emitter-base cut-off
current
VEB =5V; IC=0A - - 100 nA
hFE DC current gain VCE =5V; IC =20mA 30 - -
VCEsat collector-emitter
saturation voltage=10 mA; IB= 0.5 mA - - 150 mV bias resistor 1 (input) 1.54 2.2 2.86 kΩ collector capacitance VCB =10V; IE =ie =0A;
f=1MHz
TR1 (NPN) - - 2.5 pF
TR2 (PNP) - - 3 pF
Philips Semiconductors PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kΩ, R2 = open
Philips Semiconductors PEMD30; PUMD30
NPN/PNP double resistor-equipped transistors; R1 = 2.2 kΩ, R2 = open Package outline Packing information
[1] For further information and the availability of packing methods, see Section13.
[2] T1: normal taping
[3] T2: reverse taping
Table 9. Packing methods
The indicated -xxx are the last three digits of the 12NC ordering code.[1]
PEMD30 SOT666 2 mm pitch, 8 mm tape and reel - - -315 - mm pitch, 8 mm tape and reel - -115 - -
PUMD30 SOT363 4 mm pitch,8 mm tape and reel;T1 [2] -115 - - -135 mm pitch,8 mm tape and reel;T2 [3] -125 - - -165
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