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PUMD12NXP/PHILIPSN/a21500avaiNPN/PNP resistor-equipped transistors; R1 = 47 k惟, R2 = 47 k惟
PEMD12NXP/PHILIPSN/a60000avaiNPN/PNP resistor-equipped transistors; R1 = 47 k惟, R2 = 47 k惟


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PEMD12-PUMD12
NPN/PNP resistor-equipped transistors; R1 = 47 k惟, R2 = 47 k惟
1. Product profile
1.1 General description
NPN/PNP double Resistor-Equipped Transistors (RET) in Surface-Mounted
Device (SMD) plastic packages.
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
PEMD12; PUMD12
NPN/PNP resistor-equipped transistors;
R1 = 47 k, R2 = 47 k
Rev. 4 — 21 November 2011 Product data sheet
Table 1. Product overview
PEMD12 SOT666 - PEMB2 PEMH2 ultra small and flat
lead
PUMD12 SOT363 SC-88 PUMB2 PUMH2 very small 100 mA output current capability  Reduces component count Built-in bias resistors  Reduces pick and place costs Simplifies circuit design  AEC-Q101 qualified Low current peripheral driver Control of IC inputs Replaces general-purpose transistors in digital applications
Table 2. Quick reference data
Per transistor; for the PNP transistor (TR2) with negative polarity
VCEO collector-emitter voltage open base - - 50 V output current - - 100 mA bias resistor 1 (input) 33 47 61 k
R2/R1 bias resistor ratio 0.8 1 1.2
NXP Semiconductors PEMD12; PUMD12
NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k
2. Pinning information
3. Ordering information
4. Marking
[1] * = placeholder for manufacturing site code
Table 3. Pinning
Table 4. Ordering information
PEMD12 - plastic surface-mounted package; 6 leads SOT666
PUMD12 SC-88 plastic surface-mounted package; 6 leads SOT363
Table 5. Marking codes
PEMD12 D2
PUMD12 D*1
NXP Semiconductors PEMD12; PUMD12
NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k
5. Limiting values
[1] Device mounted on an FR4 Printed-Circuit Board (PCB), single-sided copper, tin-plated and standard
footprint.
[2] Reflow soldering is the only recommended soldering method.
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Per transistor; for the PNP transistor (TR2) with negative polarity
VCBO collector-base voltage open emitter - 50 V
VCEO collector-emitter voltage open base - 50 V
VEBO emitter-base voltage open collector - 10 V input voltage TR1
positive - +40 V
negative - 10 V
input voltage TR2
positive - +10 V
negative - 40 V output current - 100 mA
ICM peak collector current single pulse;  1ms
-100 mA
Ptot total power dissipation Tamb25C
PEMD12 (SOT666) [1][2] -200 mW
PUMD12 (SOT363) [1] -200 mW
Per device
Ptot total power dissipation Tamb25C
PEMD12 (SOT666) [1][2] -300 mW
PUMD12 (SOT363) [1] -300 mW junction temperature - 150 C
Tamb ambient temperature 65 +150 C
Tstg storage temperature 65 +150 C
NXP Semiconductors PEMD12; PUMD12
NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k
6. Thermal characteristics
[1] Device mounted on an FR4 PCB, single-sided copper, tin-plated and standard footprint.
[2] Reflow soldering is the only recommended soldering method.
Table 7. Thermal characteristics
Per transistor
Rth(j-a) thermal resistance from
junction to ambient
in free air
PEMD12 (SOT666) [1][2]- - 625 K/W
PUMD12 (SOT363) [1]- - 625 K/W
Per device
Rth(j-a) thermal resistance from
junction to ambient
in free air
PEMD12 (SOT666) [1][2]- - 417 K/W
PUMD12 (SOT363) [1]- - 417 K/W
NXP Semiconductors PEMD12; PUMD12
NPN/PNP resistor-equipped transistors; R1 = 47 k, R2 = 47 k
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