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PEF22554E
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
QuadFALC®
Quad E1/T1/J1 Framer and Line Interface Component for Long and Short
Haul Applications
PEF 22554 HT Version 2.1
PEF 22554 E Version 2.1
DS7, 2002-09-16
PrefaceThis document describes the changes implemented in the QuadFALC® Version 2.1
related to the previous version 1.3. All functions not mentioned in this document remain
unchanged.
QuadFALC® Version 2.1 is a pin-compatible replacement of QuadFALC® Version 1.x.
Severe errata of QuadFALC® Version 1.3 are fixed. For more information please contact
your local sales office.
Organization of this DocumentChapter1, OverviewGives a general description of the product differences to its predecessor.
Chapter2, Electrical CharacteristicsShows the differences in electrical behavior.
Chapter2.4, Changed Supply Power Test Conditions T1/J1Shows the mechanical dimensions of the new BGA package.
Chapter3, AppendixShows a screenshot of the available software tool.
Related DocumentationData Sheet PEF22554 Version 2.1
Errata Sheet PEB22554 Version 1.3
Addendum PEB22554 Version 1.3
Revision History: Previous Version: Preliminray Delta SheetDS 6, 2002-08-19
Major Changes:
“Functional Changes” on Page2: Additional compare status field (CCR5.6)
“Changed DC Characteristics” on Page26: Power Supply Currents & LOS Limits,
1Overview
1.1Functional ChangesThe following function has been changed:Version status in register VSTR changed from 02H to 05HThe boundary scan part number changed to 142, the boundary scan ID changed to
1. A new BSDL file is required.The pulse mask programming (registers XPM(2:0)) has to be adjusted.The MCLK reference clock programming (registers GCM(8:1)) has to be changed.Variable master clock frequency function always enabled (GCM2(4) = 1).New feature “automatic short haul/long haul adjustment” available by setting
LIM0.EQON = 1. Additional automatic resynchronization mode for T1 (new bit: FMR2.7=AFRS).Additional compare status field (mode 2) in SS7 mode (new bit: CCR5.6=CSF2).2048 kHz synchronization interface according o ITU-T G.703 Sec. 13 (E1). For more
information refer to online Application Notes http://www.infineon.com/falc.
1.2Correction of ErrataAll severe errata of QuadFALC® Version 1.3 have been fixed. For more information
please contact your local sales office.
1.3Modified Pin FunctionsQuadFALC® Version 2.1 is pin-compatible with QuadFALC® Version 1.x. However,
some pin functions have been modified as detailed below:No 5V input levels are allowed due to technology restrictions (see Page
24).The currently unused ("N.C.") pins on V1.3 devices are used as "Core Voltage
Supply" (VDDC) pins and "Voltage Selection" (VSEL) pin on V2.x devices. Due to the
new technology the core voltage is 1.8V (see Chapter
1.5).
1.4PackageIn addition to the P-TQFP-144-8 package, a P-BGA-160-1 package with a ball pitch of
1.0mm and a size of 15mm × 15mm is supported (see Figure
4).
1.5Power SupplyThe Version 2.1 device requires two supply voltages, 3.3V and 1.8V. For compatibility
supply being generated internally using an on-chip voltage regulator. In order to
minimize power consumption, it is also possible to operate the device using separate
external 3.3V and 1.8V supplies. Please note that the 1.8V supply requires de-coupling
whether generated on-chip or externally. Supply voltage selection is done by using pin
VSEL. See Figure
1 and Figure2.
Figure1Single Voltage Supply1.6Pinout
Figure3Pin Configuration P-TQFP-144-8, Top View
Figure4Ball Layout P-BGA-160-1, Top View
Figure5Ball Layout P-BGA-160-1, Bottom View
1.7Pin DescriptionA short pin list of the BGA package is given in Table
2. For a complete signal descriptionrefer to the QuadFALC® V2.1 Preliminary Data Sheet.
Table1Additional Pin Functions
Table2BGA Pin Assignment
Table2BGA Pin Assignment (cont’d)
Table2BGA Pin Assignment (cont’d)
Table2BGA Pin Assignment (cont’d)
Table2BGA Pin Assignment (cont’d)
Table2BGA Pin Assignment (cont’d)
1.8Decoupling CapacitorsTo gain best performance, the following values are recommended for the external
decoupling capacitors between VDDC and VSS. There is one decoupling capacitor
required on each VDDC pin.
Figure6Decoupling Capacitor Placement
Table3Decoupling Capacitor Parameters
1.9Operation Description E1/T1/J1Note:Write access to unused register addresses: should be avoided, or set to “00” hex
in address range. up to xA9; must be avoided in address range above xA9 if not
defined elsewhere (for example in Table
4).To achieve optimum receiver sensitivity in E1 long haul mode (>38dB) the following
sequence must be run:
Note:Sequence must be repeated whenever receiver reset (CMDR.RRES) of arbitrary
channel was performed (e.g. after setting bit LIM1.EQON).
Table4Receive Line Interface Initialization (E1)
1.10Device Marking PatternThe sales code changed from PEB22554 Version 1.3 to PEF22554 Version 2.1.
The new marking pattern is:
Figure7Marking Pattern
