PEB3065NV3.2 ,SLICOFI (Signal Processing Subscriber...Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .558.1 Frequency Re ..
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PEB3065NV3.2 ,SLICOFI (Signal Processing Subscriber...Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15®4IOM -2 Interface . ..
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PEB3065NV3.2-PEB3065N-V3.2
SLICOFI (Signal Processing Subscriber...
ICs for Communications
Signal Processing Subscriber Line Interface Codec Filter
SLICOFI®
PEB 3065 Version 3.2
PEF 3065 Version 3.2
Data Sheet01.98
DS 2
Edition 01.98
Published by Siemens AG,
HL TS,
Balanstraße 73,
81541 München
© Siemens AG 1997.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
PEB 3065
PEF 3065
Table of ContentsPageGeneral Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.1Pin Definition and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SLICOFI® Principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.1SLICOFI® Signal Flow Graph: AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.2SLICOFI® Signal Flow Graph: DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.3Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.4SLICOFI® Signal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4IOM®-2 Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Programming the SLICOFI®. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.1Types of Monitor Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
5.2SLICOFI® Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
5.3SOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.4TOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
5.5COP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.6IOM®-2 Interface Command / Indication Byte . . . . . . . . . . . . . . . . . . . . . .42
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
6.1Reset Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.2Basic Setting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.3Power Denial (PDen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.4Power Down (PDown) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
6.5Active Mode (Act) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
6.6Ringing Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
SLIC Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Transmission Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
8.1Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
8.2Group Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
8.3Out-of-Band Signals at Analog Output (receive) . . . . . . . . . . . . . . . . . . . .59
8.4Out-of-Band Signals at Analog Input (transmit) . . . . . . . . . . . . . . . . . . . . .60
8.5Overload Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
8.6Gain Tracking (receive or transmit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
8.7Total Disortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
8.8Transhybrid Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .669.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
9.1.1Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
PEB 3065
PEF 3065
Table of ContentsPage9.3DC-Feeding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
9.3.1DC-Feeding (TA=0 to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
9.3.2DC-Feeding (TA=−40 to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
9.4HV-SLIC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
9.5IOM®-2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
9.6IOM®-2 Command/Indication Interface Timing (DCL=4096kHz) . . . . . .74
9.7IOM®-2 Command/Indication Interface Timing (DCL=2048kHz) . . . . . .75
9.8External Masterclock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
10.1IOM®-2 Interface Monitor Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . .77
10.2Channel Identification Command (CIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .81
10.3Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.4List of Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
PEB 3065
PEF 3065
General DescriptionGeneral Description
The Signal Processing Subscriber Line Interface Codec Filter SLICOFI
(PEB3065/PEF3065) is a logic continuation of the well established family of the
SIEMENS PCM-Codec-Filter-IC’s with the vertical integration of all DC-feeding,
Supervision and Meterpulse Injection features on chip as well. Fabricated in a standardμm BiCMOS technology the SLICOFI is tailored for very flexible solutions in digital
communication systems.
For the first time the SLICOFI uses the benefits of a DSP not only for the voice channel
but even for line feeding and supervision which leads to a very high flexibility without the
need for external components.
Based on an advanced digital filter concept, the PEB3065/PEF3065 provides excellent
transmission performance. The new filter concept (second generation in
SIEMENS-Codec-family) leads to a maximum of independence between the different
filter blocks. Each filter block can be seen as a one to one representative of the
corresponding network element. Together with the software package SLICOS, filter
optimizing to different applications can be done in a clear and straight forward procedure.
The AC frequency behavior is mainly determined by the digital filters. Using the new
oversampling 1 bit-AD/DA converter, linearity is only limited by second order parasitic
effects.
The new - digital - solution of line feeding offers free programmability of feeding current
and voltage as well as very fast settling of the dc-operating point after transitions.0.3Hz lowpass filter in the DC-loop is mainly responsible for the system stability.
Additionally teletax generation and filtering is implemented as well as free programmable
(balanced) ring generation with zero-crossing injection. Offhook detection with
programmable thresholds is possible in all operating modes. To reduce overall power
consumption of the line card, the SLICOFI provides a special mode called Power Denial
where Offhook is done via 2 high voltage inputs (VLINE1 and VLINE2) directly connected to
the line if the HV-SLIC is switched off.
Signal Processing
Subscriber Line Interface Codec Filter
SLICOFI®
PEB 3065
PEF 3065
Data Sheet for the Version 3.2CMOS
1.1FeaturesSingle chip CODEC and FILTER including all LOW
VOLTAGE SLIC functionsOnly few external components requiredNo trimming or adjustments requiredSpecification according to relevant CCITT, LSSGR
and DBP recommendationsDigital signal processing techniqueAdvanced low power 1 μm BiCMOS1) technologyPCM encoded digital voice transmission (A-Law or
μ-Law)Four pin serial IOM-2 InterfaceStandard P-LCC-44 packageHigh performance AD and DA ConversionProgrammable digital filters forImpedance matchingTranshybrid balancingFrequency response
–GainAdvanced test capabilitiesIntegrated line and circuit testsTwo programmable tone generatorsOptimized HV-SLIC InterfaceFully digital programmable DC-CharacteristicProgrammable Constant Current from 0-70 mAProgrammable Resistive Values from 0-2 × 500 ΩProgrammable Integrated Teletax Injection and Filtering during Conversation and
OnhookProgrammable up to 125 mVrms (5 Vrms at ab-wire)Programmable frequency 12/16 kHzAbbreviations see chapter 10.4.
PEB 3065
PEF 3065
General DescriptionPolarity reversal (programmable soft or hard)Integrated (balanced) Ringing Generation with zero crossing injectionProgrammable frequency between 16.6 and 70 Hz (up to 300 Hz for test)Programmable amplitude up to 2.125 Vrms (85 Vrms at ab-wire)Four operating modes: Power Denial, Power Down, Active and RingingOffhook detection with programmable thresholds for all operating modes Integrated Ring Trip Detection with zero crossing turn off functionGround Start and Loop Start possibleIntegrated checksum Calculation for CRAMLine Card Identification
PEB 3065
PEF 3065
Pin ConfigurationPin Configuration
Figure 1
PEB 3065
PEF 3065
Pin Configuration
2.1Pin Definition and Functions
The following tables group the pins according to their functions. They include pin
number, pin name, type, a brief description of the function, and cross-references
referring to the sections in which the pin functions are discussed.
Table 1
Table 2IOM®-2 Pins
Table 3Interface to HV-SLIC
PEB 3065
PEF 3065
Pin Configuration
Table 4IO Pins
Table 5Miscellaneous Function Pins
Table 3Interface to HV-SLIC (cont’d)
PEB 3065
PEF 3065
Pin Configuration
Table 6Pins not Used
PEB 3065
PEF 3065
SLICOFI® PrinciplesSLICOFI® Principles
Five Oversampling AD/DA converters are necessary for data conversion to gain the
aspired programmability in the DSP. Generally the SLICOFI can be divided between the
AC-Loop which is handling the voice and additionally teletax and the DC-Loop for line
feeding, ringing injection and supervision.
3.1SLICOFI® Signal Flow Graph: AC
Figure 2
Transmit Path
The analog input signal has to be connected to pin 21 (ITAC) by an external capacitor
(680nF-1μF) for AC/DC separation. After passing a simple initializing prefilter (PREFI)
the voice signal is converted to a 1-bit digital data stream in the ΣΔ-converter. The first
down sampling steps are done in fast running digital hardware filters. The following steps
are implemented in the micro code which has to be executed by the central Digital Signal
Processor. This DSP-machine is able to handle the workload for the DC-loop as well. At
the end the fully processed signal (flexibly programmed in many parameters) is
transferred to the IOM-2 Interface in a PCM-compressed signal representation.
Receive Path
The digital input signal is received via the IOM-2 Interface. Expansion,
PEB 3065
PEF 3065
SLICOFI® Principles
steps which are done by the DSP-machine. The up sampling interpolation steps are
again processed by fast hardware structures to reduce the DSP-workload. The
upsampled 1-bit data stream is then converted to an analog equivalent which is
smoothed by a POST-Filter (POFI). At the summing point the values of the
TTX-Generator and the DC-loop are added and then transferred to the output pin 262W).
Loops
There are two different loops implemented: The Impedance Matching (IM) loop which is
divided in 3 separate loops to guarantee very high flexibility to various impedances, and
the Transhybrid Balancing (TH) loop.
3.2SLICOFI® Signal Flow Graph: DC
Figure 3
DC Characteristic
The incoming information at pin IT (scaled transversal current (AC + DC) transferred to
a voltage via a resistor) is first lowpass filtered (0.3Hz) for stability and noise reasons
and then fed into the DC-characteristic block. This consists of two branches which
represents different kinds of feeding behavior. In typical applications it acts as a
programmable constant current source (R > 30k). If the desired value cannot be held
PEB 3065
PEF 3065
SLICOFI® Principles
feeding switches automatically and smooth to the resistive branch (Rin > 0-1k). For
superposing voice as well as Teletax pulses the necessary drop at the line can be
calculated and taken into account as well. The outgoing DC-feeding value - superposed
with the AC-Loop result at the summing point is transferred to pin 26 (V2W).
Supervision
The HOOK-information is the most important one and the SLICOFI provides this
information via CIDU (see chapter5.6), in all operating modes:
For Power Denial via 2 high voltage input pins (VLINE) directly connected to the line.
For each other mode the line current information (from pin IT) is transferred via an ADC
to the DSP where the Offhook information is extracted in the proper way:
Power Down: Offhook is detected if Constant current feeding is possible.
Active: Offhook is detected if the incoming voltage at IT exceeds a programmed
value. To avoid instable information, lowpass filtering and a hystereses
is provided (2 independent programmable values for Offhook and
Onhook detection).
Ringing:Ring Trip occurs if the DC-value at IT exceeds the programmed Ring
Trip threshold. The AC-value is filtered by the SLICOFI automatically.
Ring Trip detection is reported within 2 cycles of the ring period and then
the internal ring generator is switched off within 3 cycles at zero crossing
of the ring voltage.
Ground key (CIDU-6: GNK) is reported if the absolute value of the voltage at pin IL
exceeds 255mV. With a programmable lowpass filter (see chapter5.6) interfering
frequencies (e.g. power lines with 50/60Hz) can be filtered very effectively.
3.3Test Features
The SLICOFI provides two different kinds of test features: Internal test loops for circuit
testing and defined test loops to perform board and line tests. There are loops for testing
AC and DC path. As a special feature it is possible to switch signals to and from the
DC-path via the IOM-2 Interface. Additionally there is the possibility to cut off the
AC-receive and transmit path.
(The different kinds of testmodes are described in chapter
10.3)
PEB 3065
PEF 3065
SLICOFI® Principles
3.4SLICOFI® Signal Block Diagram
PEB 3065
PEF 3065
IOM®-2 Interface
4IOM®-2 Interface
The IOM-2 interface consists of two data lines and two clock lines. DU (data upstream)
carries data from the SLICOFI to a master device. DD (data downstream) carries data
from the master device to the SLICOF. A frame synchronization clock signal (8kHz,
FSC) as well as a data clock signal (2048kHz or 4096kHz, DCL) has to be supplied to
the SLICOFI. The SLICOFI handles data as described in the IOM-2 specification for
analog devices.
Figure 5IOM®-2 Interface Timing for 8 voice channels (per 8kHz frame)
PEB 3065
PEF 3065
IOM®-2 Interface
Figure 6IOM®-2 Interface Timing (DCL = 4096kHz, SEL24 = 1, per 8kHz frame)
PEB 3065
PEF 3065
IOM®-2 Interface
IOM®-2 Time Slot Assignment
An assignment of 8 time slots is possible for each voice-channel. The IOM-2 operating
mode and time slot selection is set completely by pin-strapping.Time slots 1, 2, 3 and 5 are not working with DCL = 2048 kHz.
For a workaround in the 2MHz mode please contact the SIEMENS HL Application group.
Table 7
PEB 3065
PEF 3065
Programming the SLICOFI®Programming the SLICOFI®
With the appropriate commands, the SLICOFI can be programmed and verified very
flexible via the IOM-2 Interface monitor channel.
Data transfer to the SLICOFI starts with a SLICOFI-specific address byte (81H).
With the second byte one of 3 different types of commands (SOP, TOP or COP) is
selected. SOP and COP can be used as a write or read command, the TOP-Command
is used for reading only. Due to the extended SLICOFI feature control facilities, SOP,
COP and TOP commands contain additional information (e.g. number of subsequent
bytes) for programming (write) and verifying (read) the SLICOFI status.
A write command is followed by up to 8 bytes of data. The SLICOFI responds to a read
command with its IOM2 specific address and the requested information, that is up to 15
bytes of data (see chapter5.2).
Attention: Each byte on the monitor channel has to be sent twice at least according to
the IOM2 Monitor handshake procedure. (For more information on IOM-2 specific
Monitor Channel Data Structure see chapter10).
5.1Types of Monitor Bytes
The 8-bit Monitor bytes have to be interpreted as either commands or status information
stored in Configuration Registers or the Coefficient Ram. There are three different types
of SLICOFI commands which are selected by bit 2 and 3 as shown below.
(x… don’t care)
SOPStatus Operation:SLICOFI status setting/monitoring
TOPTransfer Operation:Read Certain Status Options only
COPCoefficient Operation:filter coefficient setting/monitoring
Storage of programming information:
8 (9) status configuration registers:(SCR0), SCR1, … SCR8 accessed by SOP
Bit76543210
Bit76543210
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
8 test configuration registers:STCR1…STCR8 accessed by SOP
commands
18 Transfer configuration registers:TCR1, TCR2…TCR18 accessed by TOP
commands
1 Coefficient RAM:CRAM accessed by COP commands
5.2SLICOFI® Programming Procedure
(DD… Data Downstream, DU… Data Upstream, only the Monitor Bytes are considered)
SOP– Write Commands76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU
PEB 3065
PEF 3065
Programming the SLICOFI®
TOP – Write Commands
no write command possible; reading only.
COP – Write Commands
SOP – Read Commands76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU
PEB 3065
PEF 3065
Programming the SLICOFI®
TOP – Read Commands76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU76543210Bit76543210DU
PEB 3065
PEF 3065
Programming the SLICOFI®
COP – Read Commands
Example for a Mixed Command76543210Bit76543210DU76543210Bit76543210DU
PEB 3065
PEF 3065
Programming the SLICOFI®76543210Bit76543210DU
PEB 3065
PEF 3065
Programming the SLICOFI®
5.3SOP Command
To modify or evaluate the SLICOFI status, the contents of up to 8 configuration registers
SCR1, … SCR8 may be transferred to, or up to 9 (incl. SCR0) from the SLICOFI. This is
done by a SOP-Command (status operation command).
With LSEL = 11 some test registers can be set/read (for internal use only!).
The two commands POLNR and RST are only valid if RW = 0 (write); they are ignored
for RW = 1 (read)Read/Write Information: Enables reading from the SLICOFI or writing
information to the SLICOFI
RW = 0Write to SLICOFI
RW = 1Read from SLICOFI
POLNRGeneral DC feeding Information: Normal or Reverse Polarity
POLNR = 0sets the SLICOFI to Normal Polarity feeding
POLNR = 1sets the SLICOFI to Reverse Polarity feeding
RSTSoftware Reset
RST = 0Normal Operation
RST = 1Reset SLICOFI (same as Reset pin 36 (RES)): sets the
SLICOFI to the basic setting mode (see chapter 6.1).
LSELLength select information (also see programming procedure,
chapter5.2).
This field identifies the number of subsequent data bytes
If RW = 0Write to SLICOFI
LSEL = 00no byte of data is following
LSEL = 012 bytes of data are following (SCR1, SCR2)
LSEL = 108 bytes of data are following (SCR1,... SCR8)
LSEL = 11Accesses Test Registers (see Appendix)
If RW = 1Read from SLICOFI
LSEL = 001 byte of data is following (SCR0)
LSEL = 013 bytes of data are following (SCR0, SCR1, SCR2)
LSEL = 109 bytes of data are following (SCR0, … SCR8)
LSEL = 11Accesses Test Registers (see Appendix, chapter 10.3)
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR0 Configuration Register 0
Configuration Register SCR0 can be read only. It gives a mirror of the SOP-Command
itself to control its contents and represents the reset value as defined below.
Reset value: 54H (if only SCR0 is read. It depends on LSEL1 and LSEL0.)
POLNRGeneral DC feeding Information: Normal or Reverse Polarity
POLNR = 0indicates, that the SLICOFI was set to Normal Polarity
feeding
POLNR = 1indicates, that the SLICOFI was set to Reverse Polarity
feeding1)
RSTSTStatus of Reset
Indicates the occurrence of a reset:
RSTST = 1if there has been a Reset by any of the following three
reasons:
– via the Reset-pin (RES)
– via the Power on Reset
– via the Software Reset (SOP–Command)
the RSTST-bit is set to ‘1’.
RSTST = 0no Reset has occurred since the last SOP-Read
(with LSEL = 00b).
This bit is cleared only by a SOP-read with LSEL = 00b at the end of the
data transmission.
LSELis the mirror of the SOP-Read LSEL contents.
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR1 Configuration Register 1
Configuration register SCR1 defines the basic feeding modes of the SLICOFI and
enables/disables test features:
Reset value: 00HSLICOFI is set either in Power Down or Power Denial mode together
with CIDD-bits CIDD6,7 (see chapter 6).
PD = 0SLICOFI set to Power Denial mode; line supervision viaLINE1, 2
PD = 1SLICOFI set to Power Down mode
N/BBSLICOFI is in normal or Boosted Battery mode (see chapter6.5).
N/BB = 0Normal feeding
N/BB = 1Changes ternary interface to HV-SLIC which sets the
HV-SLIC to Boosted Battery modeHandling of Loop Back functions for on chip test loops
LB = 0normal function
LB = 1the desired Loop Back function (analog or digital) is
enabled (selected by SCR6, together with the
TM-bit (SCR2-3))
ETG1Enables programmable Test Tone Generator 1
ETG1 = 0Test Tone Generator 1 is disabled
ETG1 = 1Test Tone Generator 1 is enabled
HI-bFor HV-SLIC test function
HI-b = 0normal operation
HI-b = 1changes ternary Interface to HV-SLIC which sets the
b-leg of the line into high impedance state
HI-aFor HV-SLIC test function
HI-a = 0normal operation
HI-a = 1changes ternary Interface to HV-SLIC which sets the
a-leg of the line into high impedance state
DHP-XDisable Transmit Highpass for test reasons (see chapter10.3)
DHP-X = 0Transmit Highpass Filter is enabled
DHP-X = 1Transmit Highpass Filter is disabled
CORCut Off Receive Path for test reasons (see chapter10.3)
COR = 0Receive Path transmission is available
COR = 1Receive Path is disabled
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR2 Configuration Register 2
Configuration register SCR2 defines some testmode output results, some special
SLMA-mode requirements and the possibility to program 2 I/O-ports.
Reset value: 00H (then as measured)
MVAInternal measurement results shown in the following 3 bits are valid or
not valid (read only) (see chapter 10.3)
MVA = 0the following 3 ok-bit results are not valid
MVA = 1the following 3 ok-bit results are valid
OKTONTest Tone measurement information (read only) - programmed via
COP-command (Testloop: DLB_4M and TG1 enabled, see
chapter10.3)
OKTON = 0Test tone value out of defined range
OKTON = 1Test tone value in defined range
OKTTXTest teletax metering information (read only) - programmed via
COP-command (see chapter 10.3)
OKTTX = 0Test teletax metering value smaller than defined value
OKTTX = 1Test teletax metering value larger than defined value
OKRNGTest Ring tone information (read only) – programmed via
COP-command (see chapter 10.3)
OKRNG = 0Ring tone value smaller than defined value
OKRNG = 1Ring tone value larger than defined valueenables or disables the SLICOFI Testmodes (see chapter 10.3)
TM = 0resets the assigned tests (normal mode)
TM = 1sets the assigned tests (selected by SCR6, together with
the LB-bit (SCR1-5))
NOSLNo slope: means that the ramping of teletax (TTX) signal is switched off
NOSL = 0Slope of TTX-Signal is smooth
NOSL = 1Hard switch of TTX-Signal
IO1Selection for programmable IO - Pin IO1
IO1 = 0sets the pin IO1 as an input
IO2 = 1sets the pin IO1 as an output
IO2Selection for programmable IO - Pin IO2
IO1 = 0sets the pin IO2 as an input
IO2 = 1sets the pin IO2 as an output
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR3 Configuration Register 3
Configuration register SCR3 defines the meterpulse settings and the Data Upstream
Persistency Counter.
Reset value: 8AH
TTXNOMeterpulses are represented by teletax (TTX) with 12 or 16kHz or with
Reverse Polarity
TTXNO = 0Meterpulses are represented with 12kHz or 16kHz
TTXNO = 1Meterpulses are represented with Reverse Polarity
TTX12Teletax-signal with 12kHz or 16kHz
TTX12 = 016kHz teletax-signal
TTX12 = 112kHz teletax-signal
SOREVThe reversal pulse is either soft or hard
SOREV = 0hard reversal
SOREV = 1soft reversal
Note:For proper function special coefficients generated by SLICOS should be used.
To realize this function following settings must be done:Enable the testregisters (Configuration Register 5: SCR5-1 (ENTR)=1), (page 32)The testregisterblock must be load with STCR3-0 (SOFTVER) = 1, (see chapter 10.3)
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
STCR3 Test Configuration Register 3SCR3-5 (SOREV) = 1
PDADISThe automatic HV-SLIC Power Down - Active switching (see
chapter6.4) can be switched off
PDADIS = 0use automatic Power Down-Active switching
PDADIS = 1disables automatic Power Down-Active switching
DUPTo restrict the rate of upstream C/I-bit changes, deglitching (persistence
checking) of the status information from the SLICOFI may be applied.
New status information will be transmitted upstream, after it has been
stable for N milliseconds. N is binary programmable in the range of 1 toms in steps of 1 ms; with DUP = 0H the deglitching is disabled.
Reset value is 10ms.
The HOOK, SLCX and the I(O)-bits are influenced (different counters but
same programming).
Detailed info see chapter5.4.
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR4 Configuration Register 4
Configuration register SCR4 defines the basic SLICOFI settings which enable / disable
the programmable digital filters and the second tone generator.
Reset value: 00HSet transhybrid Balancing Filter – together with the bit FIXC (SCR5-5).
For FIXC = 1 the TH-Filter is set to HTH = for ZBRD;
for FIXC = 0:
TH = 0TH-filter is disabled
TH = 1TH-filter is enabled (use programmed values)Set DSP-implemented Impedance Matching Filter - together with the bit
FIXC (SCR5-5).
For FIXC = 1 the IM-Filter is set to HIM = for 900;
for FIXC = 0:
IM = 0IM-filter is disabled
IM = 1IM-filter is enabled (use programmed values)
FRXEnable FRX- (Frequency Response Transmit) Filter
FRX = 0FRX-filter is disabled (HFRX=1)
FRX = 1FRX-filter is enabled (use programmed values)
FRREnable FRR- (Frequency Response Receive) Filter
FRR = 0FRR-filter is disabled (HFRR=1)
FRR = 1FRR-filter is enabled (use programmed values)Set AX- (Amplification/Attenuation Transmit) Filter
AX = 0AX-filter is set to default value (HAX= 10 dB)
AX = 1AX-filter is enabled (use programmed values)Set AR- (Amplification/Attenuation Receive) Filter
AR = 0AR-filter is set to default value (HAR= −15.11dB)
AR = 1AR-filter is enabled (use programmed values)
ETG2Enable programmable Test Tone Generator 2
ETG2 = 0Test Tone Generator 2 is disabled
ETG2 = 1Test Tone generator 2 is enabled
PTGUser programmable frequency or fixed frequency is selected
PTG = 0fixed frequency for both Test Tone Generators
TG1 = 1008Hz, TG2 = 2kHz
PTG = 1programmed frequency for both Test Tone Generators
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR5 Configuration Register 5
Configuration register SCR5 defines various different features.
Reset value: 20H
DHP-RDisable Receive Highpass for test reasons (see chapter 10.3)
DHP-R = 0Receive Highpass Filter is enabled
DHP-R = 1Receive Highpass Filter is disabled
LAWPCM - law selection
LAW = 0A-Law is selected
LAW = 1μ-Law (μ255 PCM) is selected
FIXCThe SLICOFI uses either fixed coefficients or the programmed ones.
FIXC = 0programmed coefficients used
FIXC = 1fixed coefficients used
fixed coefficients: (see chapter 6.2)
LINLinear mode selection (16 bit linear information in voice channel A (upper
byte) and B (lower byte).
LIN = 0PCM-mode is selected
LIN = 1linear mode is selected
IDRInitialize Data RAM
IDR = 0normal operation is selected
IDR = 1contents of Data RAM is set to 0 (for test purposes)
REXTENRinging External
REXTEN = 0normal operation
REXTEN = 1used for external (unbalanced) ringing
ENTREnable Test Mode Register
ENTR = 0normal operation: the contents of the Test Registers are
permanently set to the default values
ENTR = 1the contents of the Test Registers can be changed
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
SCR6 Configuration Register 6
Configuration register SCR6 defines various test features and test loops.
Reset value: 00H
COT8Cut Off Transmit Path at 8kHz for test reasons (Input of Compression)
COT8 = 0transmit path transmission is enabled
COT8 = 1transmit path is disabled (output is zero for μ-law and
linear mode, +1 (= LSB) for A-law)
COT16Cut Off Transmit Path at 16 kHz for test reasons (Input of TH-Filter)
COT16 = 0transmit path transmission is enabled
COT16 = 1transmit path is disabled
OPIMANOpen analog Impedance Matching Loop (IMAN)
OPIMAN = 0normal operation
OPIMAN = 1opens analog IM-Loop (HIMAN=0)
OPIM4MOpen fast digital Impedance Matching Loop (IM4M)
OPIM4M = 0normal operation
OPIM4M = 1opens fast digital IM-Loop (HIM4M=0)
TEST LOOPS4 bit field for various analog and digital test loops can be set together with
LB and TM (see chapter10.3, for detailed information).
Bit76543210
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Programming the SLICOFI®
SCR7 Configuration Register 7
Configuration register SCR7 is the Mask register. With it each bit of TCR1 (Signalling
register) can be masked; that means changes of such a “masked bit” are not causing a
change of the SLCX - bit (Data Upstream C/I-channel byte).
Reset value: FFH
HOOKMMask bit for Offhook information
HOOKM = 0each change of the HOOK bit leads to an interrupt
(SLCX-bit)
HOOKM = 1changes of HOOK bit are neglected
GNKMMask bit for ground key information
GNKM = 0each change of the GNK bit leads to an interrupt
(SLCX-bit)
GNKM = 1changes of GNK bit are neglected
VB/2MMask bit for half battery information
VB/2M = 0each change of the VB/2 bit leads to an interrupt
(SLCX-bit)
VB/2M = 1changes of VB/2 bit are neglected
ICONMMask bit for constant current information
ICONM = 0each change of the ICON bit leads to an interrupt
(SLCX-bit)
ICONM = 1changes of ICON bit are neglected
TEMPMMask bit for over temperature information
TEMPM = 0each change of the TEMPA bit leads to an interrupt
(SLCX-bit)
TEMPM = 1changes of TEMPA bit are neglected
CFAILMMask bit for clock fail information
CFAILM = 0each change of the CFAIL bit leads to an interrupt
(SLCX-bit)
CFAILM = 1changes of CFAIL bit are neglected
Information about changing half battery- and constant current- information will be
neglected on both of the Power Denial and the Ringing state, and information about
changing ground key information will be neglected in the Power Denial state.
Bit76543210
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Programming the SLICOFI®
SCR8 Configuration Register 8
Configuration register SCR8 defines some Test Mode Settings and the Ground
Key/External Indication Data Upstream Persistency Counter.
Reset value: 05H
DCANALTest bit to shorten internally the IT with the V2W pin
DCANAL = 0normal operation
DCANAL = 1the DC Analog Loop is closed
CHOPACTTransforms DC-Test values to 500 Hz rectangular values at the PCM
interface
CHOPACT = 0normal operation
CHOPACT = 1chopping function is activated
DCHOLDHolds the actual DC-value at the V2W output
DCHOLD = 0normal operation
DCHOLD = 1hold DC-value at V2W
EXT_MCLK1External Masterclock (16 MHz)
EXT_MCLK1 = 0internal masterclock is used
EXT_MCLK1 = 1external masterclock is used
To use an external masterclock of 16MHz following steps must be done:IO1 must be set to input and becomes the input-pin of the
masterclock (page 42)Connect the internal clockline to IO1 and disable the PLL by setting
the bit EXT_MCLK1 = 1
DUPGNKTo restrict the rate of upstream C/I-bit changes, deglitching (persistence
checking) of the status information from the SLICOFI may be applied.
New status information will be transmitted upstream, after it has been
stable for N milliseconds. N is binary programmable in the range of 4 toms in steps of 4ms, with DUPGNK = 0h the deglitching is disabled.
Reset value is 20ms.
The HOOK bit (for external Indication) and the GNK bit are influenced.
Detailed info see chapter5.6.
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
5.4TOP Command
If no status modification of the SLICOFI is required (there is no TOP-write operation) a
transfer operation byte TOP may be transferred.Read Information: Enables reading from the SLICOFI
RW = 0No operation
RW = 1Read from SLICOFI
LSELLength select information (also see programming procedure,
chapter5.2). This field identifies the number of subsequent data bytes.
LSEL = 00Read TCR1 (Signalling Register) only
LSEL = 01Read 3 bytes of data (TCR1, TCR2, TCR3)
LSEL = 10Read extended line card design and configuration
information only (TCR4, … TCR18).
Details see chapter10.2
LSEL = 11future reserved
TCR1 Configuration Register 1
TCR1 is the Signalling register. It indicates status information. If there is any change of
one or more bit, it is indicated via the SLCX bit in the C/I-channel. Each bit can be
masked by SCR7 Register.
Reset value: 00H
HOOKLoop information On/Offhook (same as in C/I-channel)
HOOK = 0Onhook
HOOK = 1Offhook
GNKGround key or Ground start information via IL-pin (same as in
C/I-channel)
interrupt masked in Power Denial State
GNK = 0no longitudinal current detected
GNK = 1longitudinal current detected
Bit76543210
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
VB/2Half battery voltage across the HV-SLIC is detected (V2W compared toBIM/2)
interrupt masked in Power Denial and Ringing State
VB/2 = 0line voltage smaller than half battery (| V2W | > | VBIM/2 |)
VB/2 = 1line voltage larger than half battery (| V2W | < | VBIM/2 |)
ICONCurrent limitation information
interrupt masked in Power Denial and Ringing State
ICON = 0Resistive Feeding
ICON = 1Constant Current Feeding
TEMPATemperature alarm of the HV-SLIC which is signalled through the
HV-SLIC Interface (see chapter7).
TEMPA = 0normal temperature
TEMPA = 1Temperature alarm from HV-SLIC detected
CFAILClock Fail: Not the right count of clock cycles between two frame syncs
CFAIL = 0no clock fails detected
CFAIL = 1clock fails detected
The CFAIL bit is not influenced by the DUP-counter (each failure is
reported).undefined
Any change of these bits is signalled via the interrupt-bit (SLCX) in the C/I-DU-channel.
There are two types of generating an interrupt:Each toggling of a non-masked TCR1-bit combined with a DUP-counterToggling of the non-masked CFAIL-bit (no filtering by the DUP-counter)
The status information is stored in the TCR1-register by an interrupt or - if there is no
interrupt - before reading this register only.
The HOOK- and the GNK-input are directly filtered by an own DUP-/DUPGNK-counter
too and they are also directly included in the C/I-DU-channel.
Reading the TCR1-register is possible in two ways:Reading only TCR1 (TOP-command with LSEL = 0b)Reading TCR1 with other TCR-registers (TOP-command with LSEL = 0b)
The first way gives the actual status of all TCR1-inputs if the internal interrupt is not
active and actualizes the TCR1-register.
Is the interrupt active the content of TCR1-register is read and the interrupt is cleared.
The second way gives the content of TCR1-register and nothing will be changed.
The following figure shows the flow diagram of the interrupt logic.
PEB 3065
PEF 3065
Programming the SLICOFI®
Figure 8Flow Diagram of the Interrupt Logic
PEB 3065
PEF 3065
Programming the SLICOFI®
TCR2 and TCR3 Configuration Registers 2 and 3
TCR2 and TCR3 are the checksum of all the Coefficient bytes written into the Coefficient
RAM (CRAM) of the SLICOFI by the COP-Command.
TCR2
TCR3
OKCSshows, if the checksum is valid or the internal checksum calculation is
not yet finished 1)
OKCS = 0checksum is not valid
OKCS = 1checksum is valid
Algorithm of defining the checksum: x16 x10 x7 x 1
With that algorithm you can reach a fault coverage of: (1 - 2-15)
Bit76543210
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
TCR4 to TCR18: Configuration Register 4 to 18
These 15 bytes are the possible design information bytes which are described in
chapter10.2 more detailed for the extended I0M-2 Channel Identification Command
using an external ASIC.
TCR4
TCR5
TCR18
TCR4 - TCR18 show the contents of the serial input of the ASIC via IDH-pin.
Bit76543210
Bit76543210
Bit76543210
PEB 3065
PEF 3065
Programming the SLICOFI®
5.5COP Command
With a COP Command coefficients for the programmable filters can be written to the
SLICOFI Coefficient RAM or read from the Coefficient RAM via the IOM-2 interface for
verification. (Filter optimizing to different applications is supported by the software
package SLICOS.)Read / Write
RW = 0Subsequent data is written to the SLICOFI
RW = 1Read data from the SLICOFI
CODEincludes number of following bytes and filter-addresses1)
Bit765432100000TH-Filter coefficients (part 1)(followed by 8 bytes of data)0001TH-Filter coefficients (part 2)(followed by 8 bytes of data)0010TH-Filter coefficients (part 3)(followed by 8 bytes of data)0011IM-Filter coefficients (part 1)(followed by 8 bytes of data)0100IM-Filter coefficients (part 2)(followed by 8 bytes of data)0101FRX-Filter coefficients (followed by 8 bytes of data)0110FRR-Filter coefficients(followed by 8 bytes of data)0111DC-Loop coefficient (part 1)(followed by 8 bytes of data)1000DC-Loop coefficient (part 2)(followed by 8 bytes of data)1001DC-Loop coefficient (part 3)(followed by 8 bytes of data)1010TTX and DC-Loop coefficient(followed by 8 bytes of data)1011AX-Filter coefficients(followed by 8 bytes of data)1100AR-Filter coefficients(followed by 8 bytes of data)1001TG1-Filter+BP1+LM-BP
coefficients
(followed by 8 bytes of data)1110TG2-Filter+BP2 coefficients(followed by 8 bytes of data)1111Testing (levelmeter) coefficients(followed by 8 bytes of data)
PEB 3065
PEF 3065
Programming the SLICOFI®
5.6IOM®-2 Interface Command / Indication Byte
The Command/Indication (C/I) channel is used to communicate real time status
information and for fast controlling of the SLICOFI. Data on the C/I channel is
continuously transmitted in each frame until new data is to be sent.
Data Downstream C/I - Channel Byte (receive) - CIDD
Note that there is no address DD direction because there is only one SLICOFI per
IOM2-channel. This byte is used for fast controlling of the SLICOFI. Each transfer to the
SLICOFI has to last for at least 2 consecutive frames (FSC-cycles) so that it is accepted
internally. Changes (spikes) of less than 2 FSC cycles are neglected.
RINGsee table below (for details see chapter 6).
CONVsee table below (for details see chapter 6).
TIMTiming bit to control the timing of ringing or meterpulses (for details see
chapter 6).
TIM = 0SLICOFI is in the ringing pause or no meterpulse is on.
TIM = 1SLICOFI is in the ringing phase or output of a meterpulse
is running.
IO1Value for the programmable Input/Output Pin IO1 (Pin 7) if programmed
as an output pin. If the bit REXTEN (SCR5-2) is set to 1 (external ringing)
the internally created Ring Burst On Signal (for an external relay driver)
is switched to the IO1 pin instead of the IO1-bit (for more details see
chapter6 , page 51).
IO1 = 0The corresponding pin at the digital interface of the
SLICOFI is set to a logic 0.
IO1 = 1The corresponding pin at the digital interface of the
SLICOFI is set to a logic 1.
Bit765432
Table 8
PEB 3065
PEF 3065
Programming the SLICOFI®
IO2Value for the programmable Input/Output Pin IO2 (Pin 8) if programmed
as an output pin.
IO2 = 0The corresponding pin at the digital interface of the
SLICOFI is set to a logic 0.
IO2 = 1The corresponding pin at the digital interface of the
SLICOFI is set to a logic 1.Value for the fixed Output Pin O1 (Pin 39).
O1 = 0The corresponding pin at the digital interface of the
SLICOFI is set to a logic 0.
O1 = 1The corresponding pin at the digital interface of the
SLICOFI is set to a logic 1.
Data Upstream C/I - Channel Byte (transmit) - CIDU
Note that there is no address in DU direction too. This byte is used for fast transfer of the
most important and time critical informations from the SLICOFI.
HOOKIndication of the loop condition (filtered via the DUP-counter or the
DUPGNK-counter in Power Denial State).
HOOK = 0Subscriber is Onhook.
HOOK = 1Subscriber is Offhook.
GNKIndication if a ground connection is detected (filtered via the
DUPGNK-counter). The function is disabled in Power Denial State (GNK
is set to 0).
GNK = 0No ground connection detected.
GNK = 1Ground connection detected.
SLCXInterrupt bit: Summary output of the whole signalling register (TCR1) if
they are not masked - filtered via the DUP counter (see SCR7; the
interrupt logic is described in detail in chapter5.4, page 36).
SLCX = 0No unmasked bit in the signalling register has toggled.
SLCX = 1Any unmasked bit in the signalling register has toggled.
IO1Logical state of the programmable Input/Output Pin IO1 (Pin 7) - even if
not programmed as an input pin.1)
IO1 = 0The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 0.
IO1 = 1The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 1.
Bit765432
PEB 3065
PEF 3065
Programming the SLICOFI®
IO2Logical state of the programmable Input/Output Pin IO2 (Pin 8) - even if
not programmed as an input pin.1)
IO2 = 0The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 0.
IO2 = 1The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 1.Logical state of the programmable Input Pin I1 (Pin 38).
I1 = 0The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 0.
I1 = 1The corresponding pin at the digital interface of the
SLICOFI is receiving a logic 1.
The DUP- (DUPGNK) - counters filter the status-information and the input-pin I1
respectively. The counters count down and generate enable-signals for the registers if
they are zero. Then they start counting again at the programmed value. If a
status-information or an input-signal changes the proper counter is set and continues
counting down. There are three different DUP-counters for HOOK, SLCX and the
input-pin and one DUPGNK-counter for HOOK in PDen-mode or GNK in all other modes.
Changing the mode freezes the actual status of HOOK and sets the actual
HOOK-counter.
PEB 3065
PEF 3065
Operating ModesOperating Modes
The SLICOFI supports 4 different Operating Modes: Power Denial (PDen), Power Down
(PDown), Active and Ringing which are controlled via the upper 3 bits of the Data
Downstream C/I channel byte (CIDD).
Table 9
PEB 3065
PEF 3065
Operating Modes
Figure 9
PEB 3065
PEF 3065
Operating Modes
6.1Reset Behavior
The SLICOFI has 3 different reset sources that are all internally connected.
The Reset pin RES (pin 36), which works totally asynchronous to the external clocks.
The Reset bit (Within SOP - command, bit 4). The reset is valid for SOP-write only.
Power On Reset. If internal VDDD gets above 1.5 Volts the SLICOFI is Reset by Power
On Reset.
All 3 different sources set the SLICOFI to the basic setting modes (see below).
After a reset caused by any of the sources mentioned above, the reset bit
(SCR0-4 = RSTST) in read direction is set to one. This bit is cleared (RSTST = 0) after
it has been read by a SOP-read operation with the LSEL bits set to 00b (means: read
only SCR0 byte). A SOP-read with other LSEL bits reads the actual RSTST value, but
does not clear it.
The Reset pin RES has a Schmitt-Trigger input to reduce the sensitivity for spikes. In
addition the pin RES has a spike rejection. All spikes smaller than typ. 70 ns are
neglected. The pin RES can be set to 1 for an unlimited time but at least 125μs is
recommended; during that, the DU pin is set to high impedance.
The SLICOFI leaves this mode automatically with the beginning of the next 8kHz-frame
(or after pin RES is released).
6.2Basic Setting Modes
After RESET, the SLICOFI automatically is switched to its basic settings in which it uses
internal default values for all filters and settings (AC and DC), so that the SLMA still
works in a kind of “emergency mode” and can be handled by C/I-Interface commands
only.
This means that for an (un-)determined reset (e.g. Power On Reset) the SLICOFI is
reset, but can be switched to or return automatically to any operating mode presented to
the C/I-channel after 2 FSC cycles. In all modes the SLMA stays stable, supervision and
DC-feeding are still working and conversation can go on in a proper way until all filters
and settings have been reloaded by SOP and COP-commands.
So what happens internally after resetall configuration registers are set to their default values (note that the Coefficient RAM
is not reset)the RSTST-bit (SCR0-4) is set to 1 to indicate that a reset has taken placeThe IOM-2 interface is reset. Running communication is stoppedDU is in high impedance stateAC- and DC-loop use the default values and not the programmed ones (see below)
PEB 3065
PEF 3065
Operating Modes
Boosted Battery is reset to normal feeding
Reverse Polarity is reset to Normal Polarity
all bits of the Signalling Register are masked and reset to 0
the Data Upstream C/I channel byte is reset to 0 (and IO’s are set to Input pins)
C1 and C2 are set to PDNR and PDN is set high
A-Law is chosen
Table 10DC
Table 11AC
PEB 3065
PEF 3065
Operating Modes
6.3Power Denial (PDen)
After a Reset (including the Power On Reset) the SLICOFI is set to Power Denial State.
In Power Denial all functions that are not necessary are disabled to minimize power
consumption. Via the two pins VLINE1 and VLINE2 the SLICOFI is directly connected to the
a - and b - wire, while the PDN-Pin is set high (which turns off the HV-SLIC). While the
interface is fully working - including programmability of the registers with SOP- or TOP
commands and the Coefficient RAM (COP commands) the rest of the SLICOFI is turned
off except the supervision of the line. The change of the line state is reported via the
HOOK-bit in the IOM-2 Data upstream channel. To avoid spurious Offhook - informations
caused by longitudinal induction the HOOK - bit is low pass filtered (programmable with
the DUPGNK - counter in PDen state only). The HV-interface pins C1, C2 are switched
off. The voice channel Data Downstream is directly fed into the voice channel Data
Upstream. The HOOK-indication in PDen is optimized for longitudinal suppression up toVrms for the Offhook transition.
6.4Power Down (PDown)
In Power Down Mode the DC-Loop of the SLICOFI is fully working; the AC-Loop is still
turned off. The output voltage at the V2W pin is controlled via the IT input in such a way
that it behaves like a programmable constant current source. Current limitation is used
for detecting Offhook, too. The change of the line state is reported via the HOOK-bit in
the IOM-2 Data upstream channel. To avoid spurious Offhook-informations the
HOOK-bit is lowpass filtered (programmable with DUP-counter).
The ternary HV-interface (C1, C2) is set to Power Down mode. If Offhook is detected the
HV-interface is set to one of the active modes. This can be avoided by setting
PDADIS=1 (SCR3-4). Then the HV-SLIC interface is set to Power Down anyway.
The longitudinal current supervision via the IL pin is activated in this mode.
The voice channel Data Downstream is directly fed into the voice channel Data
Upstream.
Together with the bits Hi-a and Hi-b of the configuration register 1 (SCR1-2 and SCR1-3)
simple handling of Ground Start function is possible.
Table 11AC (cont’d)
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PEF 3065
Operating Modes
6.5Active Mode (Act)
In Active Mode (“Conversation State”) both AC-and DC-Loop are fully working. The
output voltage at the V2W pin is controlled via the IT input pin in such way, that it behaves
like a constant current source which turns automatically into a programmable resistive
feeding source due to the DC-Characteristic values (see chapter3.2, page 13 for more
details).
The ternary HV-interface is set to one of the active modes.
Polarity
The SLICOFI supports either normal or reverse Polarity which is set by the POLNR-bit
(SOP-5). The information is transferred to the HV-Interface and simultaneously a
180degree phase shift of the AC- and DC-Loop is done. The performance and the
functionality is not influenced by that.
Boosted Battery
To feed subscriber lines with enhanced loop resistance the SLICOFI supports the
Boosted Battery mode. The HV-Interface pins are set to Boosted Battery (BB) mode and
the maximum V2W output voltage is extended to −3.2V.
Meterpulses
The SLICOFI supports two different kinds of meterpulses: Meterpulses with 12/16kHz
(Teletax Metering) and with polarity reversal. In the Active Mode the Timing bit (TIM)
Table 12
Pin No./Pin Name
PEB 3065
PEF 3065
Operating Modes
these two ways is made by the bit TTXNO (SCR3-7). If bit TTXNO is set to 1, then the
meterpulse is reversal. In this case the Timing bit is linked to POLNR (SOP-5) by an
EXOR gate. If bit TTXNO is set to 0, then the Timing bit and POLNR are completely
independent from another and Teletax Metering is used.
Metering with Polarity Reversal
Hard or Soft (SOREV, SCR 3-5)
As long as the TIM bit of the C/I-channel is set to 1, the SLICOFI is changing the actual
polarity of the HV-Interface and performs an immediate 180degree phase shift of the
AC- and DC-Loop.
Teletax Metering Injection
For countries with Teletax Metering, the SLICOFI provides either a 12 or 16kHz Signal
(switchable with the bit TTX12 (SCR3-6))1) which amplitude is free programmable up to
250 mVrms at V2W. The SLICOFI filters the Teletax pulses in transmit direction, too. The
slope of the pulses are internally shaped, so that the noise during switching and
transmission is less than 50mV at V2W and 1mV at the IOM-2 interface
(psophometrically weighted). With the bit NOSL (SCR2-2) the slope can be switched off.
In that case the switching noise is not defined (for signalling only).
6.6Ringing Mode
The SLICOFI generally supports balanced ringing.
If the SLICOFI is set to Ringing Mode, the HV-Interface is set to Ringing Mode, the
AC-loop is turned off and the DC-Loop is automatically opened.
The voice channel Data Downstream is directly fed into the voice channel Data
Upstream.
Balanced Ringing
The sine wave of the ringing is generated in the SLICOFI. The frequency and the
amplitude are free programmable between 16 and 70Hz and up to 2.125 Vrms at V2W,
respectively2). In Ring Pause 0V is provided at V2W. If the Ring Burst On (RBO)
command is sent to the SLICOFI via the C/I-channel (RING and TIM = 1) the begin and
end (TIM = 0) of the ring burst is automatically synchronized at the voltage zero crossing.
If the DC-current at the IT-pin exceeds the programmed value, Offhook is detected within
2 periods of the ringing frequency and the Ring Burst at V2W is switched off withinperiods. During Offhook the Ring Burst On command is neglected.
