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MTSXL (Memory Time Switch Extended La...
ICs for Communications
Memory Time Switch Extended Large
MTSXL
PEB 2447 Version 1.2
Data Sheet03.97
Edition 03.97This edition was realized using the software system FrameMaker.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München© Siemens AG 1997.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or
the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales
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For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
PEB 2447
Table of ContentsPage
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.4Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.5Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.1General Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2.1Control Memory Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2.2Evaluate Frame Measurement Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.2.3MTSXL Selftest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.3Boundary Scan and TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3.1Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3.2TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.3.3Use of Built in Selftest via the Boundary Scan Interface . . . . . . . . . . . . . . . .19
2.3.4IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.1Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3Indirect Access Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.4Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5Input Offset and Output Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3.6Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.1Register Address Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
4.2Mode Register (MODR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
4.3Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
4.4Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
4.5Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.6Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
4.7Memory Access Address/Code Register High (MACH) . . . . . . . . . . . . . . . . .37
4.8Memory Access Address Register Low (MAAL) . . . . . . . . . . . . . . . . . . . . . .38
4.9Memory Read Data Register Low (MRDL) . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.10Memory Read Data Register High (MRDH) . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.11Memory Write Data Register Low (MWDL) . . . . . . . . . . . . . . . . . . . . . . . . . .39
4.12Memory Write Data Register High (MWDH) . . . . . . . . . . . . . . . . . . . . . . . . .40
4.13Input Clock Shift Register Bank ICSR (15:0) . . . . . . . . . . . . . . . . . . . . . . . . .41
4.14Output Clock Shift Register (OSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.15Test Register (TSTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
4.16Frame Evaluation Register Low (FERL) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
4.17Frame Evaluation Register High (FERH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Memory Time Switch Extended Large
MTSXL
PEB 2447
1Overview
1.1FeaturesNon blocking time/space switch for 4.096- or
8.192-Mbit/s PCM systemsDevice clock 16.384 MHzSwitching of up to 2048 incoming PCM channels to
up to 2048 outgoing PCM channels32 input and 32 output PCM linesTristate function for further expansion and tandem operationμP read access to PCM dataProgrammable clock shift with half clock step resolution for input and outputIndividual line delay measurement for 6 additional inputsIndividual input offset programmable for 16 PCM inputsBoundary scan (fully IEEE1149.1 compatible)Built-in selftest (also usable via boundary scan interface)8-bit Intel type demultiplexed μP interfaceAll registers accessible by direct addressingIn-operation adjustment of bit sampling without bit errorsLow power consumptionSingle 5 V power supply
PEB 2447
Overview
1.2Logic Symbol
Figure 1
Functional Symbol
1.3General Device OverviewThe Siemens Memory Time Switch Extended Large MTSXL (PEB 2447) is a capacity
expansion of the MTSL (PEB 2047). It is a monolithic CMOS switching device capable
of connecting maximally 2048 PCM input time slots to 2048 output time slots. In order to
manage the problem of different line delays, six additional FS inputs can be used as
frame measurement inputs and 16 different input offsets of PCM frames are allowed.
Thus a frame wander can be compensated by adjusting the input offset during operation.
A special circuitry guarantees that no bit error will occur, when reprogramming the input
offsets.
The MTSXL on chip connection memory and data memory are accessed via the 8-bit
standard μP interface (Intel demultiplexed type).
A built-in selftest mechanism – also activated by the μP – ensures proper device
operation in the system.
The PEB 2447 is fabricated using the advanced CMOS technology from Siemens and is
mounted in a P-MQFP-100-2 package. Inputs and outputs are TTL compatible.
PEB 2447
Overview
1.4Pin Configuration(top view)
Figure 2
1.5Pin Definitions and Functions
PEB 2447
Overview
1.5Pin Definitions and Functions (cont’d)
PEB 2447
Overview
1.5Pin Definitions and Functions (cont’d)
PEB 2447
Overview
1.5Pin Definitions and Functions (cont’d)
PEB 2447
Overview
PEB 2447
Functional DescriptionFunctional DescriptionThe MTSXL is a memory time switch device. Operating with a device clock of
16.384MHz it can connect any of 2048 PCM input channels to any of 2048 output
channels.
A general block diagram of the MTSXL is shown in figure 3.
2.1General OperationThe input information of a complete frame is stored twice in the two on-chip 16-kbit data
memories DM 0 and DM 1 (Data Memory 0 and Data Memory 1). The incoming
2048channels of 8 bits each are written in sequence into fixed positions of DM 0 and
DM 1. This is controlled by the input counter in the timing control block with a 8 kHz
repetition rate.
For outputting, two connection memories (CM 0 and CM 1) are read in sequence
synchronously. Each entry in the connection memory CM 0 / CM 1 points to a location
in data memory DM 0 /DM1. The byte in this data memory location is transferred into
the current output time slot. The read access to the CM’s is controlled by an output
counter. CM 0 supplies the PCM data for outputs OUT0 to OUT15, CM 1 supplies the
PCM data for outputs OUT16 to OUT31.
PEB 2447
Functional Description
Figure 3
Block Diagram of MTSXLThe synchronization of the input and output counters is achieved by a rising edge of the
sync pulse SP, which is always sampled with the falling edge of the device clock.
Different modes of operation are configurable at the PCM interfaces (see
table 9).Furthermore, 16 PCM input lines can be aligned with individual clock shift values to
compensate different line delays. If 32 inputs are used, one clock shift value controls two
ports at the same time.
Shifting of the output frame is also possible, but all output lines are affected the same
way.
The input lines FS0 to FS5 are used as frame measurement inputs. After synchronizing
the device by the SP pulse the FS inputs can be evaluated on a per port basis. This
evaluation procedure is started by a microprocessor command. As a result the input
counter value on the rising edge of the FS signal can be read from an internal register.
Thus delay compensation is easily managed by programming appropriate clock shift
PEB 2447
Functional DescriptionDuring operation of the chip a frame length check is also supplied, which controls correct
synchronization by the SP pulse and generates an interrupt in case of lost or achieved
synchronization.
The unused output ports are tristated by mode selection, whereas unused time slots are
tristated by an additional bit in the control memory. By using this tristate capability the
MTSXL can be easily expanded to a time switch of any size.
The standard 8-bit μP interface can communicate with Intel demultiplexed
microprocessors. It gives access to the internal registers and to the control and data
memory. All registers are directly addressable. The memories are accessed by a simple
four byte indirect access method.
2.2Special FunctionsThe activity of all special functions can be read in the status register. Completion of these
functions is indicated by interrupts.
2.2.1Control Memory ResetInitialization of the device after a hardware reset (RES) is easily done with a μP
command “control memory reset”. After finishing this procedure all control memory
channels contain the information “tristated”. Apart from this tristate information the
contents of the C Memory is undefined.
2.2.2Evaluate Frame Measurement SignalA command including the address (0 … 5) will be given by the μP. The rising edge of the
corresponding frame measurement signal (FS0 … FS5) will be evaluated. The exact
timing of the FS edge can then be read from an internal 12-bit register (resolution of a
complete 8 kHz frame in half 16 MHz clock periods).
2.2.3MTSXL SelftestThe switching path of the MTSXL including input buffer, data memory, control memory,
output buffer and timing control can be tested in the system by a 2-step built-in selftest.
Activating this mechanism takes 2 × 0.625 ms (16.384 MHz). Finally the result “selftest
ok/selftest not ok” can be read from the internal status register.
After test completion the control memory has also been reset (contains the information
tristated).
The selftest can also be started and checked via the boundary scan interface.
Note:For correct execution of the built-in selftest the MTSXL needs a value of
ICSR=00. If MODR:PSB = 0 (e.g. after hardware reset) this value is programmed
automatically after start of the selftest procedure. If ICSR does not contain “00”
with MODR:PSB = 1 the selftest will fail.
PEB 2447
Functional Description
2.3Boundary Scan and TAP Controller
2.3.1Boundary ScanThe MTSXL provides fully IEEE Std. 1149.1 compatible boundary scan support
consisting of a complete boundary scana test access port controller (TAP controller)four dedicated pins (TCK, TMS, TDI, TDO)a 32 bit IDCODE register
All pins except power supply and ground are included in the boundary scan. Depending
on the pin functionality one, two or three boundary scan cells are provided:
When the TAP controller is in the appropriate mode data is shifted into / out of the
boundary scan via the pins TDI / TDO using the 6.25 MHz clock on pin TCK.
The MTSXL pins are included in the boundary scan in the following sequence:
Table 1
Boundary Scan Cell Type
Table 2
Boundary Scan Sequence
PEB 2447
Functional Description
Table 2
Boundary Scan Sequence (cont’d)
PEB 2447
Functional Description
Table 2
Boundary Scan Sequence (cont’d)
PEB 2447
Functional Description
Table 2
Boundary Scan Sequence (cont’d)
PEB 2447
Functional Description
2.3.2TAP ControllerThe TAP controller implements a state machine defined in the JTAG standard
IEEE1149.1. The instruction register of the controller is extended to 4 bits in order to
increase the number of instructions. This is necessary for the use of the build in selftest
procedure via the boundary scan interface:
The standard instructions are implemented according to the JTAG standard, just the
instruction register is extended to 4 bits. At the new instructions TAP_TEST1.. 8 special
internal test signals are activated during the state “RUN TEST / IDLE”.
The MTSXL only uses TAP_TEST1 and TAP_TEST2 according to table 3.
Table 3
Instruction Code of 4 Bit TAP Controller
PEB 2447
Functional DescriptionThe extended TAP controller uses a modified data path:
When TAP_TEST1 / 2 is activated the data path is set to shift the result of the selftest
procedure (bit STAR:STOK) out through the TDO pin.
2.3.3Use of Built in Selftest via the Boundary Scan InterfaceThe built in self test is used by the following steps:The instruction TAP_TEST2 is shifted into the TAP controller (see figure 4)STP command is shifted into the selftest control register (see table 5 and figure 5)The instruction TAP_TEST1 is shifted into the TAP controller to start the selftest
(see
figure 6) after 10240 TCK periods: Bit STAR:STOK can be shifted out (see figure 7).
Note:
ST [2:0] represent the bits CMDR:STP2..0 but do not overwrite them.
Table 4
Data Path of 4 Bit TAP Controller
Table 5
4 Bit Selftest Control Register
PEB 2447
Functional DescriptionThe TAP controller state machine passes through the different states according to
figures4 to 7. Note:The state coding is only described for explanation purposes, it is externally not
visible.
Table 6
States of TAP Controller (explanation for figures 4 to 7)
PEB 2447
Functional Description
Figure 4
Starting Instruction “TAP_TEST2” (code 0101)
Figure 5
Writing Selftest Control Register
PEB 2447
Functional Description
Figure 6
Start of Built in Selftest (instruction TAP_TEST1, code 0100)
Figure 7
Readout of Selftest Result (after 10240 TCK periods)Note:After the use of the selftest procedure over the μP Interface or the boundary scan
interface a hardware reset is necessary before the selftest procedure can be
started again over the other interface.
2.3.4IDCODEThe manufacturer code for MTSXL is according to table 2:
PEB 2447
Operational DescriptionOperational Description
3.1Initialization ProcedureFor a proper initialization of the MTSXL the following procedure is recommended:
First a reset pulse (RES) of at least two CLK clock periods has to be applied. All registers
contain now their reset values. In the next step the connection memories CM0/1 are
initialized by the commands CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP
(2:0)=011/111 (MTSXL selftest).
After having programmed a CM reset command, it takes 4096 clock periods until all
tristate control entries in the CM contain the value “1” (tristated).
If a selftest command was given, it takes 10240 clock periods to achieve the same
effect. Furthermore the register bit STAR:STOK (selftest o.k.) should read “1” in this
case, in order to prove that there is no fault on the chip. The selftest command must be
given twice: the upper half of data memory (DM0, DM1) is tested when setting
CMDR:STP (2:1)=01, the lower half of DM0, DM1 is tested by setting CMDR:STP
(2:1)=11 (see table 10).
The activity of the procedures can be monitored in STAR:PACT and an interrupt will
indicate their completion.
In all cases it is important, that the outputs are tristated by MODR:PSB = 0.
3.2Operation ModeThe operation mode of the device is fixed by programming MODR:MD (1:0) (see
table9).
3.3Indirect Access RegistersThe connection memories and data memories are accessible through the indirect access
registers MACH, MAAL, MRDH, MRDL, MWDH and MWDL. An indirect access is
actually started by writing register MACH (Memory Access Address/Code Register
High). The code value inherent in this register defines, what action has to be performed.
The low byte of the complete access address must be programmed to MAAL (Memory
Access Address Register Low) before writing to MACH. If data are necessary to perform
the access (e.g. in write operations), they have to be entered into MWDH (Memory Write
Data Register High) and MWDL (Memory Write Data Register Low) before. In read
accesses the corresponding registers MRDH (Memory Read Data Register High) and
MRDL (Memory Read Data Register Low) contain the required information after the
internal read process is completed.
PEB 2447
Operational DescriptionTypical Write Operation:Typical Read Operation:
WR MWDLWR MAAL
WR MWDHWR MACH
WR MAALRD STAR; STAR:MAC = 0
WR MACHRD MRDL
RD STAR; STAR:MAC = 0RD MRDH
3.4Frame EvaluationIf the device is in synchronized state (STAR:PSS = 1) and for example the command
“frame evaluation at FS5” (CMDR = 58H) is programmed, the second following rising
edge of FS5 is evaluated and creates the following result in register FERH:FERL (see
also table 15):
Figure 8
Frame EvaluationNote:The frame evaluation procedure gives (roughly) the number to be programmed in
ICSR (after inversion of FER0): FEV11..1 give the number of complete CLK
periods; FEV 0 gives the sampling edge (falling / rising). Due to the internal delay
in the MTSXL the sampling region and therefor the result in FEV11..1 is shifted
against CLK for a time “X” which is uncertain between 0
edge of FS occurs in that uncertain region the value of FER11..1 might vary + 1
(FER0 inverted before!).
PEB 2447
Operational Description
3.5Input Offset and Output Offset
Based on the results of the frame evaluation procedures the input offsets can be
adjusted by programming ICSR7..0 corresponding to inputs IN7..0. If data
oversampling is used, the values of ICSR7..0 can be adjusted within some limits during
operation without producing bit errors:clockrate = 2 × datarate
possible adjustment is one half clock period forward or backward.clockrate = 4 × datarate
possible adjustment is one clock period backward or two clock periods forward.
Figure 9
Input Timing
PEB 2447
Operational Description
