PEB2095NVA5 . ,IBC (ISDN Burst Transceiver Circuit)applications, pro-cesses and circuits implemented within components or assemblies.The information d ..
PEB2096 ,ICs for Communications Extended PCM Interface Controllercharacteristics.Terms of delivery and rights to change design reserved.Due to technical requirement ..
PEB22320N V2.1 ,PRACT (Primary Rate Access Clock Gene...Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB22320N V2.1 ,PRACT (Primary Rate Access Clock Gene...Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB22320NV2.1 ,PRACT (Primary Rate Access Clock Gene...ICs for CommunicationsPrimary Rate Access Clock Generator and TransceiverPRACTPEB 22320Version 2.1D ..
PEB22320NV2.1 ,PRACT (Primary Rate Access Clock Gene...Characteristics31 Recommended Oscillator Circuits32, 33 Crystal Tuning RangeData ClassificationMaxi ..
PIC17C42A , High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
PIC18F2525-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SP , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F4620-I/ML , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PEB2095NVA5-PEB2095NVA5 .-PEF2095NVA5
IBC (ISDN Burst Transceiver Circuit)
ICs for Communications
Octal Transceiver for DASL Compatible Interfaces
OCTAT-P
PEB 2096 Version 2.1
Addendum05.98 to the Data Sheet 01.96
DS 1
Edition 05.98This edition was realized using the software system FrameMaker.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München Siemens AG 1996.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, pro-
cesses and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Com-
panies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please con-
tact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement
we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs
incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the
express written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause
PEB 2096Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42.1Device Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2.2.1General Principle of the DASL Compatible Interface . . . . . . . . . . . . . . . . . . . .4
2.2.2IOM-2 System Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.2.3JTAG Boundary Scan Test Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3Individual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3.1Transceiver, Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.3.2Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2Clocking, Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3Push – Pull Sensing on Pin DU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.4Transmit Delay on DASL Compatible Interface with respect to IOM®-2 Inter-
face 8
3.5DASL Compatible Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5.1Synchronization with a Short FSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.5.2Synchronization using SSYNC (for DECT) . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.6D-Channel Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.7IOM®-2 Interface Monitor Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.8Command / Indicate Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.9Activation and Deactivation, State Machine . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.9.1States Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.9.2Info Structure on the DASL Compatible Interface . . . . . . . . . . . . . . . . . . . . .13
3.9.3Example of Activation and Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.1Identification Register – (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2General Configuration Register – (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3Bit Error Register – (Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4Configuration Register for DASL compatible Line Interfaces – (Write) . . . . .16
4.5Test Registers – (Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.6Mode Register – (Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PEB 2096OverviewThe Octal Transceiver for DASL compatible interfaces, OCTAT-P, PEB 2096,
implements the two-wire DASL compatible interface used to link voice/data digital
terminals to PBX subscriber lines. The OCTAT-P is an optimized device for LT
applications and can handle up to eight DASL compatible interfaces simultaneously.
The OCTAT-P is a CMOS device offered in a P-MQFP-44 package.
Functional DescriptionThe PEB 2096, OCTAT-P, performs the layer-1 functions of the ISDN basic access for
eight DASL compatible interfaces at the LT side of the PBX.
2.1Device ArchitectureThe OCTAT-P contains the following functional blocks:Eight line transceivers for the DASL compatible interfacesOne IOM-2 interface Frame structure converter between the IOM-2 interface and the DASL compatible
interfacesJTAG Boundary scan interfaceClocking, reset and initialization block
2.2Interfaces
2.2.1General Principle of the DASL Compatible InterfaceA frame transmitted by the exchange (LT) is received by the terminal equipment (TE)
after a given propagation delay (td). Refer to figure 1. The terminal equipment waits a
guard time of six bits (tg=15.6 μs) while the line clears. It then transmits a frame to the
exchange. The exchange begins a transmission every 250μs (known as the burst
repetition period). However, the time between the reception of a frame from the TE and
the beginning of transmission of the next frame by the LT must be greater than the
minimum guard time. Communication between an LT and a PT (Private Termination)
follows exactly the same procedure.
Note that the guard time in TE is always defined with respect to the last D-bit.
PEB 2096
Figure 1
DASL Compatible Interface Frame StructureWithin a burst, the data rate is 384 kbit/s. The 37-bit frame structure is as shown in
figure1. The framing bit (LF) is always logical ‘1’. The frame also contains the userchannels (2B+D).
It can readily be seen that in the 250 μs burst repetition period, 4 D bits, 16 B1 bits and
16 B2 bits are transferred in each direction. This results in an effective full duplex data
rate of 16 kbit/s for the D channel and 64 kbit/s for each B channel.
The OCTAT-P scrambles B- and D-channel data on the DASL compatible interface in
order to ensure that the downstream receiver gets enough pulses for a reliable clock
extraction (flat continuous power density spectrum is provided) and no periodic patterns
appear on the line.
The scrambling polynomial is: x9 + x5 + 1.
The coding technique used on the U interface is a AMI code. A logical ‘0’ corresponds to
a neutral level, logical ‘1’ are coded as alternate positive and negative pulses.
PEB 2096See figure 2. The AMI coding includes always the data bits going on the DASL
compatible interface in one direction. Thus there is a separate AMI coding unit for data
downstream and one for data upstream.
Figure 2
AMI Coding on the DASL compatible Interface
2.2.2IOM-2 System InterfaceUnchanged
2.2.3JTAG Boundary Scan Test Interface
IDCODEThe 32-bit identification register is serially read out via TDO. It contains the version
number (4 bits), the device code (16 bits) and the manufacture code (11 bits). The LSB
is fixed to “1”.
Note:In the state “test logic reset” the code “0011” is loaded into the instruction code
register.
VersionDevice CodeManufacture CodeOutput--> TDO
PEB 2096
2.3Individual Functions
2.3.1Transceiver, Analog Connections
Figure 3
External Circuitry for DASL Compatible InterfaceThe PEB 2096, OCTAT-P, covers the electrical requirements of the DASL compatible
interface for loop lengths depending on the used transformer and the cable quality:
Note:The actual values of the external resistors depend on the selected transformer.
The resistor values in figures 3 are tbd.
2.3.2Diagnostic FunctionsLoop 2 is no longer supported.
PEB 2096Operational Description
3.1GeneralAll procedures required for data transmission over the DASL compatible interface are
implemented. These comprise the DASL compatible interface frame synchronization,
activation/deactivation procedure, and timing requirements such as bit rate and jitter.
3.2Clocking, Reset and InitializationUnchanged
3.3Push – Pull Sensing on Pin DUUnchanged
3.4Transmit Delay on DASL Compatible Interface with respect to IOM®-2
InterfaceThe OCTAT-P causes delays of B- and on D-channels with respect to the IOM channel
number. Figure 4 shows this delay at a data rate of 2.048 Mbit/s.
Figure 4
Transmit Delay of B- and D-Channels
PEB 2096
3.5DASL Compatible Frame SynchronizationThere are two possibilities how to synchronize the DASL compatible frame to the IOM-2
frame: With a short FSC or with SSYNC.
3.5.1Synchronization with a Short FSCThe short FSC pulse has a width of one DCL clock (in normal use the FSC is at least 2
DCL wide). The SSYNC input must be set to 1. The period of the short FSC pulses must
be a multiple of 250 μs. The DASL compatible transmit frame starts in the IOM channel0
which follows the short FSC pulse. Refer to figure 5.
Figure 5
Synchronization with a short FSC
3.5.2Synchronization using SSYNC (for DECT)A zero pulse on the SSYNC input forces the OCTAT-P to start a frame at the beginning
of this IOM frame. Refer to figure 6.
Figure 6
Synchronization with SSYNCWhile using SSYNC for DASL compatible frame synchronization the short FSC signal is
not allowed. If not used, the SSYNC input must be connected to VDD.
