PEB2075NV1.3 .. ,IDEC (ISDN D-Channel Exchange Control...Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB2075NV1.3 ... ,IDEC (ISDN D-Channel Exchange Control...characteristics specify mean values expected over the production spread. If not otherwise specified ..
PEB2075PV1.3 ,IDEC (ISDN D-channel Exchange Control...Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB2080NVB1 ,SBC (S-Bus Interface Circuit)Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB2080PVB1 ,SBC (S-Bus Interface Circuit)Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PEB2081 NV3.4 ,SBCX (S-Bus Interface Circuit extended)applications, processes and cir-cuits implemented within compo-nents or assemblies.The information ..
PIC16F883 , 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
PIC17C42A , High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
PIC18F2525-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SP , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PEB2075NV1.3-PEB2075N-V1.3-PEB2075NV1.3 ..-PEB2075NV1.3 ...-PEB2075PV1.3
IDEC (ISDN D-Channel Exchange Control...
ICs for Communications
ISDN D-Channel Exchange Controller
(IDEC®)
PEB 2075
Data Classification
Maximum RatingsMaximum ratings are absolute ratings; exceeding only one of these values may cause irreversible
damage to the integrated circuit.
CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit. Typical
characteristics specify mean values expected over the production spread. If not otherwise specified,
typical characteristics apply at TA=25 °C and the given supply voltage.
Operating RangeIn the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about “Processing Guidelines” and “Quality Assurance” for
ICs, see our “Product Overview”.
Edition 05.92This edition was realized using the softwaresystem FrameMaker ®.
Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation,
Balanstraße 73, D–8000 München 80. Siemens AG 1992. All Rights Reserved.
As far as patents or other rights of third parties are concerned, liability is only assumed for components per se,
not for applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery, and prices please contact the Offices of Semiconductor Group in Germany
or the Siemens Companies and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the type in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PEB 2075
Table of ContentsPageFeatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.3System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152.1General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . . . . .15
2.2Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.3Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.4Individual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.1Channel Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.4.2HDLC Communication Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2.4.3Collision Control and Switching Functions . . . . . . . . . . . . . . . . . . . . . . . .33
2.4.4Test Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
2.5Preprocessed Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .433.1Microprocessor Interface Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
3.3Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.4Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.5Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Detailed Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534.1Register Address Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
4.2Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69Appendix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
ISDN D-Channel Exchange ControllerPEB 2075
(IDEC®)
CMOS ICFeaturesFour independent HDLC channels64-byte FIFO storage per channel and directionHandling of basic HDLC functions
flag detection/generation
zero deletion/insertion
CRC checking/generation
check for abortAddress recognitionC/I channel handlerSingle connection and quad connection modesIOM® interface or PCM interfaceProgrammable time slots and channel data rates (up to
4Mbit/s)Different methods of contention resolutionStandard μP- interface, multiplexed or non-multiplexed
address and data busesVectored interruptAdvanced CMOS technologyPower consumption less than 50 mW during operation.
The ISDN Digital Exchange Controller PEB 2075 (IDEC) is a serial HDLC data communication
circuit with four independent channels. Its telecommunication specific features make it especially
suited for use in variable data rate PCM systems. In addition, the device contains sophisticated
switching functions and it implements automatic contention resolution between packet data from
different sources.
Its applications include: communication multiplexers, peripheral ISDN line cards, packet handlers
and X.25 packet switching devices. The IDEC is a fundamental building block for networks with
either centralized, de-centralized or mixed signaling/packet data handling architectures.
Features
1.2Pin Definitions and Functions
Pin Definitions and Functions (cont’d)
Features
Logic Symbol
Features
1.3System Integration
Communication Multiplexers
The four independent serial HDLC communication channels implemented in the IDEC make the
circuit suitable for use in communication multiplexers.
The collision detection/resolution capability of the circuit allows statistical multiplexing of packets in
one or several physical data communication channels, for example in DMI (mode 3) applications.
Centralized Signaling/Data Packet Handlers
The IDEC can be used in central packet handlers of ISDN networks to process signaling or packet
data of four ISDN subscribers. In this application, it may be used with or without the Extended PCM
Interface Controller (EPlC®) PEB 2055.
The IDEC can be connected to the IOM interface of the EPIC, which is itself connected to the PCM
system highway. The EPIC implements concentration and time slot assignment functions. As an
alternative, the IDEC may be directly connected to PCM highways (figure 1).
The size (from 1 to 8 bits) and the position of the time slot associated with each HDLC controller is
software programmable. In addition to the receive and transmit data highways, the IDEC accepts a
third input connection for collision detection purposes. The mode of collision detection is
programmable. A "collision highway" (or time slot) can be used for remote collision control, as a
"clear to send" lead, or for local contention resolution among several IDECs.
Figure 1
Use of IDEC® in Central Signaling/Data Packet Handlers
Features
Line Cards in De-Centralized or Mixed Signaling/Data Packet Handling Architectures
The IDEC can be used on peripheral line cards to process D-channel packets for ISDN subscribers.
The PCM Controller PEB 2055 has the layer-1 controlling capacity and a B-channel switching
capacity for a total of 32 subscribers. The B and D channels and the control information for eight
subscribers are carried by one IOM interface. Thus a line card dimensioned for 32-ISDN
subscribers may employ up to eight IDECs, two for each IOM connection (figure 2). A High Level
Serial Communication Controller (HSCX) SAB 82525 with two HDLC channels, or another IDEC
may be used to transmit and receive signaling via the system highway in a common channel. Again,
such a common channel may be shared among several line cards, due to the statistical multiplexing
capability of these controllers.
In completely de-centralized D-channel processing architectures, the processing capacity of a line
card is usually dimensioned so as to avoid blocking situations even under maximum conceivable
D-channel traffic conditions. It may sometimes be more advantageous to perform p-packet handling
in a centralized manner while keeping s-packet handling on the line cards. A statistical increase in
p-packet traffic has then no effect on the line card, and can be easily dealt with by one of the
modular architectures for a central packet handler shown in the previous section. A more effective
sharing of the total p-packet handling capacity is the result, especially in a situation where p-packet
traffic patterns vary widely from one subscriber group to another.
The use of an IDEC in the mixed D-channel processing architecture is illustrated in figure 3.
The additional "transparent data" connections supported by the IDEC enable a merging of p and s
packets into one D channel. Possible collision situations are dealt with by the IDEC which uses
either the additional collision detect line (figure 3) or a time slot on the system highway (figure 3)
from the line card to the central packet handler.
Figure 2
Line Card in a De-Centralized D-Channel Handling Architecture
Features
Figure 3
IDEC® on a Line Card in a Mixed D-Channel Processing Architecture
Functional DescriptionFunctional Description
2.1General Functions and Device Architecture
The IDEC is an HDLC controller which handles four HDLC communication channels, each channel
fully independent and programmable by its own register set. The circuit performs the following
functions:Extraction (reception) and insertion (transmission) of the HDLC data packets in a time division
multiplex bit stream.Implementation of the basic HDLC functions of the layer-2 protocol, including address
recognition.Interfacing of the data packets to the microprocessor bus. For the temporary storage of data
packets internal FlFOs are used.Switching of data between serial interfaces.Implementation of different types of collision resolution.Test functions.
2.2Operating Modes
Each HDLC controller of the IDEC is assigned to one time channel determined either by time slot
assignment or by an external strobe signal.
Two basic configurations are distinguished (figure 4):In the quad connection configuration the four HDLC controllers (A - D) are connected to
individual time multiplexed communication lines;In the single connection configuration the four HDLC channels are all connected to one time
multiplexed communication line.
Figure 4
Functional Description
In the quad connection configuration two modes are distinguished as follows:Each connection is a time slotted highway, the lengths and positions of the time slots are
programmable (quad connection time slot mode);Each connection is a communication line, the time channels are marked by an external strobe
signal (quad connection common control mode).
Two modes are distinguished in turn for the single connection configuration as follows:The connection is a standard IOM interface with predefined channel positions (single
connection IOM mode);The connection is a time slotted highway (single connection time slot mode).
For simplicity, a time slotted highway will usually be referred to as a "PCM highway", or PCM for
short.
Table 1
Four Basic Operation Modes of the IDEC
To program the single connection IOM mode (CCR:MDS1, MDS0=10)
with the slave mode(MODE3-0:CMS1, CMS0=01) or
with the multi master mode(MODE3-0:CMS1, CMS0=10) or
with the uncond. trans. mode(MODE3-0:CMS1, CMS0=00)
this additional programming has to be made:
MODE0:CCS1, CCS0=00 bin
MODE1:CCS1, CCS0=00 bin
MODE2:CCS1, CCS0=00 bin
MODE3:CCS1, CCS0=00 bin
TSR0=0C hex
TSR1=1C hex
TSR2=2C hex
TSR3=3C hex
The four modes of operation are illustrated in figure 5. Via channel-by-channel programming, one
of a number of collision detection modes may be selected in each of the basic modes of operation.
For future reference, they are also depicted in figure 5.
Functional Description
Figure 5a, 5b
Operating Modes of the IDEC
Functional Description
Figure 5c, 5c
Operating Modes of the IDEC
Functional Description
Figure 5e, 5f
Operating Modes of the IDEC
Functional Description
2.3Interfaces
Microcontroller Interface
The IDEC is programmable over an 8-bit parallel microcontroller interface. Easy and fast
microprocessor access is provided by 8-bit address decoding on chip. The interface consists of 13
(19) lines and is directly compatible with processors of the multiplexed and demultiplexed address/
data bus types (Siemens/Intel or Motorola processor families). The microprocessor interface
signals are summarized in table 2.
Table 2
Microcontroller Interface Signals of the IDEC
Functional Description
Functional Description
2.4Individual Functions
2.4.1Channel Access
The four HDLC controllers of the IDEC are connected to the serial interfaces as shown in table 3.
The table indicates the selection of the data channel, the selectable time slot widths, the output
driver type, and the function of the active-low Tri-State Control (TSC) output in each of the operating
modes.
The data output is set in a high impedance state outside the time channel where data is transmitted.=Open-drain driver,=Push-pull driver.
The output driver type refers to the SD0X (or SD0X, SD1 X, SD2X and SD3X) outputs.
TSC is a push-pull signal.
Quad Connection Time-Slot Mode
Channel selection is performed via the Time-Slot Select Registers (TSR). For each HDLC channel,
the 8- bit TSR register gives the position of a time slot with a two-bit resolution. The length of the
time slot, either 1, 2, 7 or 8 bits, can be selected using the MODE register (CCS1, 0). These
parameters are common to the receive and the transmit channel.
In the case where the number of bits in a PCM frame is 256 or 512, the frame synchronization signal
FSC need not be provided at every PCM frame beginning, since bit counters are automatically reset
at frame end. When the PCM frame length is not equal to either 256 or 512 bits, the frame
synchronization signal has to be provided at the beginning of every PCM frame.
Functional Description
Table 3
HDLC Controller Channel Selection and Characteristics =Open-drain driver,=Push-pull driver.
The output driver type refers to the SD0X (or SD0X, SD1X, SD2X and SD3X) outputs.
TSC is a push-pull signal.
Functional Description
The tristate control output line TSC marks the time slot when data is transmitted/received by the
HDLC controller B.
The position of a time slot with respect to FSC, as a function of the TSR register contents, is shown
in figure 6.
Figure 6
Position of Time Slot for Different Channel Widths as a Function of TSR Register Contents
Functional Description
Quad Connection Common Control Mode
Channel selection is performed by an active high strobe signal provided through the FSC input. The
strobe signal is common to all four HDLC channels.
The TSC output is active when the FSC strobe is active.
Single ConnectionTS Mode
The time slots selected by the TSR registers all pertain to the same PCM highway. The
programming of a channel otherwise proceeds exactly as explained above.
The tristate control output line TSC marks the time slots when data is transmitted/received by any
of the four controllers.
Single Connection IOM - Mode
The IOM is an interface where a frame is composed of n IOM channels (nŠ1; n=8 in figure 7). Each
IOM channel has a unique structure. It consists of: two eight-bit bytes, corresponding to the ISDN
B channels, a MONITOR byte, and a control byte of which the first two bits are allocated to the ISDN
D channel.
In the single connection IOM mode the serial interface has an IOM frame structure and the four
HDLC channels are assigned to the D bits of four consecutive IOM channels. The choice whether
the four HDLC controllers are assigned to IOM channels 0 - 3 or 4 - 7 is governed by the
microcontroller bit VIS (Common Configuration Register). See figure 7.
Functional Description
Figure 7
Functional Description
2.4.2HDLC Communication Functions
Basic HDLC Functions
Each one of the four controller channels handles the following basic HDLC functions.
Receive directionFlag detection
A zero followed by six consecutive ones and another zero is recognized as a flag.Zero delete
A zero after five consecutive ones within an HDLC frame is deleted.Address recognition
A frame may be accepted or rejected on the basis of a comparison of the most significant
address byte (Service Access Point Identifier SAPI in Link Access Procedure for the D-
channel LAPD) with three fixed SAPI values.CRC checking
The CRC field of an HDLC frame is checked according to the generator polynomial16+x12+x5+1.Check for abort
Seven or more consecutive ones are interpreted as an abort sequence.Check for idle
Fifteen or more consecutive ones are interpreted as "idle", and reported to the processor via
a status bit.Minimum length checking
Reception of frames with less than three bytes between opening and closing flag is not
reported to the microcontroller.
Transmit directionFlag generation
A flag is generated at the beginning and at the end of every frame.Zero insert
A zero is inserted after five consecutive ones within an HDLC frame.CRC generation
The CRC field of the transmitted frame is generated according to the generator polynomial16+x12+x5+1.Abort sequence generation
An HDLC frame may be terminated with an abort sequence under software control or due to
a FIFO underrun condition.Inter-frame time fill
As inter-frame time fill either flags or idle (continuous ones) may be transmitted.
Functional Description
Reception and Transmission Functions
FIFO Structure
Each HDLC controller uses a 64-byte FIFO per direction for the intermediate storage of data
packets. All data bytes between the opening flag and the CRC field of an HDLC frame are passed
through the FIFO.
Figure 8
HDLC Frame Structure
The receive and transmit FlFOs are both divided, two blocks of 32 bytes each: One accessible to
the microcontroller and one inaccessible to the microcontroller. While the microcontroller is reading
(receive FIFO) or writing (transmit FIFO) data in one 32-byte block, the other block is filled (receive
FIFO) or emptied (transmit FIFO) by the IDEC. Thus the length of the received or transmitted frame
is not limited by the FIFO size.
Functional Description
Reception of Frames
Address Compare
Before a receive frame is stored, its address (the first byte following the opening flag) may optionally
be compared against three fixed values.
SAPG"Group SAPI"63D
SAPS"Signaling SAPI"0D
SAPP"Packet SAPI"16D
Each address compare may be individually enabled or disabled for each HDLC channel via bits
AC0, 1, 2 and 3 (ACR register).
The effect of a match is programmable as shown in table 4. In the table it is assumed that the
address compare enable bit (AC) is set for the channel in question. If AC = 0, all valid receive frames
in that channel are accepted.
Table 4
Address Compare Logic
Functional Description
Frame Storage
When a frame is accepted, it is stored in the receive FIFO.
In the case of a frame of length less than to 64 bytes, the whole frame may be stored in the receive
FIFO. After the first 32 bytes have been received, the device prompts the microcontroller to read
data from the FIFO (Receive Pool Full RPF interrupt status). Having done this, the microcontroller
releases the FIFO. This is done by the RMC (Receive Message Complete) software command,
after which the rest of the frame, when ready, is made available to the microcontroller (figure 9).
When a whole frame shorter than 32 bytes, or the final part of a frame longer than that becomes
available, the condition is indicated by an RME (Receive Message End) interrupt status, instead of
RPF.
Figure 9
Receive FIFO in the Case of a Frame No Longer than 64 Bytes.
In the case of frames at least 64 bytes long, the microcontroller will repeatedly be prompted by an
interrupt lo read out the FIFO in blocks of 32 bytes (except possibly the final block). Again, after
reading a block, the microcontroller acknowledges the data by a software command and thus
releases the FIFO. If this is not done before an additional 32-data bytes are received, the next data
byte will lead to a "data overflow" condition.
In the case of several shorter frames up to seventeen may be stored inside the HDLC controller.
After an interrupt (RME), one frame is available in the FIFO for the microcontroller to read. Up to
sixteen other frames may be stored in the meanwhile in the upper half of the FIFO (figure 10).
When the microcontroller releases the current data block from the FIFO by software command, the
next frame becomes available and the corresponding space is freed in the upper half for (a)
subsequent frame(s) (figure 10).
Functional Description
Figure 10
Receive FIFO in the Case of Short Frames
The interrupts accumulating in the process are incorporated into a queue and transferred one by
one to the microcontroller as well as additional information about the frame. In particular, the frame
length is stored in a register. Information such as "frame aborted yes/no" and "CRC error yes/no"
and "data overflow yes/no", is included in an extra byte stored in the FIFO after the last byte of the
corresponding frame.
Every interrupt has to be acknowledged by the microcontroller. A full FIFO at the beginning of a
frame will lead to a frame overflow condition.
If the microcontroller does not wish to preserve an incoming frame, the possibility exists to ignore
it. When the corresponding command (RMD) is issued, the part of the frame stored is deleted and
the rest of the entire frame will be ignored.
Functional Description
Transmission of Frames
2 x 32 bytes of intermediate storage are provided per HDLC controller in the transmit direction. After
up to 32 bytes have been written to the FIFO, transmission is started by a software command (XHF).
If the previous transmission is still underway when a new transmission command is issued,
microcontroller access to the FIFO will be blocked until the first transmission is completed
(figure11). This means that at most one complete frame may be written to the FIFO before a
transmission is initiated. If a transmission request does not include a "frame end" indicator (XME),
the HDLC controller will request the next data block via an interrupt if the FIFO contains no more
than 32 bytes. This procedure will be repeated until the microcontroller indicates that the frame is
to be closed.
In the case when this indication is not given and there is no more data ready for transmission, the
frame is terminated with an abort sequence and the microcontroller is notified via a transmit data
underrun (XDU) interrupt. The frame may also be aborted per software command. The completed
transmission of an HDLC frame is reported by an XPR (Transmit Pool Ready) interrupt status.
Figure 11
Transmit FIFO
Functional Description
2.4.3Collision Control and Switching Functions
The IDEC possesses flexible collision control capabilities which are totally transparent to the
microcontroller. The collision control modes enable use of the circuit in statistical multiplexing
applications or in centralized or de-centralized packet switches. Each of the four HDLC controllers
is individually programmed in one of four modes by its own register bits CMS1-0 (Collision Mode
Select).
Table 5 lists the four collision modes that can be selected, along with the auxiliary I/O lines used in
each case. The outputs SD1 X and SD2X can be selected to be of the open-drain or of the push-
pull type.
Table 5
Collision Modes of the IDEC
Functional Description
Unconditional Transmission Mode
The HDLC controller transmits frames without collision detection on the transmit line (time channel).
Slave Mode
The input CDR (Collision Data Receive) is used to control transmission of frames. This input is
common to all HDLC controllers which are programmed in the slave mode.
Transmission is inhibited by a "low" on the CDR input. If CDR becomes "low" during the
transmission of a frame, the frame is aborted by the HDLC controller, and the data output is set to
high impedance. Refer to figure 12.
Figure 12
Transmission Control in the Slave Mode (example)
Note:
The CDR is evaluatedat the falling edge of DCL, for a DCL rate equal to the data rate;at the falling edge of DCL immediately preceding the rising edge used for transmission, for a
DCL rate twice the data rate.
The state of CDR is evaluated by the HDLC controller only in the time channel used for transmission
by that controller. (Figure 12 is simplified in that the grouping of bits into time slots on
SD0X...SD3X and CDR is not depicted, i. e. bits outside the transmit time channel are not shown.)
When CDR is switched high, inter-frame time fill is marked in the transmit time channel if no
transmission request is pending, otherwise transmission starts at the first available instant.
Transmission of a previously aborted frame is automatically re-started by the HDLC controller if the
beginning of the frame is still available in the transmit FIFO. Otherwise an interrupt (XDU) to the
microcontroller indicates that the transmission has failed.
Functional Description
The slave mode is applicable in all of the basic operation modes, in both single connection and quad
connection applications. However, there is only one CDR line. This should especially be noted if:the IDEC is configured in the quad connection common control mode and more than one
HDLC controller is operated in the slave mode;when the same time slot is used by more than one HDLC controller in the slave mode.
In both cases more than one controller is evaluating the CDR line during the same time interval, and
when CDR goes "low" they all stop transmitting.
Multi-Master Mode
In the multi-master mode the controllers perform a bus access procedure and collision detection in
their assigned time channel(s). As a result, any number of IDECs can be assigned to one physical
channel, where they perform statistical multiplexing.
Collisions are detected by automatic comparison of each transmitted bit with the bit received via the
CDR input. For this purpose a logical "and" of the bits transmitted by parallel controllers is formed
and connected to the input CDR. This may be implemented most simply by defining the output line
driver to be of the open drain type (ODS = 1). Consequently the logical "and" of the outputs is
formed by simply tying them together ("wired or"). The result is returned to the CDR input of all
parallel circuits.
The multi-master mode is applicable in all operating modes, in both single connection and quad
connection applications. In the quad connection mode, those output lines (SD0X ... SD3X) for which
this collision mode is selected may be connected to CDR. The four HDLC controllers may either be
programmed to transmit in separate time channels or in the same time channel. A prerequisite for
the multi-master mode is that the inter-frame time fill used is "idle".
The multi-master operation is as follows (refer to figure 13).
When a mismatch between a transmitted bit and the bit on CDR is detected, the HDLC controller
stops sending further data and its output is set to high impedance.
As soon as it detects the transmit bus to be "idle" again, the controller automatically attempts to re-
transmit its frame. By definition, the bus is assumed idle when x consecutive ones are detected in
the transmit channel. Normally x is equal to 8.
Functional Description
Figure 13
Collision Detection in the Multi-Master Mode (example)
An automatic priority adjustment is implemented in the multimaster mode. Thus, when a complete
frame is successfully transmitted, x is increased to ten, and its value is restored to eight when a row
of ten1’s is detected on the bus (CDR). Furthermore, transmission of a new frame may be started
by the HDLC controller after the tenth 1.
This multi-master, deterministic priority management ensures an equal right of access of every
HDLC controller to the transmission medium, thereby avoiding blocking situations.
Master Mode
The master mode requires three auxiliary connections: data input CDR, data output SD1X and
collision data out SD2X.
This mode is applicable only in single connection operation.
In the master mode, the controller performs two functions:Switching of data packets between the main connection SD0X, SD0R and the auxiliary input
and output (CDR, SD1X)Resolution of collisions between data from the auxiliary connection CDR and HDLC frames
from the local microcontroller.
Refer to figure14.
Functional Description
Figure 14
I / O Connections in the Master Mode
Functional Description
In the TS mode the time slot programmed via the Time-Slot Select Register TSR applies
simultaneously to SD0X/SD0R and to the auxiliary lines CDR, SD1X and SD2X. In the IOM mode
the TSR register selects a time channel on the auxiliary connections CDR, SD1X and SD2X only
(however, the channel width selected should be two bits, as on the IOM interface, to ensure a
correct data throughput).
The switching of data from SD0R to SD1X is transparent. The switching of data from CDR to SD0X
depends on the state of the HDLC controller (transmit/no transmit) and on selected priorities, as
follows.
When no transmission command is issued to the HDLC controller, data is transparently switched
through from CDR to SD0X. When a transmit request is issued but the Force HDLC Frame (FHF)
bit is not set to 1, the data currently being received (if any) on CDR is given priority. The HDLC
controller starts transmitting its frame on SD0X only after CDR is detected to be idle, in other words,
when a row of eight ones is observed on CDR. Simultaneously, SD2X is set "low" to indicate that
no data will be accepted on CDR input data line.
Figure 15a shows the time relation between CDR (data in) and SD2X (collision out) as well as the
logical relation between SD2X and SD0X (data out). The figures are simplified in that the grouping
of bits into time slots on SD0X, and on SD2X/CDR is not depicted.
When a transmit command is issued and the Force HDLC Frame (FHF) bit is set to 1, the frame
currently being received on CDR is aborted. Seven ones are appended to the last bit of the aborted
frame on SD0X, after which the HDLC controller starts transmitting its frame (figure 15b).
In both cases, SD2X is set "high" again after a delay of eight bit-times following the last "0" of the
closing flag, to indicate that data is accepted on the CDR input data line. However, if a new transmit
command is issued before that time, SD2X remains "low" and transmission of the new frame starts
immediately after the eighth 1.
Functional Description
Collision Resolution in the Master Mode with Programmable Priority (FHF)
Functional Description
Note on Data Delay in Master Mode
The data bits are switched from SD0R to SD1X and from CDR to SD0X with a minimum delay as
shown in figure 16.
Two different cases are distinguished:TS mode.
In this case the time slots on SD0R/SD0X and on CDR/SD1X are identical. The data delay
from CDR to SD0X is one bit, whereas the delay from SD0R to SD1 X is two bit times.
IOM mode with identical channel (time slot) on SD0R/SD0X and CDR/SD1X. This case is
identical to the previous one.lOM mode with a time slot on CDR/SD1X which does not coincide with the lOM channel bits
on SD0R/SD0X. In this case, the data bits undergo (in addition to the inherent delay due to
the different bit positions) a delay of one bit time from CDR to SD0X, whereas no additional
bit delay is introduced when going from SDOR to SD1X.
Functional Description
Bit delay for coinciding channel/time slot position on SD0R/SD0X and on CDR/SD1X.
Figure 16a
Bit Delay from SD0R/CDR to SD1X/SD0X
Bit delay for non-identical channel/time slot position on SD0R/SD0X and on CDR/SD1X (possible
only when SD0R/SD0X is an IOM interface).
Figure 16b
Transmit Delay from SD0R/CDR to SD1X/SD0X
