PEB20560 ,ICs for Communicationscharacteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
PEB20560V2.1 ,ICs for CommunicationsBlock Diagram and System Integration . . . . . . . . . . . . . . . 1-251.6 Example for System Integ ..
PEB20570FV3.1 ,DELIC-LC (DSP Embedded Line and Port ...Data Sheet, DS 1, March 2001DELIC-LCDELIC-PBDSP Embedded Line andPort Interface ControllerPEB 20570 ..
PEB20571FV3.1 ,DELIC-PB (DSP Embedded Line and Port ...Data Sheet, DS 1, March 2001DELIC-LCDELIC-PBDSP Embedded Line andPort Interface ControllerPEB 20570 ..
PEB20590HV2.1 ,VIP (Versatile ISDN Port)Data Sheet, DS4, March 2001VIP, VIP-8Versatile ISDN PortPEB 20590 Version 2.1PEB 20591 Version 2.1W ..
PEB20591HV2.1 ,VIP-8 (Versatile ISDN Port)Data Sheet, DS4, March 2001VIP, VIP-8Versatile ISDN PortPEB 20590 Version 2.1PEB 20591 Version 2.1W ..
PIC16F874A , 28/40/44-Pin Enhanced Flash Microcontrollers
PIC16F874A , 28/40/44-Pin Enhanced Flash Microcontrollers
PIC16F883 , 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology
PIC17C42A , High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
PIC18F2525-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PIC18F2620-I/SO , 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
PEB20560-PEB20560V2.1
ICs for Communications
ICs for Communications
DSP Oriented PBX Controller
DOC
PEB 20560 Version 2.1
Preliminary Data Sheet2003-08
Note:OCEM® and OakDSPCore® (OAK®) are registered trademarks of ParthusCeva,
Inc..
Edition 2003-08
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München© Siemens AG 1997.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact
your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will
take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in-
curred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
Table of ContentsPage
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-1
1.1DOC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5
1.2Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-7
1.3Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-8
1.4Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-9
1.5Functional Block Diagram and System Integration . . . . . . . . . . . . . . .1-25
1.6Example for System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-26
Functional Block Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1ELIC0 and ELIC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.1General Functions and Device Architecture . . . . . . . . . . . . . . . . . . . .2-1
2.1.2Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.2.1Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
2.1.2.2Reset Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-2
2.1.2.3EPIC®-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.2.3.1PCM-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.2.3.2Configurable Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.2.3.3Memory Structure and Switching . . . . . . . . . . . . . . . . . . . . . . . . . .2-3
2.1.2.3.4Pre-processed Channels, Layer-1 Support . . . . . . . . . . . . . . . . . .2-4
2.1.2.3.5Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5
2.1.2.4SACCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.2.4.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.2.4.2Parallel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-6
2.1.2.4.3FIFO-Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-10
2.1.2.4.4Protocol Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12
2.1.2.4.5Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-27
2.1.2.4.6Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-28
2.1.2.4.7Serial Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-30
2.1.2.4.8Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32
2.1.2.5D-Channel Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-32
2.1.2.5.1Upstream Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-33
2.1.2.5.2Downstream Direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-38
2.1.2.5.3Control Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-39
2.1.2.5.4D-Channel Arbiter Co-operating with QUAT-S Circuits . . . . . . . .2-40
2.2SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-41
2.3Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-42
2.3.1IOM®- and PCM-Ports Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . .2-45
2.3.1.1IOM® Multiplexer for IOM®-2 Ports (CFI Interfaces of EPIC) . . . . .2-45
2.3.1.2PCM-Ports Multiplexer for PCM Highways . . . . . . . . . . . . . . . . . . .2-46
2.3.2Multiplexers for Signaling Controllers . . . . . . . . . . . . . . . . . . . . . . . .2-47
2.3.2.1SACCO-A0 and SACCO-A1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-47
Table of ContentsPage2.3.2.3SACCO-B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-49
2.3.2.4SIDEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-50
2.3.3ELIC1-Ports Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-51
2.3.4IOM®-Multiplexer for DSP Connection to EPICs . . . . . . . . . . . . . . . .2-52
2.3.5PCM/IOM MUX Registers Description . . . . . . . . . . . . . . . . . . . . . . .2-53
2.3.5.1PCM/IOM MUX Mode Register (MMODE) . . . . . . . . . . . . . . . . . . .2-53
2.3.5.2CFI Channel Select 0 Register (MCCHSEL0) . . . . . . . . . . . . . . . .2-54
2.3.5.3CFI Channel Select 1 Register (MCCHSEL1) . . . . . . . . . . . . . . . .2-55
2.3.5.4CFI Channel Select 2 Register (MCCHSEL2) . . . . . . . . . . . . . . . .2-56
2.3.5.5PCM Channel Select 0 Register (MPCHSEL0) . . . . . . . . . . . . . . .2-57
2.4Channel Indication Logic (CHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-58
2.4.1CHI Configuration Register (VMODR) . . . . . . . . . . . . . . . . . . . . . . .2-58
2.4.2CHI Control Registers (VDATR0:VDATR3) . . . . . . . . . . . . . . . . . . .2-59
2.5FSC with Delay (FSCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-60
2.6Digital Signal Processor (DSP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61
2.6.1DSP Kernel Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61
2.6.2DSP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-61
2.7DSP Control Unit (DCU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62
2.7.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62
2.7.2DSP Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-62
2.7.3Control of External Memories / Registers . . . . . . . . . . . . . . . . . . . . .2-63
2.7.3.1Memory Configuration Register (MEMCONFR) . . . . . . . . . . . . . . .2-68
2.7.3.2Test Configuration Register (TESTCONFR) . . . . . . . . . . . . . . . . . .2-69
2.7.4Emulation Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-70
2.7.5Interrupt Handling and Test Support . . . . . . . . . . . . . . . . . . . . . . . . .2-70
2.7.6Run Time Statistics Counter and Register (STATC and STATR) . . .2-71
2.7.7Program Write Protection Register (PASSR) . . . . . . . . . . . . . . . . . .2-73
2.7.8Serial (via JTAG) Emulation Configuration Register (JCONF) . . . . .2-73
2.7.9Boot Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-74
2.7.9.1Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-74
2.7.9.2Emulation Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-75
2.7.9.3Boot Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-75
2.7.9.4Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-75
2.7.9.5µP Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-76
2.7.9.6Mail Box Instructions Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-77
2.7.9.7Write Program Memory Command . . . . . . . . . . . . . . . . . . . . . . . . .2-77
2.7.9.8OAK Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-78
2.7.9.9Boot Configuration Register (BOOTCONF) . . . . . . . . . . . . . . . . . .2-79
2.7.9.10The Bootroutine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-79
2.7.10Sine Table ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-87
2.8PCM-DSP Interface Unit (PEDIU) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-88
2.8.1General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-88
Table of ContentsPage2.8.2PEDIU Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-93
2.8.2.1PEDIU Control Register (UCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-93
2.8.2.2PEDIU Status Register (USR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-97
2.8.2.3PEDIU Input Stream Bypass Enable Register (UISBPER) . . . . . .2-101
2.8.2.4PEDIU Output Stream Bypass Enable Register (UOSBPER) . . .2-103
2.8.2.5PEDIU Tri-State Register (UTSR) . . . . . . . . . . . . . . . . . . . . . . . .2-104
2.8.2.6PEDIU ROM Test Address Register (UPRTAR) and
PEDIU ROM Test Data Register (UPRTDR) . . . . . . . . . . . . . . . .2-106
2.8.3PEDIU Synchronization and Clock Rates . . . . . . . . . . . . . . . . . . . .2-107
2.8.3.1PEDIU Synchronization by FSC and DCL . . . . . . . . . . . . . . . . . .2-107
2.8.3.2Restrictions on PEDIU Clock Rates . . . . . . . . . . . . . . . . . . . . . . .2-108
2.8.4PEDIU Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-108
2.8.5PEDIU Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-109
2.8.5.1PEDIU Serial Data Processing . . . . . . . . . . . . . . . . . . . . . . . . . . .2-109
2.8.5.2PEDIU Parallel Data Processing . . . . . . . . . . . . . . . . . . . . . . . . .2-109
2.8.5.3The Circular Buffer Address Method . . . . . . . . . . . . . . . . . . . . . .2-111
2.8.6a-/µ-law Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-114
2.9On-chip Emulation (OCEM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-115
2.10Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-115
2.10.1µP Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-115
2.10.2OAK Mailbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-116
2.11µP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118
2.11.1Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118
2.11.2Memory and I/O Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-118
2.12Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-119
2.12.1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-119
2.12.2Types of Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-120
2.12.2.1Input/Output Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-120
2.12.2.2Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-120
2.12.3Clocks Generator Registers Description . . . . . . . . . . . . . . . . . . . . .2-125
2.12.3.1Clocks Select 0 Register (CCSEL0) . . . . . . . . . . . . . . . . . . . . . . .2-125
2.12.3.2Clocks Select 1 Register (CCSEL1) . . . . . . . . . . . . . . . . . . . . . . .2-126
2.12.3.3Clocks Select 2 Register (CCSEL2) . . . . . . . . . . . . . . . . . . . . . . .2-128
2.13Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-129
2.13.1MASK (IMASK0, IMASK1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-129
2.13.2Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-130
2.13.3Interrupt Priority (IPAR0, IPAR1, IPAR2) . . . . . . . . . . . . . . . . . . . .2-130
2.13.4Interrupt Cascading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-132
2.13.4.1Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-133
2.13.4.2Daisy Chaining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-134
2.13.5Global Interrupt Status Registers (IGIS0 and IGIS1) . . . . . . . . . . .2-135
2.14Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . .2-136
