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PEB20534H-10V2.0-PEB20534H-52V2.0
DSCC4 (DMA Supported Serial Communica...
ICs for Communications
DMA Supported Serial Communication Controller with 4 Channels
DSCC4
PEB 20534 Version 2.0
Data Sheet09.98
DS 2
Edition 09.98
Published by Siemens AG,
HL SC,
Balanstraße 73,
81541 München© Siemens AG 1998.
All Rights Reserved.
Attention please!As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for
applications, processes and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
PackingPlease use the recycling operators known to you. We can also help you – get in touch with your nearest sales
office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.
For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice
you for any costs incurred.
Components used in life-support devices or systems must be expressly authorized for such purpose!Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or
systems2 with the express written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be
expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that
device or system.
PEB 20534
PrefaceThe DMA Supported Serial Communication Controller with 4 Channels (DSCC4) is a
Multi Protocol Controller for a wide range of data communication and telecommunication
applications. This document provides complete reference information on hardware and
software related issues as well as on general operation.
Organization of this DocumentThis Data Sheet is divided into 16 chapters. It is organized as follows: Chapter 1, Overview
Gives a general description of the product, lists the key features, and presents some
typical applications.Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.Chapters 3,4,5,6,7 Functional Description
These chapters provide detailed descriptions of all DSCC4 internal function blocks.Chapter 8, Detailed Protocol Descriptions
Gives a detailed description of all protocols supported by the serial communication
controllers SCCs.Chapter 9, Reset and Initialization Procedure
Gives examples for DSCC4 initialization procedure and operation.Chapter 10, Detailed Register Description
Gives a detailed description of all DSCC4 on chip registers.Chapter 11, Host Memory Organization
Provides an overview of all DSCC4 data structures located in the shared memoryChapter 12, JTAG Boundary Scan
Gives a detailed description of the boundary scan unit.Chapter 13 Application Examples
These chapters will provide additional information on special applications and bus
utilization analysis.Chapter 14, Electrical Characteristics
PEB 20534timing diagrams and values for all interfaces.Chapter 15, Package Outline
PEB 20534
Table of ContentsPageOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
1.2Differences Between the DSCC4 and the ESCC Family . . . . . . . . . . . . . . .22
1.2.1Enhancements to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . . .22
1.2.2Simplifications to the ESCC Serial Core . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1.4Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4.1Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4.1.1HSSI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1.4.1.2HSSI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.4.1.3General Data Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.1Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
2.2Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48Microprocessor Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.1PCI Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.1.1Supported PCI Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
4.1.2PCI Configuration Space Register Overview . . . . . . . . . . . . . . . . . . . . . .52
4.2De-multiplexed Bus Interface Extension . . . . . . . . . . . . . . . . . . . . . . . . . . .53
DMA Controller and Central FIFOs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
5.1DMAC Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.1.1DMAC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
5.1.2DMAC Control and Data Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
5.1.2.1DMAC Transmit Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
5.1.2.2DMAC Receive Descriptor Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
5.1.2.3DMAC Operation Using Hold-Bit Control Mechanism . . . . . . . . . . . . .76
5.1.2.4DMAC Operation Using Last Descriptor Address Control Mode . . . . .78
5.1.3DMAC Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.2Central FIFOs Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.2.1Central FIFO Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.2.2Central Transmit FIFO (TFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
5.2.3Central Receive FIFO (RFIFO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
5.2.4DMAC Internal Arbitration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
5.2.5DMAC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
5.2.6Little / Big Endian Byte Swap Convention . . . . . . . . . . . . . . . . . . . . . . . .95
Multi Function Port (MFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
