PEB2047-16N ,MTSL (Memory Time Switch Large)ICs for CommunicationsMemory Time Switch LargeMTSLPEB 2047PEB 2047-16Version 2.1Data Sheet 03.95Edi ..
PEB2047-16N ,MTSL (Memory Time Switch Large)characteristics.Terms of delivery and rights to change design reserved.For questions on technology, ..
PEB2047-16-N ,MTSL (Memory Time Switch Large)applications, pro-cesses and circuits implemented within com-ponents or assemblies.The information ..
PEB2047NV2.1 ,MTSL (Memory Time Switch Large)characteristics are ensured over the operating range of the integrated circuit.Typical
PEB2047N-V2.1 ,MTSL (Memory Time Switch Large)characteristics specify mean values expected over the production spread. If nototherwise specified, ..
PEB2052NV1.5 ,PIC (PCM Interface Controller)applications.• SLD-bus to peripheral circuits, e.g. codec filter devices or ISDN componentsThe PIC ..
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PEB2047-16N-PEB2047-16-N-PEB2047NV2.1-PEB2047N-V2.1
MTSL (Memory Time Switch Large)
ICs for Communications
Memory Time Switch Large
MTSL
PEB 2047
PEB 2047-16
Version 2.1
Edition 03.95This edition was realized using the software
system FrameMaker‚.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München Siemens AG 1995.
All Rights Reserved.
Attention please!As far as patents or other rights of third par-
ties are concerned, liability is only assumed
for components, not for applications, pro-
cesses and circuits implemented within com-
ponents or assemblies.
The information describes the type of compo-
nent and shall not be considered as assured
characteristics.
Terms of delivery and rights to change design
reserved.
For questions on technology, delivery and
prices please contact the Semiconductor
Group Offices in Germany or the Siemens
Companies and Representatives worldwide
(see address list).
Due to technical requirements components
may contain dangerous substances. For in-
formation on the types in question please
contact your nearest Siemens Office, Semi-
conductor Group.
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turer.
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Components used in life-support devices
or systems must be expressly authorized
for such purpose!Critical components1 of the Semiconductor
Group of Siemens AG, may only be used in
life-support devices or systems2 with the ex-
press written approval of the Semiconductor
Group of Siemens AG.A critical component is a component used
in a life-support device or system whose
failure can reasonably be expected to
cause the failure of that life-support device
or system, or to affect its safety or effec-
tiveness of that device or system.Life support devices or systems are in-
tended (a) to be implanted in the human
body, or (b) to support and/or maintain
and sustain human life. If they fail, it is rea-
sonable to assume that the health of the
user may be endangered.
Data Classification
Maximum RatingsMaximum ratings are absolute ratings; exceeding only one of these values may cause
irreversible damage to the integrated circuit.
CharacteristicsThe listed characteristics are ensured over the operating range of the integrated circuit.
Typical characteristics specify mean values expected over the production spread. If not
otherwise specified, typical characteristics apply at TA = 25°C and the given supply
voltage.
Operating RangeIn the operating range the functions given in the circuit description are fulfilled.
For detailed technical information about "Processing Guidelines" and
"Quality Assurance" for ICs, see our "Product Overview".
PEB 2047
PEB 2047-16
Table of ContentsPageFeatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.1Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.2Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.3General Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
1.4System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122.1MTSL Internal Timing and Channel Delay . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Operational Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183.1Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.3Indirect Access Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.4Frame Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Detailed Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1Mode Register (MOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2Command Register (CMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3Status Register (STAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4Interrupt Status Register (ISTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5Mask Register (MASK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.6Indirect Access Register (IAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.7Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.1Determination of MTSL Frame Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
6.2Example for a MTSL Design guaranteeing
Constant Frame Delay for all Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . .48
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Memory Time Switch Large
(MTSL)
PEB 2047
PEB 2047-16
1FeaturesNon-blocking time/space switch for 2048-, 4096-, 8192- or 384-kbit/s PCM systemsDifferent modes programmable for input and output
separatelyConfigurable for a 4096-kHz, 8192-kHz or 16384-kHz
device clockSwitching of up to 1024 incoming PCM channels to up to
1024 outgoing PCM channels16 input and 8 output PCM linesTristate function for further expansion and tandem
operationμP read-access to PCM dataProgrammable clock shift with half clock step resolution for
input and outputIndividual line delay measurement and clock shift
mechanism for 8 PCM inputsBuilt-in selftest8-bit Motorola or Intel type μP interfaceConstant or minimal channel-delay programmable on a per
time-slot basisIn-operation adjustment of bit-sampling without bit errorsLow power consumptionSingle 5 V power supply
Important Note: All 16384-MHz features described in this
data sheet are only available with the PEB 2047-16!
PEB 2047
PEB 2047-16
1.1Pin Definitions and Functions
PEB 2047
PEB 2047-16
Pin Definitions and Functions (cont’d)
PEB 2047
PEB 2047-16
1.2Logic Symbol
Figure 1
Functional Symbol
1.3General Device Overview
The Siemens Memory Time Switch Large MTSL (PEB 2047) is an expansion of the MTSC
(PEB2045) regarding capacity and/or functionality. It is a monolithic CMOS switching device
capable of connecting maximally 1024 PCM-input time-slots to 1024 output time-slots. A constant
frame delay of one frame can be selected for wideband applications (e.g. ISDN H-Channels),
whereas for example for voice channels a minimal frame delay is programmable. In order to
manage the problem of different line delays, eight of the PCM inputs can be used as frame
measurement inputs and eight different input offsets are allowed. Thus a frame wander can be
compensated by adjusting the input offset during operation. A special circuitry guarantees that no
bit error will occur, when reprogramming the input offsets.
The MTSL on-chip connection memory and data-memory are accessed via the 8-bit standard μP-
interface (Motorola or Intel type).
A built-in selftest mechanism – also activated by the μP – ensures proper device operation in the
system.
The PEB 2047 is fabricated using the advanced CMOS technology from Siemens and is mounted
in a P-LCC-44 package. Inputs and outputs are TTL-compatible.
PEB 2047
PEB 2047-16
1.4System Integration
The main application field for the MTSL (PEB 2047) are central switches with high switching
capacity. Two possibilities exist to implement a non-blocking switch for 1024 input and 1024 output
channels.
With a 16384-kHz device clock only one MTSL is needed (figure 2), with a 8192-kHz device clock
two chips in parallel realize the same functionality (figure 3).
Figure 2
Memory Time Switch for a Non-Blocking 1024-Channel Switch (16 MHz)
Figure 3
PEB 2047
PEB 2047-16
Due to the tristate capability of the MTSL larger switches can be easily formed.
Figure 4 and 5 show how 4 devices operating with a 16384-kHz clock or 8 devices operating with
a 8192-kHz clock can be arranged to form non-blocking 2048-channel switches.
Figure 4
Memory Time Switch for a Non-Blocking 2048-Channel Switch with Four Devices (16-MHz
device clock)
Figure 5
Memory Time Switch for a Non-Blocking 2048-Channel Switch with Eight Devices (8-MHz
PEB 2047
PEB 2047-16Functional Description
The MTSL is a memory time switch device. Operating with a device clock of 8192 kHz it can connect
any of 1024 PCM-input channels to any of 512 output channels. With a device clock of 16384 kHz
all 1024 PCM channels can be switched to the output. Additionally a 2048-kbit/s mode with a
capacity of 512 × 256 time-slots and a clock frequency of 4096 kHz is possible for systems, which
need the frame integrity feature.
A general block-diagram of the MTSL is shown in figure 7.
The input information of a complete frame is stored in one of the two on-chip 8-Kbit data memories
DM0 and DM1. The incoming 1024 channels of 8 bits each are written in sequence into fixed
positions of DM0 or DM1. This is controlled by the input counter in the timing control block with a
8-kHz repetition rate. If MTSL-A1 compatible operation (i.e. no frame integrity guaranteed) is
wished, only one of the two data memories is used. Otherwise DM0 and DM1 are filled alternating
with input frames.
For outputting, the connection memory (CM) is read in sequence. Each location in the CM points to
a location in the data memory. The byte in this data memory location is transferred into the current
output time-slot. The read access to the CM is controlled by an output counter. An additional bit
(D12) in each location of the CM controls the access to the data memories DM0 and DM1. Three
address pointers – two switching aligned to the input frame (DMI, IADP), one switching aligned to
the output frame (DMO) – are working in conjunction with D12 implementing the constant/minimal
delay function (see figure 6).
PEB 2047
PEB 2047-16
Constant delay (D12 = 0):read output time-slot from data memory (not DMO)
Minimal delay (D12 = 1):if number of input time-slot to be switched to current output ≤ IADP
then
read output time-slot from data memory DMI
else
read output time-slot from data memory (not DMI)
The synchronization of this procedure will be achieved by a rising edge of the synchron pulse SP,
which is always sampled with the falling edge of the device clock.
Different modes of operation are configurable at the PCM-input interface (see table 3).
Furthermore, 8 PCM-input lines can be aligned with individual clock shift values to compensate
different line delays. If more than 8 inputs are used one clock shift value controls up to two ports at
the same time.
The input lines IN8 to IN15 can be used as additional frame-measurement inputs (FS(0:7)). After
synchronizing the device by the SP pulse the FS inputs can be evaluated on a per port basis. This
evaluation procedure is started by a microprocessor command. As a result the input counter value
on the rising edge of the FS signal can be read from an internal register. Thus delay compensation
is easily managed by programming appropriate clock shift values and/or a possible software offset.
During operation of the chip a frame length check is also supplied, which controls correct
synchronization by the SP pulse and generates an interrupt in case of lost or achieved
synchronization.
The output buffer operation is controlled by mode selection and the chosen clock-rate (4096 kHz,
8192 kHz or 16384 kHz) (see table 2). Shifting of the output frame is also possible, but all output-
lines are affected the same way.
The unused output ports are tristated by mode selection, whereas unused time-slots are tristated by
an additional bit in the control memory. By using this tristate capability the MTSL can be easily
expanded to a time switch of any size (see figure 2 to 5).
PEB 2047
PEB 2047-16
Figure 7
Block Diagram MTSL
The standard 8-bit μP interface can communicate with Intel multiplexed/demultiplexed
microprocessors as well as with Motorola demultiplexed processors. It gives access to the internal
registers and to the control- and data memory. Five directly addressable registers are provided. All
other registers and the memories are accessed by a simple three byte indirect access method
PEB 2047
PEB 2047-16
2.1MTSL Internal Timing and Channel Delay
Figure 7 shows the chip internal timing of writing and reading the data memory for all possible
operation modes.
Control Memory Reset
Initialization of the device after a hardware reset (RES) is easily done with a μP-command “control
memory reset”. After finishing this procedure all control memory channels contain the information
“tristated”.
Evaluate Frame Measurement Signal
A command and an address (0 … 7) will be given by the μP. The rising edge of the corresponding
frame measurement signal (FS0 … FS7) will be evaluated. The exact timing of the FS edge can
then be read from an internal 12-bit register (resolution of a complete 8-kHz frame in half 16-MHz
clock periods).
MTSL-Selftest
The switching path of the MTSL including input buffer, data memory, control memory, output buffer
and timing control can be tested in the system by a built-in selftest. The two data memories DM0
and DM1 require two test procedures. Activating this mechanism takes (2×2.5)ms (4096kHz),×1.25) ms (8192 kHz) or (2 × 0.625)ms (16384 kHz). Finally the result “selftest ok/selftest not
ok” can be read from the internal status register.
After test completion the control-memory is also reset.
2.2Special Functions
The activity of all special functions can be read in the status register. Completion of these functions
is indicated by interrupts.
PEB 2047
PEB 2047-16
Figure 8
PEB 2047
PEB 2047-16
For a system operating with 8192-kHz device clock and 8192-Mbit/s/8192 Mbit/s input/output data
rate the following frame delay table can be deduced from the timing diagram:
Table 1
From this table it can be seen, that it is not possible to achieve the constant delay of one frame for
all switching paths. Those input time-slots, which are written to the data memory later than they
should have been read (for example in the above configuration TS124 – TS127 switched to TS0 or
TS1, OUT1, 2, 3), will be delayed by three frames!
PEB 2047
PEB 2047-16Operational Description
3.1Initialization Procedure
For a proper initialization of the MTSL the following procedure is recommended:
First a reset pulse (RES) of at least two CLK clock-periods has to be applied. All registers contain
now their reset values. In the next step the connection-memory CM is initialized by the commands
CMDR:STP (1:0) = 01 (CM reset) or CMDR:STP (1:0) = 11 (MTSL selftest).
After having programmed a CM-reset command, it takes 4096-clock periods until all tristate-control
entries in the CM contain the value “1” (tristated).
If a selftest-command was given, it takes 10240-clock periods to achieve the same effect.
Furthermore the register bit STAR:STOK (selftest o.k.) should still be set to “1” in this case, in order
to prove that there is no fault on the chip. From version V2.1 up, the selftest command must be given
for each data memory (DM0, DM1) separately. DM1 is tested, when register OPCR contains the
reset value FFH, DM0 is tested by programming OPCR to FBH.
The activity of the procedures can be monitored in STAR:PACT and an interrupt will indicate their
completion.
In all cases it is important, that the outputs are tristated by MOD:PSB = 0.
3.2Operation Mode
The operation mode of the device is fixed by programming MOD:OMD (1:0) and MOD:IMD (2:0)
and by the device clock used at pin CLK (see table 2 and 3).
3.3Indirect Access Register
The connection-memory, data-memory and indirect registers are accessible through the indirect
access register (IAR). An indirect access is performed by reading and/or writing three consecutive
bytes to/from IAR. An incomplete three-byte access is indicated by STAR:Z = 1. After having read
and/or written the third byte the operation selected by IAR:C (1:0), WR/RDQ is started and the bit
STAR:B is set to 1. It takes at most 4.5 clock periods (8.5 clock periods for a “read data memory”)
until the operation is performed and STAR:B is reset.
PEB 2047
PEB 2047-16
3.4Frame Evaluation
Suppose the following timing at PCM input IN5 (mode 2):
Figure 9
If the device is in synchronized state (STAR:PSS = 1) and the command “frame evaluation at FS5”
(CMDR = 58H) is programmed, the second following rising edge of FS5 is evaluated and creates the
following result in register FER:
D (11)=0
D (10:1)=3E7H
D (0)=0
D0 is fixed to 0 and doesn’t have a meaning in 8-MHz clock operation modes.
The actual offset of the incoming frame can now be calculated according to the formulas given in
table 9.
PEB 2047
PEB 2047-16
3.5Input Offset and Output Offset
Based on the results of the frame evaluation procedures the input offsets can be adjusted by
programming ICSR (7:0) corresponding to inputs IN (7:0). If data oversampling is used, the values
of ICSR (7:0) can be adjusted within some limits during operation without producing bit errors:clockrate = 2×datarate
possible adjustment is one half clockperiod forward or backward.
Figure 10clockrate = 4 × datarate
possible adjustment is one clockperiod backward or two clockperiods forward.
Figure 11
The output offset is the same for all output lines and is fixed in register OCSR.
PEB 2047
PEB 2047-16Detailed Register Description
4.1Mode Register (MOD)
Access in the multiplexed μP-interface mode:Read/write, address: 0H
Access in a demultiplexed μP-interface mode:Read/write, address: 0H
Reset value:00H
PSBPCM Stand By; a logical 0 switches the PCM-interface outputs to high
impedance.
MD2If set to “1”, the PEB 2047 is able to switch channels with 2048-kHz data rate,
when operating with 8.192 MHz (switching capacity 512 × 512 time-slots) or
4.096 MHz (switching capacity 512×256 time-slots).
OMD1 … OMD0Output Mode 1 and 0; these bits define the PCM-output mode according to
the following table.
Input and output mode combinations which use the same device clock frequency have to be selected.
Bit7Bit0
Table 2
Output Modes
PEB 2047
PEB 2047-16
IMD2 … IMD0:Input Mode 2, 1 and 0; these bits define the PCM-input mode according to
the following table.Input and output mode cominations which use the same device clock frequency have to be selected.
Table 3
Input Modes
PEB 2047
PEB 2047-16
4.2Command Register (CMDR)
Access in the multiplexed μP-interface mode:Write, address 2H
Access in a demultiplexed μP-interface mode:Write, address 1H
Address:01H
FSAD (2:0)Frame Synchronization signal Address 2 to 0; Address of the chosen FS
signal 0 to 7 to be evaluated by the procedure started by SFE.
SFEStart Frame Evaluation; a one in this bit position starts the frame evaluation
procedure. A read operation on register FER will stop an unfinished frame
evaluation procedure.Reset Incomplete instruction; if a three byte indirect register access is not
completed the internal logic must be initialized again before a new three byte
access is possible.
STP0 … STP1Start Procedure 1 and 0.
The following procedures can be activated by these bits:
Note:Before activating one of these procedures MOD:PSB has to be set to 0. During selftest or CM
reset the device will ignore the external synchronization pulse and the user has no access to
the internal data memory.
Bit7Bit0
Table 4
STP Commands
PEB 2047
PEB 2047-16
4.3Status Register (STAR)
Access in the multiplexed μP-interface mode:Read, address: 2H
Access in a demultiplexed μP-interface mode:Read, address: 1H
Reset value:01H
Incomplete instruction; a three byte indirect instruction is not completed (Z = 1).
FSAD (2:0)Frame Synchronization signal Address 2 to 0: see CMDR.
BBusy; an indirect access is active (memories or indirect registers); the three byte
indirect access register is not accessible.
PACTProcedure Active; one of the procedures started by the μP (selftest, CM reset or
frame evaluation) is active.
PSSPCM Synchronization Status; the PCM interface is synchronized (logical 1) or
not synchronized (logical 0).
STOKSelftest O.K.; after a selftest procedure this bit is set to 1, if no faults are detected.
Note:This bit is only valid, if no power failure or inappropriate clocking occurred during
the test (see ISTA:IR); this bit is set to 1 by a start selftest command or by
hardware reset.
Bit7Bit0
PEB 2047
PEB 2047-16
4.4Interrupt Status Register (ISTA)
Access in the multiplexed μP-interface mode:Read, address: 4H
Access in a demultiplexed μP-interface mode:Read, address: 2H
Reset value:00H
FECFrame Evaluation Completed; the indirect register FER contains a valid offset and can be
read; this bit is reset by reading ISTA.Procedure Completed; the procedure started from the command register (CM reset or
MTSL selftest) is finished; this bit is reset by reading ISTA.Initialization Request. The connection memory has to be programmed due to a loss of data
(IR = 1). The IR bit is set after power failure or inappropriate clocking. This bit is reset by
reading ISTA. It can only be retriggered again after a selftest or CM-reset procedure.
PFIPCM-Framing Interrupt; this bit being logical 1 indicates the loss or gain of synchronization.
Synchronization is considered lost by the MTSL if the SP signal is not repeated within the
correct period. Synchronization is considered achieved, if two consecutive SP pulses with
the correct period have been received. PFI is reset by reading ISTA.
4.5Mask Register (MASK)
Access in the multiplexed μP-interface mode:Write, address: 4H
Access in a demultiplexed μP-interface mode:Write, address: 2H
Reset value:00H
A logical 1 disables the corresponding interrupt as described in ISTA. A masked interrupt is stored
internally and reported in ISTA immediately, if the mask is released.
Bit7Bit0
Bit7Bit0
