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PEB2045NVA3SIEN/a35avaiMTSC (Memory Time Switch CMOS)
PEB2045NVA3INFINEONN/a5200avaiMTSC (Memory Time Switch CMOS)
PEB2045N-VA3 |PEB2045NVA3SIEN/a670avaiMTSC (Memory Time Switch CMOS)
PEB2045N-VA3 |PEB2045NVA3SIEMENSN/a6avaiMTSC (Memory Time Switch CMOS)
PEB2045N-VA3 |PEB2045NVA3infineonN/a14avaiMTSC (Memory Time Switch CMOS)
PEB2045NVA-3 |PEB2045NVA3SIEMENSN/a100avaiMTSC (Memory Time Switch CMOS)
PEB2045PVA3infineonN/a153avaiMTSC (Memory Time Switch CMOS)


PEB2045NVA3 ,MTSC (Memory Time Switch CMOS)Block Diagram SP CLK OUT 0 OUT 7ITB00554Line

PEB2045NVA3-PEB2045N-VA3-PEB2045NVA-3-PEB2045PVA3
MTSC (Memory Time Switch CMOS)
Memory Time Switch CMOS (MTSC)
General Description
The MTSC PEB 2045 is a monolithic CMOS circuit, which
has the ability to connect any of the 512 PCM channels of
16 incoming PCM lines to any of the 256 PCM channels of
eight output lines.
The PCM information for a complete frame is stored in the
4-Kbit speech memory SM, i.e. all of the 512 words with 8 bits
are written into a fixed position of the SM. This is controlled
by the input counter every 125 Vs. The words are read using
random access with an address that is stored in a connection
memory CM for each of the 256 output channels. The access
to the CM is controlled by the output counter.
To produce a connection the SM address and the CM
address must be written into the PEB 2045 via a HP interface.
The SM-address contains the time-slots and line numbers of
the incoming PCM words. The CM address consists of the
time-slots and line numbers of the output words.
The PEB 2045 can be connected to 2-Mbit/s, 4-Mbit/s and
8-Mbit/s PCM systems, the device clock may be either
4.096 MHz or 8.192 MHz.
In a second operational mode the PEB 2045 together with the
PEB 2035 (ACFA, Advanced CMOS Frame Aligner) and the
PEB 2235 (IPAT, ISDN Primary Access Transceiver)
implements the system interface of up to four primary
multiplex access lines. This interface can be configured for
2-Mbit/s, 4-Mbit/s and 8-Mbit/s systems; a clock shift for input
and output lines with half clock step resolution is
programmable. Selection of operating modes and
programming is made by writing to the mode register and, via
the Indirect Access Register (IAR), the Clock Shift Register
(CSR) and the General Configuration Register (GCR).
The components PEB 2045 and PEF 2045 are functionally
identical. The difference between the two types lies in the
temperature range. The PEB 2045 operates in the
temperature range 0 to 70 °C, the PEF 2045 in the range
- 40 to 85 °C.
Applications
. All types of switching systems
- Concentrator function
. Frequency transforming interface between 2-Mbit/s,
4-Mbit/s and 8-Mbit/s PCM systems
. 16/16 space switch for 8-Mbit/s PCM systems
. System interface for up to four primary multiplex access
lines in combination with the PEB 2035 (ACFA) and
*PEB 2235 (IPAT)
Siemens Aktiengesellschaft
PEB 2045
Type Package
PEB 2045-N P-LCC-44-1 (SMD)
PEB 2045-P P-DlP-40-1 (not for new design)
PEF 2045-N P-LCC-44-1 (SMD)
PEF 2045-P P-DIP-40-1 (not for new design)
Features
. Time/space switch for 2048-, 4.096- and 8.192-kbit/s
PCM systems
. Different kinds of modes (2048, 4096, 8192 kbit/s
or mixed mode)
. Switching of up to 512 incoming PCM channels to up to
256 outgoing PCM channels
. 16 input and eight output PCM lines
. Configurable for primary access and
standard applications
. Programmable clock shift with half clock
step resolution for input and output in primary access
configuration
. Configurable for a 4096- and 8192-kHz device clock
. Tristate function for further expansion and tandem
operation
. Tristate control signals for external drivers in primary
access configuration
2048-kHz clock output in primary access coMguration
Space switch mode
8-bit uP interface
Single + 5-V power supply
Advanced low power CMOS technology
Memory Time Switch CMOS (MTSC) PEB 2045
IN0 IN15
D7 - D0
PCM IN
P Connection
A0 Intélrface Memory
Address Gen
Timing Control
PCM OUT
Block Diagram SP CLK OUT (l OUT 7
ITB00554
Line Dual Rail Internal System
Interface Interface Primary Interface
1.544 Mbit l s Highway 2.048 /4.096/
2.048 Mbit I s 2.048 Mbit I s 8.192 Mbitls
PEB 2045
PEB 2235 PEB 2035
IPAT(E) ACFA
SAB 82525
HSCX ITB00544
ETHETHH
Optimized System Interface for Four Primary Multiplex Access Lines
Siemens Aktiengesellschaft 2
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