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PEB2035NV4.1 ,ACFA (Advanced CMOS Frame Aligner)Table of Contents Page1
PEB2035NV4.1 ,ACFA (Advanced CMOS Frame Aligner)applications, processes and circuits implemented within components or assemblies.The information de ..
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PEB2035N V4.1-PEB2035NV4.1-PEB2035N-V4.1-PEB2035NV4.1 .-PEB2035PV4.1-PEB2035P-V4.1
ACFA (Advanced CMOS Frame Aligner)
ICs for Communications
Advanced CMOS Frame Aligner
ACFA
PEB 2035

Data Sheet01.94
Edition 01.94
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München
© Siemens AG 1994.
All Rights Reserved.
Attention please!
As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.
The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies
and Representatives worldwide (see address list).
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your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.
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Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express
written approval of the Semiconductor Group of Siemens AG.A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the
General Information
Table of ContentsPageFeatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2Pin Configurations (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.3Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69Detailed Register Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
6.1Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119Package Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130Annex. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
Advanced CMOS Frame Aligner (ACFA)
CMOS IC
PEB 2035
1Features
Serial Interface to Line Interface UnitFrame alignment/synthesis for 2048kbit/s (CEPT,
PCM30) and 1544kbit/s (T1, PCM 24)Meets newest CCITT Rec’s (Blue Book), FTZ Rec’s and
AT&T technical advisories (DMI, August 1986)Programmable formats for
PCM 30: Doubleframe, CRC Multiframe
PCM 24: 4-Frame Multiframe (F4), 12-Frame Multiframe
(F12, D3/4), Extended Superframe (ESF), Remote Switch
Mode (F72)Selectable conditions for loss of syncSelectable line codes (HDB3, B8ZS, AMI with ZCS)Unipolar NRZ for interfacing fibre optical transmission
routesError checking via CRC4 or CRC6 proceduresInsertion and extraction of alarms and facility signalingIDLE code insertion for selectable channels

Microprocessor InterfaceParallel, demultiplexed microprocessor interface for random access to control and status
registersAlarm interrupt capabilitiesAccess to different signaling information:
– Sa-, E, Si -bits (register)
– Sa-bits (5-byte stack)
– FDL bits with the possibility of mixed insertion
– CCS, CAS-CC (common channel), CAS-BR (bit robbing) via 2/3-byte stacks with DMA/
interrupt supportExtensive test and diagnostic capabilities
GeneralAdvanced CMOS technologyLow power consumption (< 100mW)Packaging: P-DIP-40, P-LCC-44
1.1Introduction
The Advanced CMOS Frame Aligner PEB 2035 (ACFA) is a monolithic CMOS device which
implements the interface to primary rate PCM carriers. It may be programmed to operate in 24-
channel (T1) and 32-channel (CEPT) carrier systems.
The ACFA features include: selectable multiframe (six multiframe formats), error checking (CRC4,
CRC6), multiple line codes (HDB3, B8ZS, AMI), and programmable signaling paths. The device
includes functions which meet newest CCITT (Blue Book) and FTZ recommendations for primary
rate interfaces and the AT&T Digital Multiplexed Interface specifications (DMI) plus some additional
features requested by the market. Controlling and monitoring of the device is performed via a
parallel eight-bit microprocessor bus.
The circuit contains a two-frame elastic memory which ensures wander absorption between the
PCM carrier and a synchronous, system internal highway.
All signaling types - CCS, CAS and bit-robbed signaling in conjunction with Clear Channel
Capability - are supported by the ACFA. In addition, the ACFA allows flexible access to facility data
link and service channels. Extensive testing capabilities are included.
The ACFA is suitable for a wide range of voice and data applications. Below you find a list of
equipment as described by the CCITT which potential ACFA applications.
2048 kbit/s Applications
– PCM Multiplex equipment according to G.732, G.735, G.738.
– Digital Multiplex equipment according to G.736
– Digital Multiplex equipment according G.742, G745
– External Access equipment according to G.737, G.739
– Digital Exchange equipment according to G.705, Q.511, Q512
PEB 2035
PEB 2035
– Video Conferencing according to H120, H130
– Transcoder equipment according to G.761
– Digital circuit multiplication equipment according to G.763
– Digital section/line system according to G.921, G.952, G.956
1544 kbit/s
– PCM Multiplex equipment according to G.733
– Digital Multiplex equipment according to G.734
– Digital Multiplex equipment according G.743
– Digital Exchange equipment according to G.705, Q.511, Q512
– Transmultiplex equipment according to G.793
– Video Conferencing according to H.120, H.130
– Transcoder equipment according to G.762
– Digital circuit multiplication equipment according to G.763
– Digital section/line system according to G.951, G.955
– ADPCM multiplex equipment according to G.724
The ACFA is available in either P-DIP-40 or P-LCC-44 packages. As with all of the ISDN circuits
from Siemens, the ACFA has been implemented in advanced CMOS technology. Total power
consumption is less than 100mW.

Pin Configurations (cont’d)
(top view)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions (cont’d)
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions (cont’d)
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions (cont’d)
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions (cont’d)
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
1.3Pin Definitions and Functions (cont’d)
1.3Pin Definitions and Functions (cont’d)
PEB 2035
PEB 2035
Logic Symbol
(*) ISDN Primary Access Transceiver (IPAT®) PEB 2235/PEB 2236 for receive line clock recovery,
TTL/line voltage translation and pulse shaping.
Note:Some pins have mode dependent functions and thus may appear more than once in the logic
symbol.
Block Diagram
The ACFA comprises complete paths for receive and transmit direction for connecting the Primary
Access Line Interface Unit to the system internal PCM highway:
The Receive/Transmit Link Interface with encoder/decoder and alarm detectors connects the ACFA
to the Line Interface Unit (e.g. IPAT, PEB 2235/PEB 2236).
The Receiver/Transmitter perform frame alignment/synthesis, CRC checking/generation, alarm
and signaling extraction/insertion.
The Receive/Transmit Speech Memory compensates the wander and jitter of the assigned route
clock. Time-slot assignment to the system internal highway is also handled via this memory.
The parallel microprocessor interface can be used for controlling and monitoring of all functions and
alarms as well as extraction and insertion of signaling data. Additionally, a Direct Memory Access
(DMA) interface and bundel of specific signals enable powerful support for a varity of possible
external signaling controllers.
PEB 2035
PEB 2035System Integration
The Advanced CMOS Frame Aligner provides the interface between a primary rate PCM (T1 or
CEPT) transmission line and any digital system that connects to a 2048- or 4096-kbit/s PCM
highway. An example is given in figure 1, where the system interface is handled by a space-time
switch, in this case the Siemens PEB 2045 (MTSC). This figure shows an optimized implementation
of a complete Primary Access Interface (with CCS signaling) consisting of four CMOS circuits:
ACFA:Advanced CMOS Frame Aligner
HSCX:High-Level Serial Communication Controller Extended
MTSC:Memory Time Switch CMOS
IPAT:ISDN Primary Access Transceiver

Figure 1
Primary Access Interface
The ACFA provides several ways of accessing the signaling data which it extracts from/inserts into
the PCM carrier data stream. The example in figure 1 shows a case where signaling is sent to the
system internal highway in one of the (otherwise) unequipped time-slots, to be processed by an
autonomous signaling controller. In the case of message oriented common channel signaling
(CCS), an integrated solution is provided by the CMOS High-Level Serial Communication Controller
HSCX (SAB 82525).
This controller is able to extract and insert signaling messages in programmable one-bit steps up to
256-bit time-slots, and thus requires no extra hardware.
Since the CMOS Memory Time Switch is a switch for 256-output channels and the HSCX is actually
a dual channel controller, a quad primary access interface unit with non-blocking switch requires
only 11 devices:ACFAPEB 2035IPATPEB 2235HSCXSAB 82525MTSCPEB 2045,
as shown in figure 2.

Figure 2
Quad Primary Access Interface
PEB 2035
PEB 2035Functional Description
General Functions and Device Architecture
1. Receive Path
Receive Link Interface
For data input, two different data types with selectable input sense are supported:Dual rail data (PCM[+], PCM[–]) at ports RDIP, RDIM received from a line interface unit
(e.g. PEB2235/PEB 2236, Siemens ISDN Primary Access Transceiver, IPAT).Unipolar data at port ROID (PCM 30) or at port RDIP (PCM 24) received from a fibre optical
interface.
Latching of data is done using the falling edges of the Receive Route Clock (RRCLK, 2048kHz or
1544kHz) recovered from the PCM receive data stream. Dual rail data is subsequently converted
into a single rail, unipolar bit stream. In PCM 30 mode, the HDB3 line code is used along with double
violation detection or extended code violation detection (selectable). In PCM 24 mode, a selection
between B8ZS or simple AMI (ZCS) coding is provided. In this case, all code violations that do not
correspond to zero substitution rules will be detected.
These errors increment the code violation counter (8 or 10 bits length).
Note: In PCM 30 mode, this counter can also be used to count sub-multiframe error indications
instead of code violations.
When using the unipolar input mode, the decoder is by-passed and no code violations will be
detected.
Additionally, the receive link interface comprises the alarm detection for AIS (Alarm Indication
Signal: unframed bit stream with constant logical 'one') and NOS (No Signal: input signal with an
insufficient bit rate or an insufficient density of ones).
The single rail bit stream is then processed by the receiver.
Receiver
For both the PCM 30 mode and the PCM 24 mode the following functions are performed:Synchronization on pulse frameSynchronization on multiframeError indication when synchronization is lost. In this case, AIS is automatically sent to the system
side (this function can be disabled).Initiating and controlling of resynchronization after reaching the asynchronous state. This may be
automatically done by the ACFA, or user controlled via the microprocessor interface.Detection of remote alarm indication from the incoming data stream.Separation of service bits and data link bits. This information is stored in special status registers.Generation of control signals to synchronize the CRC checker, the parity generator, and the
receive speech memory write control unit.
If programmed and applicable to the selected multiframe format, CRC checking of the incoming
data stream is done by generating check bits for a CRC submultiframe (or ESF multiframe)
according to either the CRC 4 procedure (PCM 30, refer to CCITT Rec. G704) or the CRC 6
are received during the next CRC (sub-)multiframe. If there is at least one mismatch, the CRC error
counter will be incremented. As addition, this 8-bit counter (default) can be extended to 10-bit
length.
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined as
interrupt source for triggering interrupt port AINT.
Receive Speech Memory
The speech memory is organized as a two-frame elastic buffer with a size of 64 × 9 bit (PCM 30) or
48 × 9 bit (PCM 24) 9 bit include 8-bit channel data plus one parity bit.
The functions are:Clock adaption between system clock (SCLK) and route clock (RRCLK).Compensation of input wander and jitter. Maximum of wander amplitude (peak-to-peak):
PCM 30:190 UI (1 UI = 488ns)
PCM 24:126 UI in channel translation mode 0 (bit ACR.SLM reset)
142 UI in channel translation mode 0 (bit ACR.SLM set)
78 UI in channel translation mode 1
(1 UI = 644ns)
For detailed information on the channel translation modes.Frame alignment between system frame and receive route frameReporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is converted into bit-
parallel, channel-serial data which is circularly written to the speech memory using the Receive
Route Clock (RRCLK). At the same time, a parity signal is generated over each channel and also
stored in the speech memory.
Reading of stored data is controlled by the System Clock (SCLK) and the Synchronous Pulse
(SYPQ) in conjunction with the programmed offset values for the receive time-slot/clock-slot
counters. After conversion into a serial data stream and parity checking (errors are reported via the
status registers), the data is given out via port RDO. Channel parity information is output at port
RCHPY with selectable output sense. In PCM 24 mode, two channel translation modes are
provided. Unequipped time-slots will be set to ’FF’ hex. For both PCM modes, two bit rates (2048/
4096kbit/s) are selectable via the microprocessor interface.
Figure 3 gives an idea of operation of the receive speech memory:
A slip condition is detected when the write pointer (W) and the read pointer (R) of the memory are
nearly coincident, i.e. the write pointer is within the slip limits (S +, S –). The values of S + and S –
depend on the selected PCM mode, on the channel translation mode and on the value of bit
ACR.SLM. If a slip condition is detected, a negative slip (the next received frame is skipped) or a
positive slip (the previous received frame is read out twice) is performed at the system interface,
depending on the difference between RRCLK and SCLK, i.e. on the position of pointer R and W
within the memory.
PEB 2035
PEB 2035
Figure 3
The Receive Speech Memory as Circularly Organized Memory
Additionally in PCM 30 mode the receive speech memory can be switched to one frame length
(LOOP.SFM). This feature is useful for master-slave applications to reduce the delay between line
interface and system interface. For correct operation, System Clock SCLK and Synchronous Pulse
SYPQ have to be derived from the Receive Route Clock RRCLK and the Receive Frame
Synchronous Pulse RFSPQ (PLL application). In single frame mode, however, it is not possible to
perform a slip after the slip condition has been detected. Thus, values of receive time-slot/clock-slot
offset (RC0, RC1) have to be specified great enough to prevent too great approach of frame begin
(line side) and frame begin (system side).
2. Transmit Path
The inverse functions are performed for the transmit direction.
The PCM data is received from the system internal highway at port XDI with 2048kbit/s or
4096kbit/s. The channel assignment is equivalent to the receive direction. All unequipped time-
slots will be ignored.
The contents of selectable channels (time-slots) can be overwritten by the pattern defined via
register IDLE. The selection of ’idle channels’ is done by programming the three/four-byte register
bank ICB1…ICB3, ICB4.
In PCM 24 mode, additional signaling information can be provided on a separate input (XSIG).
Internal multiplexing of (speech) data and signaling data can be disabled on a per channel basis
(Clear Channel Capability). This is also valid when using the internal signaling stack.
Latching of data is controlled by the System Clock (SCLK) and the Synchronous Pulse (SYPQ) in
conjunction with the programmed offset values for the Transmit Time-slot/Clock-slot Counters.
Transmit Speech Memory
The transmit speech memory is operational only in the PCM 24 mode. This one-frame elastic buffer
with a size of 24 × 9 bit (8 bit channel data plus 1 parity bit) serves as a temporary store for the PCM
data to adapt the system clock (SCLK) to the externally generated Transmit Route Clock (XRCLK),
and to re-translate channel structure used in the system to that of the line side. Its optimal start
position is initiated when programming the above offset values. Normally, XRCLK has to be phase
locked to a common submultiple of SCLK such as 8kHz. A difference in the effective data rates of
system side and transmit side may lead to an overflow/underflow of the transmit speech memory:
thus, errors in data transmission to the remote end may occur. This error condition (transmit slip) is
reported to the microprocessor via the status registers. It signals that the external clock generation
is defective.
Maximum wander amplitude in PCM 24 mode (peak-to-peak):Channel translation mode 0: 58 UIChannel translation mode 1: 46 UI
(1 UI = 644ns)
Because this is, under normal circumstances, a rare error condition no automatic action is taken by
the transmit speech memory as opposed to the receive speech memory in the case of a positive or
negative slip. In this case the ACFA requires a re-initialization of the transmit memory by re-
programming of the transmit time-slot counter. After that, this memory has its optimal start position.
In PCM 30 mode, the Transmit Route Clock (XRCLK) is derived directly from the system clock by
an internal clock divider. Consequently, the data received from the system interface is switched
through without the need of intermediate storage.
The parity generation/checking mechanism is symmetrical to the receive path. The channel data is
checked with the channel parity information generated internally or externally (input at port XCHPY
with selectable input sense). Errors are reported to the microprocessor interface. To avoid
difficulties with external parity generation, the parity signal for non-speech data (e.g. signaling data
or channels with bit robbing information) is computed internally.
PEB 2035
PEB 2035
Transmitter
The serial bit stream is then processed by the transmitter which has the following functions:Frame/multiframe synthesis of one of the six selectable framing formatsInsertion of service and data link informationRemote alarm generationCRC generation and insertion of CRC bits
Note: As addition in PCM 24 mode, all CRC bits of one outgoing extended multiframe are
inverted in case a CRC error is flagged for the previous received multiframe (function is enabled
via bit GCR.CRCI).
In PCM 24 mode, the transmitter of the ACFA can be synchronized externally for multiframe begin
(port XCHPY, bit ACR.EXMF). This feature is required if the bit-robbed signals are routed through
the switching network and are inserted in transmit direction via the system interface.
Transmit Link Interface
Similar to the receive link interface two different data types with selectable output sense are
supported:Dual rail data (PCM[+], PCM[–]) at ports XDOP, XDOM with 50% or 100% duty cycle (bit
EMOD.XFB) transmitted to a line interface unit, e.g. PEB 2235, Siemens ISDN Primary Access
Transceiver, IPAT. Single rail data is converted into a dual rail bit stream. In PCM 30 mode, the
HDB3 line code is employed. In PCM 24 mode, selection between B8ZS or simple AMI coding
with zero code suppression (B7 stuffing) is provided. B7 stuffing can be disabled on a per
channel basis (clear channel capability).Unipolar data at port XOID (PCM 30) or at port XDOP (PCM 24) with 100% duty cycle
transmitted to a fibre optical interface.
Clocking off data is done with the positive transitions of the transmit route clock: XRCLK (2048kHz
or 1544kHz). In PCM 30 mode, XRCLK is generated by the ACFA, whereas in PCM 24 mode it
must be generated by an external clock generator.
Additionally, the dual rail outputs XTOP and XTOM are provided for test applications.
3. Additional Functions
Signaling Support
Generation of all supporting signals to achieve simple access to signaling information (CCS, CAS-
CC, CAS-BR, FDL) at the system interface. In PCM 24 mode, the additional input XSIG is provided
for connection to a bit-robbed signaling controller. Furthermore, the controlling of the internal
signaling stacks is done by this unit.
For support of common PCM 24 applications, clear channels can be specified via the 3-byte register
bank CCB1…CCB3.
Alarm Interrupt
Normally, the control of data transmission via the PCM line is done by polling the internal status
registers of the ACFA at equidistant time intervals.
However, for fast error handling the option exists to configure a specific output port as interrupt port
(AINT). This signal may be connected to an interrupt input of the board processor. Triggering of this
output may be caused by up to 11 (PCM 30) or 9 (PCM 24) maskable interrupt sources.
Single Channel Loop Back
As one of the extended test options, the single channel loop back enables reflection of a selected
channel back to the system interface at port RDO.
Idle Code Insertion
In transmit direction, the contents of selectable channels can be overwritten by the pattern defined
via register IDLE. The selection of 'idle channels' is done by programming the three/four-byte
register bank ICB1…ICB3, ICB4.
PEB 2035
PEB 2035
Operating Modes
The operating mode of the ACFA is selected by programming the carrier data rate, line code,
multiframe structure, and signaling scheme.
The ACFA implements all of the standard and/or common framing structures for both PCM 30
(CEPT, 2048kbit/s) and PCM 24 (T1, 1544kbit/s) carriers. These are summarized in table 1, along
with the signaling types applicable in each of the multiframe formats. ’General signaling’ refers to the
support the ACFA provides for handling the data link or service bits, as the case may be, in the
multiframe.
Table 1
Summary of ACFA Framing and Supported Signaling Modes
CCS=Common Channel Signaling
CAS-CC=Channel Associated Signaling (Common Channel)
CAS-BR=Channel Associated Signaling (Bit Robbing)
For CCS, CAS-CC, and CAS-BR, different types of support are provided.
Note: All signaling procedures (e.g. HDLC), signaling frame synchronization and synthesis have to
be performed by an external controller (e.g. SAB 82525, HSCX for CCS).
The next pages give a general description of the PCM modes and their assigned framing formats.
After RESET, the ACFA is switched to PCM 30 doubleframe format automatically.
PCM 30 Mode
Bit: MODE.PMOD = 0
General
PCM line bit rate:2048kbit/s ± 50ppm
Single frame length:256 bit, No.1…256
Framing frequency:8kHz
Organization:32 time-slots, No.0…31
with 8 bits each, No.1…8
time-slot 0 is reserved for frame alignment word and service information. Switching between the two
applicable framing formats (doubleframe/CRC-multiframe) is done via bit MODE.CRC.
Line InterfacingDual rail data with HDB3 coding in conjunction with double violation detection or extended code
violation detection (CCR.EXTD). Errors can be counted by the Code Violation Counter CVC with
8- or 10-bit length (selectable via bit EMOD.ECVE).Single rail unipolar data (MODE.OPT) with no zero suppression algorithm.
General AlarmsAIS: Detection is flaggered by bit RSR.AIS. Transmission is enabled via port COS or bit
MODE.XAIS.NOS: Detection is flagged by bit RSR.NOS.RAI: Remote Alarm Indication is flagged by bit RSR.RRA and RSW.RRA. Transmission is
enabled via bit XSW.XRA.
Channel Assignment
The channel (time-slot) assignment from the PCM line to the system internal highway is performed
without any changes of channel numbering (TS0 ↔ TS0,…, TS31 ↔ TS31). In receive direction,
the contents of time-slot 0 are switched through transparently. In transmit direction, contents of
time-slot 0 of the outgoing PCM frame are normally generated by the ACFA. Additionally, one of
three transparent modes (XSP.TT0S, XSP.TT0, EMOD.TT0X) can be selected to achieve
transparency either for Sn -, Si -bit information of for the complete time-slot 0.
PEB 2035
PEB 2035
General SignalingSa bits in accordance with CCITT Blue Book G.704.E bits in accordance with CCITT Blue Book G.704.
SignalingCCS
For Common Channel Signaling the use of time-slot 16 is recommended. The use of CCS is
allowed with both the doubleframe and the CRC-multiframe format.CAS-CC
For Channel Associated Signaling the use of time-slot 16 is recommended. The autonomous
CAS multiframe structure is not related to a doubleframe or a CRC-multiframe structure (refer to
CCITT G.704).
Note: CAS multiframe synchronization and synthesis is not performed by the ACFA.
Doubleframe Format
The framing structure is defined by the contents of time-slot 0 (refer to table 2).
Table 2
Allocation of Bits 1 to 8 of Time-Slot 0
Notes:1. Si bits: reserved for international use. If not used, these bits should be fixed to ’1’. Access
to received information via bits RSW.RSIS and RSP.RSIF. Transmission is enabled via bits
XSW.XSIS and XSP.XSIF.
2. Fixed to ’1’. Used for synchronization.
3. Remote alarm indication: In undisturbed operation ’0’; in alarm condition ’1’.
4. Sa bits: Reserved for national use. If not used, they should be fixed at ’1’. Access to
received information via bits RSW.RY0…RY4. Transmission is enabled via bits
XSW.XY0…XY4. (*)
For transmit direction, contents of time-slot 0 are additionally determined by the selected
transparent mode: a - Bit Access
As an extension for access to Sa-bit information via registers RSW and XSW a new option is
implemented to allow the usage of internal Sa-bit stacks RSN and XSN in doubleframe format.
This function is enabled by setting MODE.CRC = 1, MODE.ENSN = 1 and EMOD.DFSN = 1.
The new function uses an internal 16-frame structure but no CRC multiframe alignment/generation
is performed although MODE.CRC is set to one. For more details refer to chapter CRC-Multiframe
and to description of status flags RFLG and XFLG.
Synchronization Procedure
Synchronization status is reported via bit RSR.LOS. Framing errors are counted by the Framing
Error Counter (FEC). Asynchronous state is reached after detecting 3 or 4 consecutive incorrect
FAS words or 3 or 4 consecutive incorrect service words (bit 2 ≠ 1 in time-slot 0 of every other frame
not containing the frame alignment word), the selection is done via bit RC1.ASY4. Additionally, the
service word condition can be disabled.
In asynchronous state, counting of framing errors will be stopped and AIS is automatically sent to
the system internal highway (can be disabled via bit EMOD.DAIS).
The resynchronization procedure starts automatically after reaching the asynchronous state.
Additionally, it may be invoked user controlled via bit: CCR.FRS (Force Resynchronization: the FAS
word detection is interrupted. In connection with the above conditions this will lead to asynchronous
state. After that, resynchronization starts automatically).
Synchronous state is reached after detecting:a correct FAS word in frame n,the presence of the correct service word (bit 2 = 1) in frame n + 1a correct FAS word in frame n + 2.
Undisturbed operation starts with the beginning of the next doubleframe.Note: As a special extension for double frame format, the Sn-bit stack may be used optionally.
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CRC-Multiframe
The multiframe structure shown in table 3 is enabled by setting bit: MODE.CRC.
Multiframe:2 submultiframes = 2 × 8 frames
Frame alignment:refer to section Doubleframe Format
Multiframe alignment:bit 1 of frames 1, 3, 5, 7, 9, 11 with the pattern ‘001011’
CRC bits:bit 1 of frames 0, 2, 4, 6, 8, 10, 12, 14
CRC block size:2048 bit (length of a submultiframe)
CRC procedure:CRC4, according to CCITT Rec. G704
Table 3
CRC-Multiframe Structure
E: Spare bits for international use. Access to received information via bits RSP.RS13 and
RSP.RS15. Transmission is enabled via bits XSP.XS13 and XSP.XS15. Additionally, automatic
transmission for submultiframe error indication is selectable.
Sa: Spare bits for national use. Additionally, the 5-byte stacks RSN and XSN are provided.
C1..C4: Cyclic redundancy check bits
A: Remote alarm indication
For transmit direction, contents of time-slot 0 are additionally determined by the selected
transparent mode:
Notes:The Sa-bit stack XSN may be used optionally.Additionally, automatic transmission of submultiframe error indication is selectable.
The CRC procedure is automatically invoked when the multiframe structure is enabled. CRC errors
in the received data stream are counted by the CRC Error Counter CEC (one error per
submultiframe, maximum). This 8-bit counter is extendable to 10-bit length (XSP.AXS, CECX).
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can be defined as
interrupt source (XC1.MCA) for triggering interrupt port AINT.
Synchronization Procedure
Multiframe alignment is assumed to have been lost if doubleframe alignment has been lost (flagged
at bit RSR.LOS and bit RSR.CAL).
The multiframe resynchronization procedure starts when Doubleframe alignment has been
regained. For Doubleframe synchronization refer to section Doubleframe Format. It may also be
invoked by the user by settingbit CCR.FRS for complete Doubleframe and multiframe re-synchronizationbit MODE.MFCS for multiframe re-synchronization only.
The CRC checking mechanism will be enabled after the first correct multiframe pattern has been
found. However, CRC errors will not be counted in asynchronous state.
The (multiframe) synchronous state is reached after detecting two correct multiframe alignment
patterns at an interval of n×2ms (n = 1,2,3 …). The CRC4 flag RSR.CAL will be reset. Checking
the multiframe pattern is disabled when the receiver is in the synchronous state.
Automatic Force Resynchronization
As addition, a search for Doubleframe alignment is automatically initiated if two multiframe pattern
with a distance of n×2ms have not been found within a time interval of 8ms after doubleframe
alignment has been regained (bit MODE.AFR).a - Bit Access
Due to new signaling procedures using the five Sa bits (Sa4…Sa8) of every other frame of the CRC
multiframe structure, two possibilities of access via the microprocessor are implemented.
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PEB 2035The standard procedure allows reading/writing the Sa-bit registers RSW, XSW without further
support. The Sa-bit information will be updated every other frame.The advanced procedure, enabled via bit MODE.ENSN, allows reading/writing two Sa-bit stacks
RSN, XSN with a size of 5 bytes. The two status bits RSP.RFLG and RSP.XFLG require
updating the stack information by reading/writing five bytes per multiframe from/to the assigned
stack address.To avoid loss of information, the status bits should be monitored at time intervals
less than 2 ms (1.5 ms recommended). With the first access to a stack, the associated status bit
will be reset.
Additionally, a transmit or receive multiframe begin interrupt is provided if alarm interrupt mode
is enabled (CCR.AINT) and bits XSP.MXMB or XSP.MRMB are set.
Organization of the Stacks
The sequently received Sa bits (Sa4 up to Sa5) of odd numbered frames of the multiframe structure
are re-organized to bytes containing the Sa-information of the same level (Sa4 byte up to Sa8 byte).
The Sa8 byte is the first byte to read or to write via the microprocessor interface (refer to table 4).
Moreover, Sa bits may be processed via the system interface. Setting bit XSP.TT0S or EMOD.TT0X
enables transparency for Sn bits in transmit direction (refer to table 3).
Table 4
Organization of the Sn-Bit Stacks
Microprocessor
Interface
E-Bit Access
Due to newest signaling requirements, the E bits of frame 13 and frame 15 of the CRC multiframe
can be used to indicate received errored submultiframes:
Submultiframe Istatus→E-Bit located in frame 13
Submultiframe IIstatus→E-Bit located in frame 15CRC error:E = 1
CRC error:E = 0
Standard Procedure
After reading the Submultiframe Error Indication SEI.SI1 and SEI.SI2, the microprocessor has to
update contents of register XSP (XS13, XS15). Access to these registers has to be synchronized to
assigned multiframe begin. This can be done by evaluating the Transmit/Receive Multiframe Flags
(RSP.XFLG, RSP.RFLG) or by activating Transmit/Receive Multiframe Begin Interrupts
(CCR.AINT, XSP.MXMB, XSP.MRMB).
Automatic Mode
By setting bit XSP.AXS status information of received submultiframes is automatically inserted in E-
bit position of the outgoing CRC Multiframe without any further interventions of the microprocessor.
Submultiframe Error Indication Counter
If programmed via bit EMOD.ESEI, counter CVC (8 or 10 bits) counts zeros in E-bit position of frame
13 and 15 of every received CRC Multiframe. This counter option gives information about the
outgoing transmit PCM line if the E bits are used by the remote end for submultiframe error
indication.
Note:E bits may be processed via the system interface. Setting bit XSP.TT0S enables
transparency for E bits (and Sa bits) in transmit direction (refer to table 3).
PCM 24 Mode
Activated with bit MODE.PMOD = 1.
General
PCM line bit rate:1544 kbit/s ± 50 ppm
Single frame length:193 bit, No. 1…193
Framing frequency:8 kHz
Organization:24 time-slots, No. 1…24
with 8 bits each, No. 1…8 and one preceding F bit
Selection of one of the four permissible framing formats is performed by bits GSR.FM0 and
GSR.FM1. These formats are::4-frame multiframe
F12:12-frame multiframe (D3/D4)
ESF:Extended Superframe
F72:72-frame multiframe (remote switch mode)
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Line InterfacingDual rail data with B8ZS or AMI(ZCS) coding (selection via bit MODE.CODE). All code violations
which do not correspond to zero code substitution rules are registrated by the Code Violation
Counter (CVC) with 8- or 10-bit length (selected via bit EMOD.ECVE).
If AMI coding with zero code suppression (B7-stuffing) is selected, ‘clear channels’ without B7-
stuffing can be defined by programming registers CCB1 … CCB3.Single rail unipolar data with no zero suppression algorithm (MODE.OPT = 1).
General Aspects of Synchronization
Synchronization status is reported via bit RSR.LOS (Loss Of Synchronization). Framing errors
(pulse frame and multiframe) are counted by the Framing Error Counter FEC.
Asynchronous state is reached if
2 out of 4 (bit RC1.SLC reset), or
2 out of 5 (bit RC1.SLC set)
framing bits (terminal framing or multiframing) are incorrect. If auto-mode is enabled, counting of
framing errors is interrupted.
The resynchronization procedure can be controlled by either one of the following procedure:automatically (GCR.AUTO = 1). Additionally, it may be triggered by the user by setting/resetting
one of the bits CCR.FRS (Force Resynchronization) or CCR.EXLS (External Loss of Frame).user controlled, exclusively, via above control bits in the non-auto-mode (GCR.AUTO = 0).
Addition for F12 and F72 Format
FT and FS bit conditions, i.e. pulse frame alignment and multiframe alignment can be handled
separately if programmed via bit EMOD.SSP. Thus, a multiframe re-synchronization can be
automatically initiated after detecting 2 errors out of 4/5 consecutive multiframing bits without
influencing the state of the terminal framing.
In the synchronous state, the setting of CCR.FRS or CCR.EXLS resets the synchronizer and
initiates a new frame search. The synchronous state is reached if there is only one definite framing
candidate. In the case of repeated apparent simulated candidates, the synchronizer remains in the
asynchronous state.
In asynchronous state, the function of CCR.EXLS is the same as above. Setting bit CCR.FRS
induces the synchronizer to lock onto the next available framing candidate if there is one.
Otherwise, a new frame search is started. This is useful in case the framing pattern that defines the
pulseframe position is imitated periodically by a pattern in one of the speech/data channels. The F-
bit Error History (FSR.FEH5 … 0) may be used in the decision whether to initiate resynchronization.
The updating of these bits depends on the resynchronization mode:Auto mode: updating only during the synchronous state.Non-auto-mode: updating during the synchronous state and
until one of the above control bits are set during the asynchronous state.
The control bit CCR.EXLS should be used first because it starts the synchronizer to search for a
definite framing candidate.
To observe actions of the synchronizer, the Frame Search Restart Flag RSR.FSRF is implemented.
When resynchronization is initiated, the following values apply for the time required to achieve the
synchronous state in case there is one definite framing candidate within the data stream:
Table 5
Resynchronization Timing
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Figure 4
Influences on Synchronization Status
Figure 4 gives an overview of influences on synchronization status for the case of different external
actions. Activation of auto-mode and non-auto-mode is performed via bit GSR.AUTO. Generally, for
initiating resynchronization it is recommended to use bit: CCR.EXLS first. In case where the
synchronizer remains in the asynchronous state, bit CCR.FRS may be used to enforce it to lock
onto the next framing candidate, although it might be a simulated one.
General AlarmsAIS: Detection is flagged by bit RSR.AIS. Transmission is enabled via port COS or bit
MODE.XAIS.NOS: Detection is flagged at bit RSR.NOS.RAI: Remote Alarm Indication is flagged at bit RSR.RRA. Transmission is enabled via bit
GCR.XRA. The type of remote alarm indication depends on the selected multiframe format.
Channel Assignment
Two possibilities are provided for converting the 24 speech channels to the 32 time-slots on the
system internal highway (refer to section Interface to System Internal Highway). The selection is
performed via bit MODE.CTM. Transparent mode setting bit GCR.TM switches the ACFA in
transparent mode:In transmit direction bit 8 of the FS/DL time-slot from the system internal highway (XDI) is
inserted
in the F-bit position of the outgoing frame.In receive direction the framing bit is also forwarded to RDO and inserted in the FS/DL time-slot.
Bit RDCF (bit 1 of FS/DL time-slot) indicates a DL bit.
General Signaling
For data link or signaling applications, it may be necessary to have external access to the FS bits
(F4 and F72 format) or to the DL bits of the extended superframe. Two methods of access are
provided:in a defined FS/DL time-slot of the PCM data stream on the system internal highwayby reading and writing special registers via the microprocessor interface (RFDL, XFDL).
Simultaneous use of both of these modes is permitted. For this application, FS/DL subchannels for
transmit direction may be programmed on a bit-by-bit basis over 12 frames via the additional mask
register FMR. They are accessed via the microprocessor interface while the other subchannels are
passed transparently from the system internal highway to the FS/DL-bit position of the assigned
outgoing 193-bit frame.
A combination of the two accessing methods only makes sense when using the more complex
multiframing formats (ESF, F72) to get a defined FS/DL subchannel assignment. For the 4-frame
multiframe structure, all mask bits are normally to be set to the same logical level.
Additional Support: 4-kHz DL clock
If programmed via bit ACR.DLC, ports RCHPY and XCHPY provide signals which mark the DL-bit
position within the data stream at RDO and XDI.
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Signaling
The selection of the signaling scheme is done via bit MODE.SIGM.CCS
MODE.SIGM = 0
For Common Channel Signaling, the use of time-slot 24 is recommended. In channel translation
mode 1 channel 17 (corresponding to time-slot 16 on the system internal highway) may be
selected instead of channel 24 by programming the bit FMR.SM24. The use of CCS is permitted
for all multiframe formats.CAS-CC
MODE.SIGM = 0
Instead of CCS the above channels may be used for carrying CAS information. For positioning
of the CAS multiframe with respect to the selected multiframe structure, refer to DMI, part III,12.1.
Note: Synchronization to and synthesis of the CAS multiframe is not performed by the ACFA.
The use of CAS-CC is permitted for all multiframe formats.CAS-BR
MODE.SIGM = 1
The use of CAS bit robbing mode is applicable to F12, ESF, and F72 multiframe format.
Especially when using the CAS-BR signaling schemes it could be necessary to define ‘clear
channels’ for data transmission. By programming registers CCB1 … CCB3 they can be selected on
a per channel basis.
4-Frame Multiframe
The allocation of the FT bits (bit 1 of frames 1 and 3) for frame alignment signal is shown in table 6.
The FS bit may be used for signaling.
Remote alarm is indicated by setting bit 2 to ’0’ in each channel.
Table 6
4-Frame Multiframe Structure
Synchronization Procedure
For multiframe synchronization, the terminal framing bits (FT bits) are observed. The synchronous
state is reached if at least one terminal framing candidate is definitely found, or the synchronizer is
forced to lock onto the next available candidate (CCR.FRS).
12-Frame Multiframe
Normally, this kind of multiframe structure only makes sense when using the CAS bit robbing mode.
In addition, CCS and CAS-CC are also allowed. The multiframe alignment signal is located at the
FS-bit position of every other frame (refer to table 7).
There are two possibilities of remote alarm indication:bit 2 = 0 in each channel of a frame, selected with bit CCR.SRAF= 0the last bit of the multiframe alignment signal (bit 1 of frame 12) changes from ‘0’ to ‘1’, selected
with bit CCR.SRAF = 1.
Synchronization Procedure
In the synchronous state terminal framing (FT bits) and multiframing (FS bits) are observed,
independently. Further reaction on framing errors depends on the selected sync/resync procedure
(via bit EMOD.SSP):EMOD.SSP = ‘0’: terminal frame and multiframe synchronization are combined.
Two errors within four/five framing bits (via bit RC1.SLC) of one of the above will lead to the
asynchronous state for terminal framing and multiframing. Additionally to the bit RSR.LOS, loss
of multiframe alignment is reported via bit FSR.MLOS.
The resynchronization procedure starts with synchronizing upon the terminal framing. If the
pulseframing has been regained, the search for multiframe alignment is initiated. Multiframe
synchronization has been regained after two consecutive correct multiframe patterns have been
received.EMOD.SSP = ‘1’: terminal frame and multiframe synchronization are separated
Two errors within four/five terminal framing bits will lead to the same reaction as described above
for the ‘combined’ mode.
Two errors within four/five multiframing bits will lead to the asynchronous state only for the
multiframing. Loss of multiframe alignment is reported via bit FSR.MLOS. The state of terminal
framing is not influenced.
Now, the resynchronization procedure includes only the search for multiframe alignment.
Multiframe synchronization has been regained after two consecutive correct multiframe patterns
have been received.
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Table 7
12-Frame Multiframe Structure
Extended Superframe
The use of the first bit of each frame for the multiframe alignment word, the data link bits, and the
CRC bits is shown in table 8.
Table 8
Extended Superframe Structure
The CRC6 checking algorithm is enabled via bit MODE.CRC. If not enabled, all check bits in the
transmit direction are set to ‘1’.
Additions:CRC6 Inversion
If enabled via bit GCR.CRCI, all CRC bits of one outgoing extended multiframe are
inverted in case a CRC error is flagged for the previous received multiframe.
CRC Alarm Interrupt
As an extension of the alarm interrupt capabilities, the occurrence of a CRC error can
be defined as interrupt source (XC1.MCA) for triggering interrupt port AINT.
Remote alarm is indicated by the periodical pattern ‘1111 1111 0000 0000 …’ in the DL bits.
All signaling schemes are applicable for this multiframing structure. For external access to the DL
bits, refer to section General.
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Synchronization Procedure
For multiframe synchronization the FAS bits are observed. Synchronous state is reached if at least
one framing candidate is definitely found, or the synchronizer is forced to lock onto the next
available candidate (CCR.FRS).
72-Frame Multiframe
As a special kind of the 12-frame structure, an alternate use of the FS-bit pattern is defined for
carrying data link information. This is done by stealing some of redundant multiframing bits after the
transmission of the 12-bit framing header (refer to table 9). The position of A and B signaling
channels (bit robbing mode) is defined by zero-to-one and one-to-zero transitions of the FS bits and
is continued when the FS bits are replaced by the data link bits. The use of this 24-bit data link
channel, however, is not specified by the ACFA. For access to these bits refer to section General.
Remote Alarm is indicated by setting bit 2 to zero in each channel. An additional use of the D bits
for alarm indication is user defined and must be done externally.
In addition to CAS-BR, CCS and CAS-CC are also applicable to this multiframe structure.
Synchronization Procedure
In the synchronous state terminal framing (FT bits) and multiframing (FS bits of the framing header)
are observed independently. Further reaction on framing errors depends on the selected sync/
resync procedure (via bit EMOD.SSP):EMOD.SSP = ‘0’: terminal frame and multiframe synchronization are combined
Two errors within four/five framing bits (via bit RC1.SLC) of one of the above will lead to the
asynchronous state for terminal framing and multiframing. Additionally to the bit RSR.LOS, loss
of multiframe alignment is reported via bit FSR.MLOS.
The resynchronization procedure starts with synchronizing upon the terminal framing. If the
pulseframing has been regained, the search for multiframe alignment is initiated. Multiframe
synchronization has been regained after two consecutive correct multiframe patterns have been
received.EMOD.SSP = ‘1’ : terminal frame and multiframe synchronization are separated
Two errors within four/five terminal framing bits will lead to the same reaction as described above
for the ‘combined’ mode.
Two errors within four/five multiframing bits will lead to the asynchronous state only for the
multiframing. Loss of multiframe alignment is reported via bit FSR.MLOS. The state of terminal
framing is not influenced.
Now, the resynchronization procedure includes only the search for multiframe alignment.
Multiframe synchronization has been regained after two consecutive correct multiframe patterns
have been received.
Table 9
72-Frame Multiframe Structure
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PEB 2035Interfaces
Interface to Primary Rate PCM Carriers
Receive Direction
RDIPIReceive Data In Plus
RDIMIReceive Data In Minus
RRCLKIReceive Route Clock
Transmit Direction
XDOPOTransmit Data Out Plus
XDOMOTransmit Data Out Minus
XRCLKTransmit Route ClockPCM 30: provided by the ACFAPCM 24: Generated externally
The above signals are to be used for the connection to a Line Interface Unit (LIU) such as the
Siemens PEB 2235/PEB 2236, IPAT. Latching data on RDIP/RDIM is done on the falling edge of
RRCLK. Normally, RRCLK is extracted from the incoming data stream by the LIU. Clocking off data
at XDOP/XDOM is done on positive transitions of XRCLK with 50 % or 100 % duty cycle (selectable
via bit EMOD.XFB). To simplify different types of line interface units, the input sense of RDIP/RDIM
and the output sense of XDOP/XDOM are selectable via bits RC0. RDIS and XC0.XDOS.
Line CodesPCM 30:HDB3
PCM 24:B8ZS(MODE.CODE = 1)
AMI (ZCS)(MODE.CODE = 0)
Interface to Fibre Optical System
The use of the fibre optical interface is alternative to the use of the PCM carrier interface. Its
activation is performed via bit MODE.OPT, which enables reception and transmission of unipolar
uncoded data.
Receive Direction
ROIDIPCM 30: Receive Optical Interface Data
RDIP/RDIM are ignored.
RDIPIPCM 24: Receive Data In Plus
RDIM has no function.
RRCLKIas above
Transmit Direction
XOIDOPCM 30: Transmit Optical Interface Data
XDOPOPCM 24: Transmit Data Out Plus
XDOM should be ignored.
XRCLKI/Oas above
The inputs for unipolar data (ROID, RDOP) are latched on the falling edge of RRCLK. Outputs XOID
and XDOP are clocked off on positive transitions of XRCLK with 100 % duty cycle. The input/output
sense is selectable via the same control bits (RC0.RDIS, XC0.XDOS) as for the PCM carrier
interface ports. However, in the PCM 30 mode, the sense for ROID and XOID is opposite to RDIP/
RDIM and XDOP/XDOM.
Interface to Clock Generator
SCLKISystem (station) Clock
with 4096/8192 kHz. Selection is performed by bit XC1.SCLK
SYPQISynchronous Pulse
defines the beginning of the frame on the receive/transmit system internal
highway in conjunction with the values of the assigned time-slot/clock-slot
counters (RC0.RCO, RC1.RTO, XC0.XCO, XC1.XTO).
XRCLKIPCM 24: as above
RFSPQOReceive Frame Synchronous Pulse
8-kHz framing pulse derived from the received PCM route signal. It may
be used for PLL applications in master-slave configurations.
Interface to System Internal Highway
SCLKIas above
SYPQIas above
RDOOReceive Data Out
system internal receive 2048/4096 kbit/s highway. clocking off of the data
is done on negative transitions of SCLK. The beginning of time-slot 0 is
defined by SYPQ and the offset values of the Receive Clock-slot and
Time-slot Counters RC0.RCO, RC1.RTO (refer to figure 5).
XDIITransmit Data In
system internal transmit 2048/4096 kbit/s highway. Latching of the data is
done on negative transitions of SCLK. The beginning of time-slot 0 is
defined by SYPQ and the offset values of the Transmit Clock-slot and
Time-slot Counters: XC0.XCO, XC1.XTO (refer to figure 6).
The selection of the data is performed via bit MODE.IMOD.
In PCM 24 mode, only 24 of the 32 time-slots on RDO and XDI are used. The rest of the unequipped
time-slots are set to ‘FF’ hex (RDO) or ignored (XDI), except time-slot 0 or 31 which is used to carry
FS/DL information. The two possible channel translation modes are shown in table 10.
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Figure 5
Data on RDO
Figure 6
Data on XDI
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Table 10
Channel Translation Modes for PCM 24
S: CCS/CAS-CC signaling channel
The formats for FS/DL data transmission via the system interface are as follows:
Receive Direction
FS/DL bits on system internal receive highway (RDO), time-slot 0 to 31
Figure 7
Receive FS/DL Bits on RDO
Each data bit is repeated for two frames. The reception of a new FS/DL bit is indicated by the
Receive Data Change Flag (normal operation: RDCF toggles; transparent mode enabled via bit
GCR.TM: RDCF is set, if the FS/DL bit-slot contains valid DL information). For further support in
locating optionally defined subchannels, the Receive Multiframe Flag and the Transmit Multiframe
Flag are provided for marking the beginning of the multiframe. In addition, the signals RMFB and
XMFB may be used for that purpose.
Transmit Direction
FS/DL data on system internal transmit highway (XDI), time-slot 0 or 31

Figure 8
Transmit FS/DL Bits on XDI
The FS/DL bit of every second frame is inserted into the transmit FS/DL-bit location of the assigned
outgoing 193-bit frame.
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Interface to Signaling Controller
SCLKIas above
SYPQIas above
RDOOas above
XDIIas above
RSIGMOReceive Signaling Marker
It marks all signaling bits on RDO.
XSIGMOTransmit Signaling Marker
It marks all signaling bits on XDI.
RREQOReceive DMA/Interrupt Request
Enabled via bit XC0.ISIG. It requires read access to the internal Receive
Signaling Stack RSIG.
XREQOTransmit DMA/Interrupt Request
Enabled via bit XC0.ISIG. It requires write access to the internal Transmit
Signaling Stack XSIG.
ACKNLQIDMA/Interrupt Acknowledge
Enabled via bit XC0.ISIG. This input acts as access enable to the
signaling stacks for I/O-to-memory DMA applications.
XSIGIPCM 24: Transmit Signaling Data
Additional system internal transmit highway input for signaling data. Used
if the switching network circuits are not able to tri-state their outputs.
Normally, this will be used for CAS-BR applications.
RMFBOPCM 24: Receive Multiframe Begin
It marks the beginning of every received multiframe on RDO. Additional
pulses every twelve frames are provided in ESF and F72 format to enable
easy access to FS/DL information which may be used for synchronizing
an external controller. Generation of these additional pulses can be
disabled via bit ACR.MFBS. For interrupt applications, the internal status
bits MFR.RRS and MFR.RMB may be used in conjunction with the
acknowledge bit XFDL.RMAK.
XMFBOPCM 24: Transmit Multiframe Begin
Its function is equivalent to RMFB for the transmit direction. Associated
bits: MFR.XRS, MFR.XMB, XFDL.XMAK and also ACR.MFBS.
FREEZSOPCM 24: Freeze Signaling
Synchronization status signal which informs the signaling controller that
current signaling should be frozen.
AFROPCM 24: Additional Function Receive
If enabled via bit ACR.DLC, this signal provides a 4-kHz DL clock which
marks the DL-bit position within the data stream at RDO.
AFTOPCM 24: Additional Function Transmit
If bit ACR.EXMF is reset, its function is equivalent to AFR for the transmit
direction.If bit ACR.EXMF is set, this input signal can be used to synchronize the
transmitter of the ACFA externally for multiframe begin.
Signaling Support
The above signals may be used to support different signaling applications for CCS, CAS-CC, or
CAS-BR. For each method, different ways of access to signaling data are implemented:
Access viaan intelligent controller without the need of supporting signals (e.g. SAB 82525, HSCX)a controller supported by the ACFAa DMA controllerthe board microprocessorAccess via an Intelligent Controller
Applications: CCS, (CAS-CC)
The intelligent controller is able to locate the signaling data on the system internal highway by itself
when supplied with the synchronous pulse SYPQ of the system (see figure 9). In PCM 24
applications, the normally unused input XSIG has to be connected to XDI.
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Connection of an Intelligent Signaling Controller Access via a Signaling Controller Supported by the ACFA
Applications: CCS, CAS-CC, CAS-BR
The supporting signals enable easy access to signaling data on the system internal highway (see
figures 10 to 14).

Figure 10
Connection of a Supported CCS/CAS-CC Controller
Figure 11
Connection to a CAS-BR Controller (PCM 24 mode only)
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Figure 12
Figure 13
Supporting Signals for CAS-BR Applications (PCM 24 mode only)
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Signaling Markers in 2/4-Mbyte/s System Interface Mode
2-Mbyte/s Interface Mode

Figure 14
4-Mbyte System Interface Mode
In the PCM 24 mode an additional possibility exists for using the FS/DL bits for signaling, e.g. for
CCS (see figure 14). For synchronizing this controller to the multiframe structurethe time-slot internal flagsthe signals RMFB and XMFB, andthe signals AFR and AFT (4-kHz DL clock)
may be used.

Figure 15
Connection to a Controller in FS/DL-Bit Application
c. Support for Direct Memory Access
Applications: CCS, CAS-CC, CAS-BR
After a DMA request, reading from and writing to the assigned stack must be done twice in the case
of PCM 30 mode and three times when PCM 24 mode is enabled.
Further handling of the signaling information is done automatically by the ACFA. In addition to the
signals for transfer control (RREQ, XREQ, ACKNLQ), the signals RMFB and XMFB may be used for
synchronization.
Acknowledging and clearing pending requests is done in one of the following ways:
XREQbit EMOD.EDMA = ‘0’: at the end of the first write access to stack XSIG (rising edge of
WRQ).
bit EMOD.EDMA = ‘1’: with the beginning of the second (PCM 30) or third (PCM 24) write
access to stack XSIG.XREQ is reset with the falling edge of ACKNLQ or CEQ and remains
reset if a write cycle to stack XSIG follows. Otherwise, it becomes active again until the
second or third access to stack XSIG is provided.
This stack is addressed by
1. address ‘A’ and write command (memory-to-memory DMA transfer)
PEB 2035
PEB 2035
RREQbit EMOD.EDMA = ‘0’: at the end of the first read access to stack RSIG (rising edge of
RDQ).
bit EMOD.EDMA = ‘1’: with the beginning of the second (PCM 30) or third (PCM 24) read
access to stack RSIG (falling edge of RDQ).
This stack is addressed by
1. address ‘7’ and a read command (memory-to-memory DMA transfer)
2. signal: ACKNLQ and read command (I/O-to-memory DMA transfer)
Both requests may be triggered at the same time. The sequence of service is determined by the
user.

Figure 16
Connection to a DMA Controller
d. Access via Microprocessor
In principle, the use of the microprocessor for signaling tasks is similar to memory-to-memory DMA
applications. The request signals RREQ and XREQ indicate the meaning of interrupt requests.
Additionally, in PCM 24 mode the possibility exists to use FS/DL bits for carrying signaling
information. In this case, the signals RMFB and XMFB are used as interrupt requests.
Acknowledging is done by programming the two interrupt acknowledge bits XFDL.RMAK and
XFDL.XMAK.
Figure 17
Connection to a Microprocessor for Signaling Applications
Interface to Testing Unit
XTOPOTransmit Test Data Out Plus
XTOMOTransmit Test Data Out Minus
PCM(+) and PCM(–) output signals which may be used for external
diagnostic loopback. The output sense is selectable via bit XC0.XTDS.
XRCLKOPCM 30: as above
RESQIReset
RCHPYOReceive Channel Parity
Even/odd parity signal assigned to time-slots on RDO (bit ACR.DLC has
to be reset). Its sense is programmed via bit RC0.RPYS.
XCHPYITransmit Channel Parity
Even/odd parity signal assigned to time-slots on XDI. This function is
enabled via bit XC0.EPY (bits ACR.DLC and ACR.EXMF have to be
reset). Its sense is programmed via bit XC0.EPYS.
DFPYOPCM 30: Doubleframe Parity
Even parity signal of the previously received doubleframe.
PEB 2035
PEB 2035
Interface to Microprocessor
D0-7I/OBidirectional data bus
A0-3IAddress bus
WRQIWrite enable
RDQIRead enable
CEQIChip enable
COSICarrier Out of Service
Initiates transmission of AIS via XDOP, XDOM, and XOID.
AINTOAlarm Interrupt
If enabled via bit CCR.AINT, this signal may be triggered by any one of
the 11 (PCM 30) or 9 (PCM 24) alarm sources configured via register
MASK, via bit XC1.MCA, and via bits XSP.MRMB and XSP.MXMB (PCM
30 mode only). Acknowledging is done by writing a ‘1’ to bit LOOP.AIA.
RREQOas above
XREQOas above
RMFBOPCM 24: as above
XMFBOPCM 24: as above
AFTIPCM 24: Additional Function Transmit
If bit ACR.EXMF is set, this input signal can be used to synchronize the
transmitter of the ACFA externally for multiframe begin.
Test Functions
There are three types of monitoring/testing functions:Passive tests which do not affect the normal operation of the device (e.g.: parity check)Active tests which partly degrade the functionality (e.g.: test loop for a single channel)Diagnostics, during which the device is not operational (e.g.: diagnostic loop of an entire trunk).
Alarm Simulation
Alarm simulation does not affect the normal operation of the device, i.e. all channels remain
available for transmission. However, possible ‘real’ alarm conditions are not reported to the
processor or to the remote end when the device is in the alarm simulation mode.
The alarm simulation is initiated by setting the bit CCR.SIM. The following alarms are simulated:No signalAlarm Indication Signal (AIS)Loss of pulse frameRemote alarm indicationReceive slip indicationTransmit slip indicationReceive parity error
Framing error counterCode violation counter (HDB3/B8ZS Codes)CRC4/6 error counterSome of the above indications are only simulated if the ACFA is configured in a mode where the
alarm is applicable (e.g. no CRC4 error simulation when doubleframe format is enabled).
Controlling the alarm simulation depends on the selected PCM mode:
PCM 30 Mode
Setting of the bit CCR.SIM initiates alarm simulation. Error counting and indication will occurs while
this bit is set. After it is reset all simulated error conditions disappear. Alarms like AIS and NOS are
cleared automatically. The indications of slips, parity errors and the error counters have to be
cleared by setting/resetting corresponding bits of register CCR (CCR.CLR, CCR.CCPY).
PCM 24 Mde
The alarm simulation is controlled by the value of the Alarm Simulation Counter: ASR.SC which is
incremented by setting bit: CCR.SIM. Contrary to PCM 30 mode, resetting this bit has no influence
on running alarm simulation.
Clearing of alarm indications:automatically for NOS, remote alarm, AIS, and loss of synchronization anduser controlled for slips, parity errors, and error counters via bit CCR.CLR
is only possible at defined counter steps of ASR.SC. For complete simulation (ASR.SC = 0), eight
simulation steps are necessary.
Speech Memory Supervision
During normal operation, the receive and transmit paths may be monitored to detect malfunctions
by using parity generation/checking and loopback of individual time-slots.
Parity Check
Both the receive and the transmit memories are supervised by a parity bit generation/checking
mechanism. A parity bit is generated at the input of the receive (resp. transmit) speech memory and
written to the memory along with the eight bit PCM data (in PCM 30 mode the transmit memory is
by-passed).
Parity is checked at the memory output and errors are reported via status bits:Receive Channel Parity Error: RSR.RPE (PCM 30), ASR.RPE (PCM 24) for the channel selected
via register CPY.Transmit Channel Parity Error: RSP.XPE (PCM 30), ASR.XPE (PCM 24) for the channel
selected via register CPY.Global Parity Error: RSP.GPE (PCM 30), MFR.GPE (PCM 24) for all transmit and receive
channels.
PEB 2035
PEB 2035
For the transmit path, the parity bit may optionally be input over pin XCHPY rather than being
generated internally (enabled via bit XC0.EPY; input sense selection via bit XC0.EPYS). This parity
bit should be fed in simultaneously with bit 8 (LSB) of the corresponding time-slot.
The use of the internal parity generator for the transmit path makes sense only for PCM 24 systems,
since for PCM 30 the transmit memory is not operational. An externally generated parity bit
(XCHPY) on the contrary, may provide means for monitoring system internal PCM paths for
malfunctions, both in PCM 30 and PCM 24 systems.
The parity bit generated at the input of the receive speech memory is output at port RCHPY
simultaneously with the corresponding time-slot. The output sense is selectable by bit RC0.RPYS.
Loopback of Time-Slots
Each of the 31 (24) channels may be selected for loopback from the system PCM input (XDI) to the
system PCM output (RDO). This loopback is programmed for one channel at a time selected by
register LOOP. In PCM 24 mode, it is possible to enable loop back of ‘pure’ channel data which is
input at port XDI, without signaling information supplied at port XSIG (bit LOOP.SLB). This function
is permitted in all signaling modes (CCS, CAS-CC and CAS-BR). During loopback, an idle channel
code programmed in register IDLE is transmitted to the remote end in the corresponding PCM route
channel.
For the channel test, sending sequences of test patterns like a 1-kHz check signal should be
avoided. Otherwise, an increased occurrence of slips in the tested channel will disturb testing.
These slips do not influence the other channels and the function of the receive memory. The usage
of a quasi-static test pattern is recommended.
Processor Interface Test
Testing the processor interface will not affect the normal operation of the device. The normally write
only control registers may be read in a test mode by setting bit CCR.CRD (except for all
acknowledge bits and the PCM 30 Sn-bit stack).
Diagnostic of Receive Speech Memory
The receive speech memory may be tested in the PCM 30 mode by an even parity bit generated
over a doubleframe. The doubleframe parity signal is output via pin DFPY.
Diagnostic Loopback
The test outputs XTOP and XTOM give a replica of the normal PCM route outputs and thus enable
monitoring of possible malfunctions of the transmission path, even during normal operation. A
diagnostic loopback of data may be implemented externally over XTOP and XTOM. During
diagnostics, transmission of AIS over XDOP and XDOM (XOID) should be initiated by setting port
COS to ‘1’ or setting bit MODE.XAIS to indicate that the PCM route is not available for normal use.In
applications with PEB 2235, PEB 2236, IPAT, as the line interface unit for the ACFA, diagnostic
loops to remote end and to system internal highway are performed without the need of any

Partno	Mfg	Dc	Qty	Available	Descript
PEB2035N V4.1 \|PEB2035NV41		N/a	25	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035N V4.1 \|PEB2035NV41	SIEMENS	N/a	25	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035NV4.1 \|PEB2035NV41	SIEMENS	N/a	7	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035NV4.1 \|PEB2035NV41	AMERICA	N/a	6284	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035NV4.1 \|PEB2035NV41	Infineon	N/a	33500	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035N-V4.1 \|PEB2035NV41	infineon	N/a	3	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035NV4.1 . \|PEB2035NV41	Infineon	N/a	370	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035PV4.1 \|PEB2035PV41	SIMENS	N/a	300	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035PV4.1 \|PEB2035PV41	INFNEON	N/a	47	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035PV4.1 \|PEB2035PV41	INFINEON	N/a	270	avai	ACFA (Advanced CMOS Frame Aligner)
PEB2035P-V4.1 \|PEB2035PV41	SIE	N/a	38	avai	ACFA (Advanced CMOS Frame Aligner)