PEB20324 ,ICs for Communicationscharacteristics.Terms of delivery and rights to change design reserved.Due to technical requirement ..
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PEB2035N V4.1 ,ACFA (Advanced CMOS Frame Aligner)applications, processes and circuits implemented within components or assemblies.The information de ..
PEB2035NV4.1 ,ACFA (Advanced CMOS Frame Aligner)Table of Contents Page1
PEB2035NV4.1 ,ACFA (Advanced CMOS Frame Aligner)applications, processes and circuits implemented within components or assemblies.The information de ..
PEB2035NV4.1 ,ACFA (Advanced CMOS Frame Aligner)Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
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PIC17C42A , High-Performance 8-Bit CMOS EPROM/ROM Microcontroller
PEB20324
ICs for Communications
ICs for Communications
Multichannel Network Interface Controller for HDLC + Extensions
MUNICH128X
PEB 20324 Version 2.2
For questions on technology, delivery and prices please contact the Infineon Technologies Offices
in Germany or the Infineon Technologies Companies and Representatives worldwide:
see our webpage at http://www.infineon.com
Edition 04.99
Published by Infineon Technologies AG i. Gr.,
SC,
Balanstraße 73,
81541 München© InfineonTechnologiesAG i.Gr. 1999.
All Rights Reserved.
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the express written approval of the InfineonTechnologiesAG.A critical component is a component used in a life-support device or system whose failure can reasonably be
PEB 20324
PEF 20324
PrefaceThe MUNICH128X is a 128-channel WAN Protocol Controller which provides four
independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA
Controller and a Serial PCM Interface Controller. The device is offered in a 160-
pinMQFP package, making it ideal for high-port-density applications.
Organization of this DocumentThis Hardware Reference Manual is divided into 7 chapters. It is organized as follows: Chapter 1, Introduction
Gives a general description of the product and its family, lists the key features, and
presents some typical applications.Chapter 2, Pin Description
Lists pin locations with associated signals, categorizes signals according to function,
and describes signals.Chapter 3, Functional IC Description
Gives a general functional overview of the MUNICH128X.Chapter 4, Electrical Characteristics
Gives a detailed description of all electrical DC and AC characteristics and provides
timing diagrams and values for all interfaces.Chapter 5, Test Modes
Gives a detailed description of the JTAG boundary scan interface.Chapter 6, Package Outline
Related DocumentationMUNICH128X Version 2.2
Prpgrammer’s Reference Manual 03.99 DS1
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Table of ContentsPagePreface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.2Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
1.3Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
1.4Differences to the MUNICH32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.1Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283.1Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.2Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
3.3Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
3.4System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4.1Operational Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .375.1Important Electrical Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
5.2Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
5.3Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
5.4DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
5.5Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
5.6AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
5.6.1PCI Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
5.6.1.1PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
5.6.1.2PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
5.6.1.3PCI Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
5.6.2De-multiplexed Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
5.6.3PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
5.6.4System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
5.6.5JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
6.1Boundary Scan Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
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List of FiguresPage
Figure 1-1Simplified Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 1-2Logic Symbol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 1-3System Integration of the MUNICH128X in PCI-Based System . . . . . .12
Figure 1-4System Integration of the MUNICH128X in De-multiplexed System . . .13
Figure 2-1Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 3-1Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 3-1System Integration of the MUNICH128X in PCI-Based System . . . . . .34
Figure 3-2System Integration of the MUNICH128X in De-multiplexed System . . .35
Figure 5-1Power-up and Power-down scenarios. . . . . . . . . . . . . . . . . . . . . . . . . .37
Figure 5-2Power-Failure scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Figure 5-1Input/Output Waveform for AC Tests. . . . . . . . . . . . . . . . . . . . . . . . . . .43
Figure 5-2PCI Output Timing Measurement Waveforms. . . . . . . . . . . . . . . . . . . .44
Figure 5-3PCI Input Timing Measurement Waveforms . . . . . . . . . . . . . . . . . . . . .44
Figure 5-4PCI Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Figure 5-5PCI Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Figure 5-6PCI Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Figure 5-7Master Single READ Transaction followed by a Master Single
WRITE Transaction in De-multiplexed Bus Configuration. . . . . . . . . . .51
Figure 5-8Master Burst WRITE/READ Access in De-multiplexed Bus
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Figure 5-9PCM Serial Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Figure 5-10System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 5-11JTAG-Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Figure 6-1Block Diagram of Test Access Port and Boundary Scan. . . . . . . . . . . .57
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List of TablesPage
Table 2-1Pin Descriptions by Functional Block: Port0 Serial Interface. . . . . . . 17
Table 2-2Pin Descriptions by Functional Block:Port1 Serial Interface . . . . . . . 18
Table 2-3Pin Descriptions by Functional Block:Port2 Serial Interface . . . . . . . 19
Table 2-4Pin Descriptions by Functional Block:Port3 Serial Interface . . . . . . . 20
Table 2-5Pin Descriptions by Functional Block: PCI Interface. . . . . . . . . . . . . . 21
Table 2-6Pin Descriptions by Functional Block:
DEMUX Interface (additional signals to PCI Interface) . . . . . . . . . . . . 25
Table 2-7Pin Descriptions by Functional Block:Power Supply. . . . . . . . . . . . . . 26
Table 2-8Pin Descriptions by Functional Block: Test Interface. . . . . . . . . . . . . . 27
Table 5-1Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5-2Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 5-3Non-PCI Interface Pins
TA = 0 to + 70×C; VDD5 = 5V ± 5%, VDD3 = 3.3V ± 0.3V,
VSS = 0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 5-4Non-PCI Interface Pins
TA = 25×C; VDD5 = 5V ± 5%, VDD3 = 3.3V ± 0.3V, VSS = 0V . . . 42
Table 5-5PCI Input and Output Measurement Conditions . . . . . . . . . . . . . . . . . 44
Table 5-6Number of Wait States Inserted by the MUNICH128X as Initiator. . . . 48
Table 5-7Number of Wait States Inserted by the MUNICH128X as Slave . . . . . 48
Table 5-8PCI Clock Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 5-9PCI Interface Signal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 5-10Additional De-multiplexed Interface Signal Characteristics . . . . . . . . . 52
Table 5-11PCM Serial Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 5-12System Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 5-13JTAG-Boundary Scan Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 6-1Boundary Scan Sequence in MUNICH128X . . . . . . . . . . . . . . . . . . . . 58
Table 6-2Boundary Scan Test Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
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IntroductionIntroduction
The MUNICH128X is a 128-channel WAN Protocol Controller which provides four
independent 24/32-channel HDLC controllers, each with a dedicated 64-channel DMA
Controller and a Serial PCM Interface Controller. The device is offered in a 160-
pinMQFP package, making it ideal for high-port-density applications.
The MUNICH128X provides capability for up to 128full duplex serial PCM channels. The
chip performs layer2 HDLC formatting/deformatting or V.110 or X.30 protocols up todata rate of 38.4kbit/s (V.110) or 64kbit/s (HDLC). The MUNICH128X also performs
transparent transmission for DMImodes0,1, and 2. Processed data is transferred to
host memory via the PCI interface or de-multiplexed bus interface.
The MUNICH128X is compatible with the LAPD ISDN (Integrated Services Digital
Network) protocol specified by CCITT, as well as with HDLC, SDLC, LAPB and DMI
protocols. It provides rate adaptation for time slot transmission from 64kbit/s down tokbit/s and the concatenation of time slots, supporting the ISDN H0, H11, H12
superchannels.
Figure 1-1Simplified Block Diagram
Multichannel Network Interface Controller for HDLC +
Extensions
MUNICH128X
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1.1Features
Four independent 24/32-channel HDLC PCM
Controllers with common PCI interface.
Each of them provides:Dedicated 1024byte Tx BufferDedicated 1024byte Rx BufferDedicated Serial PCM Interface ControllerT1 rates: 1.536, 1.544, 3.088, 6.176Mbit/sE1 rates: 2.048, 4.096, 8.192Mbit/sDedicated 64-channel DMA ControllerSupports linked-list buffer processing16-DWord Tx DMA FIFO16-DWord Rx DMA FIFO4-DWord burst of Rx descriptors3-DWord burst of Tx descriptorsn-DWord burst of configuration blocks
(n is unlimited according the MUNICH128X, but internal port arbitration may lead to
a lower typical burst size of 4 or 8DWords)Dynamic Programmable Channel AllocationCompatible with T1/DS1 24-channel and CEPT 32-channel PCM byte formatConcatenation of any, not necessarily consecutive, time slots to superchannels
independently for receive and transmit directionSupport of H0, H11, H12 ISDN-channelsSubchanneling on each time slot possible
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IntroductionBit Processor Functions (adjustable for each channel)HDLC ProtocolAutomatic flag detectionShared opening and closing flagDetection of interframe-time-fill change, generation of
interframe-time-fill ‘1’s or flagsZero bit insertion Flag stuffing and flag adjustment for rate adaptionCRC generation and checking (16 or 32 bits)Transparent CRC option per channel and/or per messageError detection (abort, long frame, CRC error, 2 categories
of short frames, non-octet frame content)ABORT/IDLE flag generationV.110/X.30 ProtocolAutomatic synchronization in receive direction, automatic generation of
the synchronization pattern in transmit directionE/S/X bits freely programmable in transmit direction, may be changed
during transmission; changes monitored and reported in receive directionGeneration/detection of loss of synchronismBit framing with network data rates from 600 bit/s up to 38.4 Kbit/sTransparent Mode ASlot synchronous transparent transmission/reception without frame structureFlag generation, flag stuffing, flag extraction, flag generation
in the abort case with programmable flagSynchronized data transfer for fractional T1/PRI channelsTransparent Mode BTransparent transmission/reception in frames delimited by 00H flagsShared opening and closing flagFlag stuffing, flag detection, flag generation in the abort caseError detection (non octet frame content, short frame, long frame)Transparent Mode RTransparent transmission/reception with GSM 08.60 frame structureAutomatic 0000H flag generation/detectionSupport of 40, 391/2, 401/2 octet framesError detection (non octet frame contents, short frame, long frame)Protocol IndependentChannel inversion (data, flags, IDLE code)Format conventions as in CCITT Q.921 § 2.8Data over- and underflow detected
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Introduction32Bit/33MHz PCI2.1Interface32Bit/33MHz De-multiplexed Bus Interface Option0.5μm, 3.3
V-Optimized Technology3.3V I/O Capability with 5.0V Input Tolerance160-pinMQFP Package
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Introduction
1.2Logic Symbol
•
Figure 1-2Logic Symbol
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Introduction
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Introduction
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Introduction
1.4Differences to the MUNICH32 128-channel capabilitySymmetrical Rx and Tx Buffer Descriptor formats for faster switchingImproved Tx idle channel polling process for significantly reducing bus occupancy of
idle Tx channelsDedicated 1024byte Tx BufferDedicated 1024byte Rx BufferBurst capability also on transmit and receive data sections (8 DWORDs)Additional PCM modes supported: 3.088MBit/s, 6.176MBit/s, 8.192MBit/s32Bit/33MHz PCI2.1 master/slave interface;
this interface can be configured in De-mux modeSeparate Rx and Tx Status Queues in host memory
(the MUNICH128X provides one set for each of the four HDLC Controllers)Slave access to on-chip registersTime Slot-shift capability:Programmable from -4 clock edges to +3 clock edges
relative to the synchronization pulseProgrammable to sample Tx and/or Rx data at either falling or rising edge of clockSoftware initiated action request (via the Command Register)Tx End-of-Packet transmitted-on-wire interrupt capability for each channelTx packet size increased to 64Kbytes (HDLC mode)Rx packet size 8Kbyte limit interrupt disableTx data TRISTATETM control lineSynchronized data transfer in TMA mode
for complete transparency when using fractional T1/PRILittle/Big Endian data formats
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Pin DescriptionsPin Descriptions
2.1Pin Diagram
(top view)
•
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Pin Descriptions
Pin descriptions in Tables 2-1 to 2-8 are grouped by functional block, as shown by the
heading for that group. Pin types are indicated by abbreviations:
Signal Type Definitions:
The following signal type definitions are partly taken from the PCI Specification
Revision2.1:Input is a standard input-only signal.Totem Pole Output is a standard active driver.
t/s, I/OTri-State or I/O is a bi-directional, tri-state input/output pin.
s/t/sSustained Tri-State is an active low tri-state signal owned and driven
by one and only one agent at a time. (For further information refer to
the PCI Specification Revision 2.1)
o/dOpen Drain allows multiple devices to share as a wire-OR. A pull-up
is required to sustain the inactive state until another agent drives it,
and must be provided by the central resource.
Signal Name Conventions:
Note:The signal type definition specifies the functional usage of a pin. This does not
reflect necessarily the implementation of a pin, e.g. a pin defined of signal type
‘Input’ may be implemented with a bidirectional pad.
Note:All unused input or I/O pins without internal Pull-Up/Down resistor must be
connected to a defined level either connected to VDD3 /VSS or to a Pull-Up/Down
resistor (<= 10k).Not Connected Pin
Such pins are not bonded with the silicon. Although any potential at
these pins will not impact the device it is recommended to leave them
unconnected. NC pins might be used for additional functionality in later
versions of the device. Leaving them unconnected will guarentee
hardware compatibility to later device versions.
ReservedReserved pins are for vendor specific use only and should be connected
as recommended to guarantee normal operation.
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Pin Descriptions
Table 2-1Pin Descriptions by Functional Block: Port0 Serial Interface
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Pin Descriptions
Table 2-2Pin Descriptions by Functional Block:Port1 Serial Interface
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Pin Descriptions
Table 2-3Pin Descriptions by Functional Block:Port2 Serial Interface
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Pin Descriptions
Table 2-4Pin Descriptions by Functional Block:Port3 Serial Interface
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Pin Descriptions
Table 2-5Pin Descriptions by Functional Block: PCI Interface
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Pin Descriptions
Table 2-5Pin Descriptions by Functional Block: PCI Interface (cont’d)
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Pin Descriptions
Table 2-5Pin Descriptions by Functional Block: PCI Interface (cont’d)
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Pin Descriptions
Table 2-5Pin Descriptions by Functional Block: PCI Interface (cont’d)
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Pin Descriptions
Table 2-6Pin Descriptions by Functional Block:
DEMUX Interface (additional signals to PCI Interface)
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Pin Descriptions
Table 2-7Pin Descriptions by Functional Block:Power Supply
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Pin Descriptions
Table 2-8Pin Descriptions by Functional Block: Test Interface
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Functional DescriptionFunctional Description
3.1Functional Overview
The MUNICH128X provides four independent “cores” as well as global functional blocks
(see Figure 3-1).
3.2Block Diagram
•
Figure 3-1Block Diagram
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Functional Description
3.3Functional Blocks
Each core consists of dedicated circuitry: Serial PCM Interface Controller, Configuration
and State RAM (CSR), 24/32-channel HDLC Controller with internal Transmit and
Receive Buffers, 64-Channel DMA Controller, and Register Set.
3.3.1Serial PCM Interface Controller
This block controls both Parallel–to-Serial (Tx) and Serial-to-Parallel (Rx) conversion
and PCM timing. Additionally, this block controls the multiplexing of channels through the
HDLC controller, as well as switching for the test loops.
3.3.2Configuration and State RAM (CSR)
This block contains internal RAM which maintains the state of each channel. The
Multiplex Control Block of the Serial PCM Interface Controller handles the switching of
the CSR information into and out of the 24/32-channel HDLC Controller.
3.3.324/32-channel HDLC Controller
The HDLC Controller performs protocol processing for each channel independently,
based on the CSR information for each channel.
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Functional Description
3.3.3.1Tx Block
Transmit Buffer (TB)
The Tx Block of the HDLC Controller contains a 1024byte buffer (TB) which may be
allocated to all 32channels of one cove equally (i.e., 2-DWords per channel) or may be
allocated based on superchannel considerations (e.g., 8–DWords per channel forchannels).
HDLC Protocol
Bit stuffing, flag generation, flag stuffing and adjustment, and CRC generation (either 16-
bit or 32-bit) are performed.
V.110 and V.30 Protocol
Bit framing from 600bit/s to 38.4Kbit/s, automatic generation of the synchronization
pattern, generation of loss of synchronization, programmable E/SX bits (including during
run-time) are performed.
Transparent Mode A
This mode supports slot synchronous, transparent transmission without frame structure.
It provides flag generation, flag stuffing, flag generation in the abort case with
programmable flag, and synchronized data transfer for fractional T1/E1 PRI applications.
Transparent Mode B
This mode supports transparent transmission in frames delimited by 00H flags, shared
closing and opening flag, flag stuffing and flag generation in the abort case.
Transparent Mode R
This mode supports transparent transmission with GSM08.60 frame structure with
automatic 0000H flag generation and support of 40, 39.5, and 40.5 octet frames.
Protocol Independence
Channel inversion (data, flags, idle code) follows the format conventions as in CCITT
Q.921.
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Functional Description
3.3.3.2Rx Block
Receive Buffer (RB)
The Rx Block of the HDLC Controller contains a 1024byte buffer (RB) which is allocated
to channels via requests from the protocol controller, as determined by the received data
for each channel.
HDLC Protocol
Flag detection (supports multiple flags between packets or a single flag shared as a
closing flag and an opening flag between packets), abort character detection, idle code
detection, zero-bit detection and deletion, packet length count, and CRC checking (either
16-bit or 32-bit) are performed.
V.110 and V.30 Protocol
Bit framing from 600bit/s to 38.4Kbit/s, automatic synchronization of the
synchronization pattern, detection of loss of synchronization, programmable E/SX bits
(including during run–time) are performed.
Transparent Mode A
Mode A supports slot synchronous transparent reception without frame structure. It
provides flag detection, flag extraction and synchronized data transfer for fractional T1/
E1 PRI applications.
Transparent Mode B
This mode supports transparent reception in frames delimited by 00H flags. Sharing
closing flag and opening flag, and flag detection.
Transparent Mode R
This mode supports transparent reception with GSM08.60 frame structure with
automatic 0000H flag detection. Support of 40, 39.5, and 40.5 octet frames, and error
detection (non–octet frame contents, short frame, long frame).
Protocol Independence
Channel inversion (data, flags, idle code) follows the format conventions as in CCITT
Q.921, data overflow and underflow detection.
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Functional Description
3.3.3.364-channel DMA Controller Block
This block controls memory address calculation, buffer management (including linked-
lists) and interrupt processing. The 24/32-channel HDLC Controller has a dedicated
DMA channel for each channel and direction. During run-time, the DMA Controller
performs operations with host memory primarily as a bus master. This block providesinput and 32output channels.
3.3.3.4Register Set
This block provides configuration and control of the Serial PCM Interface Controller, the
HDLC Controller and the DMA Controller. Also, a shared status register STAT provides
status and interrupt information associated with each of the four cores.
