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PDTA114ET Limiting values Table 6.
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PDTA113EU
PNP resistor-equipped transistors; R1 = 1 kOhm, R2 = 1 kOhm
Product profile1.1 General descriptionPNP Resistor-Equipped Transistors (RET).
[1] Also available in SOT54A and SOT54 variant packages (see Section2)
1.2 Features
1.3 Applications
1.4 Quick reference data
PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
Rev. 05 — 2 September 2009 Product data sheet
Table 1. Product overviewPDTA113EE SOT416 SC-75 - PDTC113EE
PDTA113EK SOT346 SC-59A TO-236 PDTC113EK
PDTA113EM SOT883 SC-101 - PDTC113EM
PDTA113ES[1] SOT54 (TO-92) SC-43A TO-92 PDTC113ES
PDTA113ET SOT23 - TO-236AB PDTC113ET
PDTA113EU SOT323 SC-70 - PDTC113EU Built-in bias resistors n Reduces component count Simplifies circuit design n Reduces pick and place costs General purpose switching and
amplification Circuit drivers Inverter and interface circuits
Table 2. Quick reference dataVCEO collector-emitter voltage open base - - −50 V output current (DC) - - −100 mA bias resistor 1 (input) 0.7 1 1.3 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ Pinning information
Table 3. Pinning
SOT54 input (base) output (collector) GND (emitter)
SOT54A input (base) output (collector) GND (emitter)
SOT54 variant input (base) output (collector) GND (emitter)
SOT23, SOT323, SOT346, SOT416 input (base) GND (emitter) output (collector)
SOT883 input (base) GND (emitter) output (collector)
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001aab348
006aaa148
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006aaa148
006aaa144
sym003
Transparent
top view
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NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ Ordering information[1] Also available in SOT54A and SOT54 variant packages (see Section 2 and Section9).
Marking[1] * = -: made in Hong Kong
* = p: made in Hong Kong
* = t: made in Malaysia
* = W: made in China
Table 4. Ordering informationPDTA113EE SC-75 plastic surface mounted package; 3 leads SOT416
PDTA113EK SC-59A plastic surface mounted package; 3 leads SOT346
PDTA113EM SC-101 leadless ultra small plastic package; 3 solder lands;
body 1.0 × 0.6 × 0.5 mm
SOT883
PDTA113ES[1] SC-43A plastic single-ended leaded (through hole) package; leads
SOT54
PDTA113ET - plastic surface mounted package; 3 leads SOT23
PDTA113EU SC-70 plastic surface mounted package; 3 leads SOT323
Table 5. Marking codesPDTA113EE 16
PDTA113EK 17
PDTA113EM G4
PDTA113ES TA113E
PDTA113ET *15
PDTA113EU *14
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ Limiting values[1] Refer to standard mounting conditions
[2] Reflow soldering is the only recommended soldering method.
[3] Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 μm copper strip line.
Thermal characteristics[1] Refer to standard mounting conditions.
[2] Reflow soldering is the only recommended soldering method.
[3] Refer to SOT883 standard mounting conditions; FR4 printed-circuit board with 60 μm copper strip line.
Table 6. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCBO collector-base voltage open emitter - −50 V
VCEO collector-emitter voltage open base - −50 V
VEBO emitter-base voltage open collector - −10 V input voltage
positive - +10 V
negative - −10 V output current (DC) - −100 mA
ICM peak collector current - −100 mA
Ptot total power dissipation Tamb ≤ 25°C
SOT416 [1]- 150 mW
SOT346 [1]- 250 mW
SOT883 [2][3]- 250 mW
SOT54 [1]- 500 mW
SOT23 [1]- 250 mW
SOT323 [1]- 200 mW
Tstg storage temperature −65 +150 °C junction temperature - 150 °C
Tamb ambient temperature −65 +150 °C
Table 7. Thermal characteristicsRth(j-a) thermal resistance from
junction to ambient
in free air
SOT416 [1]- - 833 K/W
SOT346 [1]- - 500 K/W
SOT883 [2][3]- - 500 K/W
SOT54 [1]- - 250 K/W
SOT23 [1]- - 500 K/W
SOT323 [1]- - 625 K/W
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ Characteristics
Table 8. CharacteristicsTamb = 25 °C unless otherwise specified
ICBO collector-base cut-off
current
VCB = −50 V; IE = 0 A - - −100 nA
ICEO collector-emitter
cut-off current
VCE = −30 V; IB = 0 A - - −1 μA
VCE = −30 V; IB = 0 A;= 150°C −50 μA
IEBO emitter-base cut-off
current
VEB = −5 V; IC = 0 A - - −4mA
hFE DC current gain VCE = −5 V; IC = −40 mA 30 - -
VCEsat collector-emitter
saturation voltage
IC = −30 mA; IB = −1.5 mA - - −150 mV
VI(off) off-state input voltage VCE = −5 V; IC = −100 μA- −1.3 −0.5 V
VI(on) on-state input voltage VCE = −300 mV; IC = −20 mA −2 −1.7 - V bias resistor 1 (input) 0.7 1 1.3 kΩ
R2/R1 bias resistor ratio 0.8 1 1.2 collector capacitance VCB = −10 V; IE = ie = 0 A;
f=1MHz
--2 pF
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ Package outline
Fig 5. Package outline SOT416 (SC-75)
Plastic surface-mounted package; 3 leads SOT416
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
Fig 6. Package outline SOT346 (SC-59A/TO-236)
Plastic surface-mounted package; 3 leads SOT346
NXP Semiconductors PDT A113E series
PNP resistor-equipped transistors; R1 = 1 kΩ, R2 = 1 kΩ
Leadless ultra small plastic package; 3 solder lands; body 1.0 x 0.6 x 0.5 mm SOT883
