PCKV857DGG ,70-190 MHz differential 1:10 clock driverPIN CONFIGURATION• ESD classification testing is done to JEDEC Standard JESD22.Protection exceeds 2 ..
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PCKV857-PCKV857DGG
70-190 MHz differential 1:10 clock driver
Product data
Supersedes data of 2001 Mar 16
File under Intergrated Circuits ICL03
2001 Jun 12
Philips Semiconductors Product data
PCKV85770–190 MHz differential 1:10 clock driver
FEATURES ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114. Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA Optimized for clock distribution in DDR (Double Data Rate)
SDRAM applications as per JEDEC specifications 1-to-10 differential clock distribution Very low skew (< 100 ps) and jitter (< 100 ps) Operation from 2.2 V to 2.7 V AVDD and 2.3 V to 2.7 V VDD SSTL_2 interface clock inputs and outputs CMOS control signal input Test mode enables buffers while disabling PLL Low current power-down mode Tolerant of Spread Spectrum input clock Full DDR solution provided when used with SSTL16877 or
SSTV16857 See PCKV856 for I2C capable clock driver
DESCRIPTIONThe PCKV857 is a high-performance, low-skew, low-jitter zero delay
buffer designed for 2.5 V VDD and 2.5 V AVDD operation and
differential data input and output levels.
The PCKV857 is a zero delay buffer that distributes a differential
clock input pair (CLK, CLK) to ten differential pairs of clock outputs
(Y[0:9], Y[0:9]) and one differential pair feedback clock outputs
(FBOUT, FBOUT) . The clock outputs are controlled by the clock
inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog
power input (AVDD). When PWRDWN is high, the outputs switch in
phase and frequency with CLK. When PWRDWN is low, all outputs
are disabled to high impedance state (3-State), and the PLL is shut
down (low power mode). The device also enters the low power
mode when the input frequency falls below 20 MHz. An input
frequency detection circuit will detect the low frequency condition
and after applying a > 20 MHz input signal, the detection circuit
turns on the PLL again and enables the outputs.
When AVDD is grounded, the PLL is turned off and bypassed for test
purposes. The PCKV857 is also able to track spread spectrum
clocking for reduced EMI.
The PCKV857 is characterized for operation from 0 to +70 °C.
PIN CONFIGURATION
ORDERING INFORMATION
Philips Semiconductors Product data
PCKV85770–190 MHz differential 1:10 clock driver
PIN DESCRIPTION
FUNCTION TABLE
NOTES:H = HIGH voltage level
L = LOW voltage level
Z = high impedance OFF-state
X = don’t care Subject to change. May cause conflict with FBIN pins. Additional feature that senses when the clock input is less than 20 MHz and places the part in sleep mode.
BLOCK DIAGRAM
Philips Semiconductors Product data
PCKV85770–190 MHz differential 1:10 clock driver
ABSOLUTE MAXIMUM RATINGS1
NOTES: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 3.6 V maximum.
RECOMMENDED OPERATING CONDITIONS1
NOTES: Unused inputs must be held high or low to prevent them from floating. DC input signal voltage specifies the allowable DC execution of differential input. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and
VCP is the complementary input level. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing.
Philips Semiconductors Product data
PCKV85770–190 MHz differential 1:10 clock driver
DC ELECTRICAL CHARACTERISTICSOver recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
NOTE: This is intended to operate in the SSTL_2 type IV unterminated mode without series resistors on the outputs. All typical values are at respective nominal VDDQ. Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing.
TIMING REQUIREMENTSOver recommended ranges of supply voltage and operating free-air temperature.
NOTE: Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power-up.
Philips Semiconductors Product data
PCKV85770–190 MHz differential 1:10 clock driver
AC CHARACTERISTICSGND = 0 V; tr = tf ≤ 2.5 ns; CL = 50 pF; RL = 1 kΩ
NOTE: Refers to transition of noninverting output.
