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PCK953BD
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
General descriptionThe PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high
performance clock tree designs. With output frequencies of up to 125 MHz, and output
skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The
devices employ a fully differential PLL design to minimize cycle-to-cycle and phase jitter.
The PCK953 has a differential LVPECL reference input, along with an external feedback
input. These features make the PCK953 ideal for use as a zero delay, low skew fan-out
buffer. The device performance has been tuned and optimizedfor zero delay performance.
The MR/OE input pin will reset the internal counters and 3-state the output buffers when
driven HIGH.
The PCK953is fully 3.3V compatible and requiresno external loop filter components.All
control inputs accept LVCMOS or LVTTL compatible levels, while the outputs provide
LVCMOS levels with the ability to drive terminated 50 Ω transmission lines. For series
terminated50Ω lines, eachof the PCK953 outputs can drive two traces, giving the device
an effective fan-out of 1: 18. The device is packaged in a 7 mm×7 mm 32-lead LQFP
package to provide the optimum combination of board density and performance.
Features Fully integrated PLL Output frequency up to 125 MHz in PLL mode Outputs disable in high-impedance LQFP32 packaging 55 ps cycle-to-cycle jitter typical9 mA quiescent current typical 60 ps static phase offset typical
PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL
clock driver
Rev. 05 — 9 October 2008 Product data sheet
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver Ordering informationAlso refer to Table 8 “Packing information”.
Functional diagram Pinning information
5.1 Pinning
Table 1. Ordering informationPCK953BD LQFP32 plastic low profile quad flat package; 32 leads; body 7×7× 1.4 mm SOT358-1
PCK953BD/G
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
5.2 Pin description Functional descriptionRefer to Figure 1 “Functional diagram”.
6.1 Function selection
Table 2. Pin descriptionVCCA 1 Analog supply voltage. See Section 11 “Application information” for
design and layout considerations.
FB_CLK 2 Feedback clock input (CMOS) to comparator/phase detector.
n.c. 3, 4, 5, 6 Not connected.
GNDI 7 Ground pin associated with input circuitry.
PECL_CLK 8 LVPECL reference clock input, true.
PECL_CLK 9 LVPECL reference clock input, complementary.
MR/OE 10 Master reset/output enable input. SeeT able 3 “Function selection”.
VCCO 11, 15,19,
23, 27
Supply voltage pins associated with output driver circuitry. 12 Buffered clock outputs (CMOS). 14 16 18 20 22 24 26
GNDO 13, 17,21,
25, 29
Ground pins associated with output driver circuitry.
QFB 28 Buffered clock output intended to be fed to feedback pin FB_CLK.
PLL_EN 30 PLL enable input pin. SeeT able 3 “Function selection”.
BYPASS 31 Bypass input pin. See Table 3 “Function selection”.
VCO_SEL 32 VCO select input pin. See Table 3 “Function selection”.
Table 3. Function selectionBYPASS 1 PLL enabled PLL bypass
MR/OE 1 outputs disabled outputs enabled
VCO_SEL 1 divide-by-2 divide-by-1
PLL_EN 1 select VCO select PECL_CLK
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver Limiting values Static characteristics[1] Vcm is the difference from the most positive side of the differential input signal. Normal operation is obtained when the HIGH input is
within the Vcm range and the input swing lies within the Vi(p-p) specification.
[2] The PCK953 outputs can drive series or parallel terminated 50 Ω (or 50 Ω to 0.5VCC) transmission lines on the incident edge (see
Section 11 “Application information”).
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VCC supply voltage −0.3 +4.6 V input voltage −0.3 VDD+ 0.3 V input current - ±20 mA
Tstg storage temperature −40 +125 °C
Table 5. Static characteristicsTamb =0 °C to 70 °C; VCC= 3.3V±5 %, unless specified otherwise.
VIH HIGH-level input voltage LVCMOS inputs 2.0 - 3.6 V
VIL LOW-level input voltage LVCMOS inputs - - 0.8 V
Vi(p-p) peak-to-peak input voltage PECL_CLK 300 - 1000 mV
Vcm common-mode voltage PECL_CLK [1] VCC− 1.5 - VCC− 0.6 mV
VOH HIGH-level output voltage IOH= −20 mA [2] 2.4 - - V
VOL LOW-level output voltage IOL =20mA [2]- - 0.5 V input current - - ±75 μA input capacitance - - 4 pF
CPD power dissipation capacitance per output - 25 - pF
ICC maximum quiescent supply current all VCC pins - 9 20 mA
ICCPLL maximum PLL supply current VCCA pin only - 9 20 mA
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver Dynamic characteristics
10. PLL input reference characteristics
Table 6. Dynamic characteristicsTamb =0 °C to 70 °C; VCC= 3.3V±5 %; unless specified otherwise.
tr(o) output rise time 0.8 V to 2.0V 0.30 0.55 0.8 ns
tf(o) output fall time 0.8 V to 2.0V 0.30 0.55 0.8 ns output duty cycle 45 50 55 %
tsk(o) output skew time output-to-output; relative to QFB - - 100 ps
fVCO PLL VCO lock range 120 - 500 MHz
fo(max) maximum output frequency PLL mode; VCO_SEL=1 20 - 100 MHz
PLL mode; VCO_SEL=0 35 - 125 MHz
Bypass mode - - 225 MHz
tpd(lock) input to EXT_FB delay (with
PLL locked)
fref =50MHz −75 - +125 ps
tpd(bypass) input to Qn delay PLL bypassed 3 5.2 7 ns
tPLZ-HZ output disable time - - 7 ns
tPZL output enable time - - 6 ns
tjit(cc) cycle-to-cycle jitter time peak-to-peak - 55 100 ps
tlock maximum PLL lock time - 0.01 10 ms
Table 7. PLL input reference characteristicsTamb =0 °C to 70°C.
Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
fref reference input frequency 20 - 125 MHz
frefDC reference input duty cycle 25 - 75 %
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
11. Application information
11.1 Power supply filteringThe PCK953 is a mixed analog/digital product and as such it exhibits some sensitivities
that would not necessarily be seen on a fully digital product. Analog circuitry is naturally
susceptibleto random noise, especiallyif this noiseis seenon the power supply pins. The
PCK953 provides separate power supplies for the output buffers (VCCO) and the
phase-locked loop (VCCA) of the device. The purpose of this design technique is to try to
isolate the high switching noise digital outputs from the relatively sensitive internal analog
phase-locked loop. In a controlled environment such as an evaluation board, this level of
isolationis sufficient. However,ina digital system environment whereitis more difficultto
minimize noise on the power supplies, a second level of isolation may be required. The
simplest form of isolation is a power supply filter on the VCCA pin for the PCK953.
Figure 3 illustrates a typical power supply filter scheme. The PCK953 is most susceptible
to noise with spectral content in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs to be met in the final filter
design is the DC voltage drop that will be seen between the VCC supply and the VCCA pin
of the PCK953. The current sourced though the VCCA pin is typically 15 mA (20 mA
maximum), assuming that a minimum of 3.0 V must be maintained on the VCCA pin,
very little DC voltage drop canbe tolerated whena 3.3V VCC supplyis used. The resistor
shown in Figure 3 must have a resistance of 10 Ω to 15 Ω to meet the voltage drop
criteria. The RC filter pictured will provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above 20 kHz. As the noise frequency
crosses the series resonant point of an individual capacitor, its overall impedance begins
to look inductive, and thus increases with increasing frequency. The parallel capacitor
combination shown ensures that a low impedance path to ground exists for frequencies
well above the bandwidthof the PLL.Itis recommended that the user start withan8Ωto Ω resistor to avoid potential VCC drop problems, and only move to the higher value
resistors when a higher level of attenuation is shown to be needed.
Although the PCK953 has several design features to minimize the susceptibility to power
supply noise (isolated power and grounds and fully differential PLL) there still may be
applications in which overall performance is being degraded due to system power supply
noise. The power supply filter schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver
11.2 Driving transmission linesThe PCK953 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user, the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of less than 20 Ω, the drivers can drive either parallel or series terminated
transmission lines.
In most high performance clock networks, point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series terminated or parallel
terminated transmission lines canbe used. The parallel technique terminates the signalat
the end of the line with a 50 Ω resistance to 0.5VCC. This technique draws a fairly high
levelof DC current, and thus onlya single terminated line canbe drivenby each outputof
the PCK953 clock driver. For the series terminated case, however, thereisno DC current
draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an
output drivinga single series terminated line versus two series terminated linesin parallel.
When taken to its extreme, the fan-out of the PCK953 clock driver is effectively doubled
due to its capability to drive multiple lines.
The waveform plots of Figure 5 show the simulation results of an output driving a single
line versus two lines. In both cases, the drive capability of the PCK953 output buffers is
more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the
delay measurements in the simulations, a delta of only 43 ps exists between the two
differently loaded outputs. This suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of the PCK953. The output
waveformin Figure5 showsa stepin the waveform; this stepis causedby the impedance
mismatch seen looking into the driver. The parallel combinationof the43Ω series resistor
plus the output impedance does not match the parallel combination of the line
impedances. The voltage wave launched down the two lines will equal:
(1) =50 Ω||50Ω =36 Ω||36Ω =14ΩL VSos Ro Zo++------------------------------=
NXP Semiconductors PCK953
20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL clock driver(2)
At the load end, the voltage will double due to the near unity reflection coefficient, to
2.62V . It will then increment towards the quiescent 3.0 V in steps separated by one
round-trip delay (in this case, 4.0 ns).
Since this step is well above the threshold region, it will not cause any false clock
triggering, however, designers may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving multiple lines, the situation in Figure6
should be used. In this case, the series terminating resistors are reduced such that when
the parallel combination is added to the output buffer impedance, the line impedance is
perfectly matched.
SPICE level output buffer models are available for engineers who want to simulate their
specific interconnect schemes. In addition, IV characteristics are in the process of being
generated to support the other board-level simulators in general use.L 3.0 25 14 25++------------------------------ 3.0 25------ 1.31V== =
