PCF8591T ,PCF8591; 8-bit A/D and D/A converterLIMITING VALUES10 HANDLING11 DC CHARACTERISTICS12 D/A CHARACTERISTICS13 A/D CHARACTERISTICS14 AC CH ..
PCF8591T/2 ,PCF8591; 8-bit A/D and D/A converterGENERAL DESCRIPTION2• Sampling rate given by I C-bus speedThe PCF8591 is a single-chip, single-supp ..
PCF8591T-2 ,PCF8591; 8-bit A/D and D/A converterLIMITING VALUES10 HANDLING11 DC CHARACTERISTICS12 D/A CHARACTERISTICS13 A/D CHARACTERISTICS14 AC CH ..
PCF8593P ,Low power clock/calendarFUNCTIONAL DESCRIPTION15 PACKAGE OUTLINES7.1 Counter function modes7.2 Alarm function modes16 SOLDE ..
PCF8593T ,Low power clock/calendarINTEGRATED CIRCUITSDATA SHEETPCF8593Low power clock/calendar1997 Mar 25Product specificationSupersed ..
PCF8593T/1 ,PCF8593; Low power clock/calendar
PHB9NQ20T ,N-channel TrenchMOS(TM) transistorELECTRICAL CHARACTERISTICST= 25˚C unless otherwise specifiedjSYMBOL PARAMETER CONDITIONS MIN. TYP. ..
PHC20512 ,Complementary enhancement mode MOS transistors
PHC21025 ,Complementary enhancement mode MOS transistorsDISCRETE SEMICONDUCTORSDATA SHEETPHC21025Complementary enhancementmode MOS transistors1997 Jun 20Pr ..
PHC2300 ,Complementary enhancement mode MOS transistorsAPPLICATIONS3s source 22• Universal line interface in telephone sets 4g gate 22• Relay, high-speed ..
PHC2300 ,Complementary enhancement mode MOS transistorsFEATURES PINNING - SOT96-1 (SO8)• High-speed switchingPIN SYMBOL DESCRIPTION• No secondary breakdow ..
PHC2300 ,Complementary enhancement mode MOS transistorsDISCRETE SEMICONDUCTORSDATA SHEETM3D315PHC2300Complementary enhancementmode MOS transistorsProduct ..
PCF8591P-PCF8591T-PCF8591T/2-PCF8591T-2
PCF8591; 8-bit A/D and D/A converter
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
CONTENTS FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 Addressing
7.2 Control byte
7.3 D/A conversion
7.4 A/D conversion
7.5 Reference voltage
7.6 Oscillator CHARACTERISTICS OF THE I2 C-BUS
8.1 Bit transfer
8.2 Start and stop conditions
8.3 System configuration
8.4 Acknowledge
8.5 I2 C-bus protocol LIMITING VALUES HANDLING DC CHARACTERISTICS D/A CHARACTERISTICS A/D CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION PACKAGE OUTLINES SOLDERING
17.1 Introduction to soldering through-hole mount
packages
17.2 Soldering by dipping or by solder wave
17.3 Manual soldering
17.4 Suitability of through-hole mount IC packages
for dipping and wave soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
FEATURES Single power supply Operating supply voltage 2.5Vto6V Low standby current Serial input/output via I2C-bus Address by 3 hardware address pins Sampling rate given by I2 C-bus speed 4 analog inputs programmable as single-ended or
differential inputs Auto-incremented channel selection Analog voltage range from VSS to VDD On-chip track and hold circuit 8-bit successive approximation A/D conversion Multiplying DAC with one analog output.
APPLICATIONS Closed loop control systems Low power converter for remote data acquisition Battery operated equipment Acquisition of analog values in automotive, audio and
TV applications.
GENERAL DESCRIPTIONThe PCF8591 is a single-chip, single-supply low power
8-bit CMOS data acquisition device with four analog
inputs, one analog output and a serial I2 C-bus interface.
Three address pins A0, A1 and A2 are used for
programming the hardware address, allowing the use of
up to eight devices connected to the I2 C-bus without
additionalhardware. Address, controland datato and from
the device are transferred serially via the two-line
bidirectional I2 C-bus.
The functions of the device include analog input
multiplexing, on-chip track and hold function, 8-bit
analog-to-digital conversion and an 8-bit digital-to-analog
conversion. The maximum conversion rateis givenby the
maximum speed of the I2 C-bus.
ORDERING INFORMATION
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
BLOCK DIAGRAM PINNING
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591 FUNCTIONAL DESCRIPTION
7.1 Addressing
Each PCF8591deviceinan I2C-bussystemis activatedby
sending a valid address to the device. The address
consists of a fixed part and a programmable part. The
programmable part must be set according to the address
pins A0,A1 and A2. The address always hastobe sentas
the first byte after the start condition in the I2C-bus
protocol. The last bit of the address byte is the
read/write-bit which sets the directionof the following data
transfer (see Figs 4, 16 and 17).
7.2 Control byte
The second byte senttoa PCF8591 device willbe stored
in its control register and is required to control the device
function. The upper nibbleof the control registeris usedfor
enabling the analog output, and for programming the
analog inputs as single-ended or differential inputs. The
lower nibble selects one of the analog input channels
defined by the upper nibble (see Fig.5). If the
auto-increment flag is set, the channel number is
incremented automatically after each A/D conversion.
If the auto-increment mode is desired in applications
where the internal oscillator is used, the analog output
enable flag in the control byte (bit 6) should be set. This
allows the internal oscillator to run continuously, thereby
preventing conversion errors resulting from oscillator
start-up delay. The analog output enableflag maybe reset
at other times to reduce quiescent power consumption.
The selectionofa non-existing input channel resultsin the
highest available channel number being allocated.
Therefore, if the auto-increment flag is set, the next
selected channel will be always channel 0. The most
significant bits of both nibbles are reserved for future
functions and have to be set to logic 0. After a Power-on
reset condition all bits of the control register are reset to
logic 0. The D/A converter and the oscillator are disabled
for power saving. The analog output is switched to a
high-impedance state.
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
7.3 D/A conversion
The third byte sent to a PCF8591 device is stored in the
DAC data register and is converted to the corresponding
analog voltage using the on-chip D/A converter. This D/A
converter consistsofa resistor divider chain connectedto
the external reference voltage with 256 taps and selection
switches. The tap-decoder switches one of these taps to
the DAC output line (see Fig.6).
The analog output voltage is buffered by an auto-zeroed
unity gain amplifier. This buffer amplifier maybe switched
on or off by setting the analog output enable flag of the
control register. In the active state the output voltage is
held until a further data byte is sent.
The on-chip D/A converter is also used for successive
approximation A/D conversion. In order to release the
DACforan A/D conversion cycle the unity gain amplifieris
equipped witha track and hold circuit.This circuit holds the
output voltage while executing the A/D conversion.
The output voltage suppliedto the analog output AOUTis
given by the formula shown in Fig.7. The waveforms of a
D/A conversion sequence are shown in Fig.8.
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
7.4 A/D conversion
The A/D converter makes use of the successive
approximation conversion technique. The on-chip D/A
converter and a high-gain comparator are used
temporarily during an A/D conversion cycle. A/D conversion cycleis always started after sendinga
valid read mode address to a PCF8591 device. The A/D
conversion cycle is triggered at the trailing edge of the
acknowledge clock pulse and is executed while
transmitting the result of the previous conversion (see
Fig.9).
Once a conversion cycle is triggered an input voltage
sampleof the selected channelis storedon the chip andis
convertedto the corresponding 8-bit binarycode.Samples
pickedup from differential inputs are convertedtoan 8-bit
twos complement code (see Figs 10 and 11).
The conversion result is stored in the ADC data register
and awaits transmission. If the auto-increment flag is set
the next channel is selected.
The first byte transmitted in a read cycle contains the
conversion result code of the previous read cycle. After a
Power-on reset condition the first byte read is a
hexadecimal 80. The protocol of an I2 C-bus read cycle is
shown in Chapter 8, Figs 16 and 17.
The maximum A/D conversion rate is given by the actual
speed of the I2 C-bus.
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
7.5 Reference voltage
For the D/A and A/D conversion either a stable external
voltage reference or the supply voltage has to be applied
to the resistor divider chain (pins VREF and AGND).
The AGND pin hastobe connectedto the system analog
ground and may have a DC off-set with reference to VSS.
A low frequency may be applied to the VREF and AGND
pins. This allows the use of the D/A converter as a
one-quadrant multiplier; see Chapter 15 and Fig.7.
The A/D converter may also be used as a one or two
quadrant analog divider. The analog input voltage is
dividedby the reference voltage. The resultis convertedto binary code.In this application the user hasto keep the
reference voltage stable during the conversion cycle.
7.6 Oscillator
An on-chip oscillator generates the clock signal required
for the A/D conversion cycle and for refreshing the
auto-zeroed buffer amplifier. When using this oscillator the
EXT pin has to be connected to VSS. At the OSC pin the
oscillator frequency is available.
If the EXT pin is connected to VDD the oscillator output
OSC is switched to a high-impedance state allowing the
user to feed an external clock signal to OSC.
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591 CHARACTERISTICS OF THE I2 C-BUS
TheI2 C-busisfor bidirectional, two-line communication between different ICsor modules. The two lines area serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data
transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One databitis transferred during each clock pulse. The dataon the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal.
8.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the
clockis HIGH,is definedas the start condition (S).A LOW-to-HIGH transitionof the data line while the clockis HIGH,is
defined as the stop condition (P).
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
8.3 System configuration device generatinga messageisa ‘transmitter’,a device receivinga messageis the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’.
8.4 Acknowledge
The number of data bytes transferred between the start and stop conditions from transmitter to receiver is not limited.
Each data byteof eight bitsis followedby one acknowledge bit. The acknowledgebitisa HIGH level puton the busby
the transmitter whereas the master also generatesan extra acknowledge related clock pulse.A slave receiver whichis
addressed must generate an acknowledge after the reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW
during the HIGH period of the acknowledge related clock pulse. A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Philips Semiconductors Product specification
8-bit A/D and D/A converter PCF8591
8.5 I2 C-bus protocol
After a start condition a valid hardware address has to be sent to a PCF8591 device. The read/write bit defines the
directionof the following singleor multiple byte data transfer. For the format and the timingof the start condition (S), the
stop condition (P) and the acknowledge bit (A) refer to the I2 C-bus characteristics. In the write mode a data transfer is
terminated by sending either a stop condition or the start condition of the next data transfer.
