PCF8582C-2T ,256 x 8-bit CMOS EEPROM with I2C-bus interfaceFeatures■ Low power CMOS:◆ 2.0 mA maximum operating current◆ maximum standby current 10 μA (at 6.0 ..
PCF8582C-2T ,256 x 8-bit CMOS EEPROM with I2C-bus interfaceBLOCK DIAGRAM15.1 Introduction7 PINNING15.2 DIP7.1 Pin description PCF8582C-215.2.1 Soldering by di ..
PCF8582C-2T ,256 x 8-bit CMOS EEPROM with I2C-bus interfaceFEATURES211 I C-BUS CHARACTERISTICS2
PCF8582C-2T ,256 x 8-bit CMOS EEPROM with I2C-bus interfaceBLOCK DIAGRAM15.1 Introduction7 PINNING15.2 DIP7.1 Pin description PCF8582C-215.2.1 Soldering by di ..
PCF8582C2-T ,256 x 8-bit CMOS EEPROM with I2C-bus interfaceFEATURES • High reliability by using a redundant storage code• Endurance: 1000000 Erase/Write (E/W) ..
PCF8582E-2 ,256 x 8-bit CMOS EEPROMS with I2C-bus interfaceINTEGRATED CIRCUITSDATA SHEETPCX8582X-2 Family256 x 8-bit CMOS EEPROMS2with I C-bus interfaceProduc ..
PHB45NQ10T ,N-channel TrenchMOS(tm) transistor
PHB45NQ10T ,N-channel TrenchMOS(tm) transistor
PHB45NQ15T ,N-channel TrenchMOS(tm) standard level FET
PHB45NQ15T ,N-channel TrenchMOS(tm) standard level FET
PHB47NQ10T ,N-channel enhancement mode field-effect transistor
PHB47NQ10T ,N-channel enhancement mode field-effect transistorPHP47NQ10T; PHB47NQ10TN-channel enhancement mode field-effect transistorRev. 01 — 16 May 2001 Produc ..
PCF8582C-2T
256 x 8-bit CMOS EEPROM with I2C-bus interface
PCF8582C-2256 × 8-bit CMOS EEPROM with I2 C-bus interface
Rev. 04 — 25 October 2004 Product data DescriptionThe PCF8582C-2 is a floating gate Electrically Erasable Programmable Read Only
Memory (EEPROM) with 2 kbits (256× 8-bit) non-volatile storage. By using an
internal redundant storage code, it is fault tolerant to single bit errors. This feature
dramatically increases the reliability compared to conventional EEPROMs. Power
consumptionis low dueto the full CMOS technology used. The programming voltage
is generated on-chip, using a voltage multiplier.
Data bytes are received and transmitted via the serial I2 C-bus. Up to eight
PCF8582C-2 devices may be connected to the I2 C-bus. Chip select is accomplished
by three address inputs (A0, A1 and A2).
Timing of the E/W cycle is carried out internally, thus no external components are
required. Programming Time Control (PTC), Pin 7, must be connected to either VDD
or left open-circuit. There is an option of using an external clock for timing the length
of an E/W cycle.
Features Low power CMOS: 2.0 mA maximum operating current maximum standby current 10 μA (at 6.0 V), typical 4 μA Non-volatile storage of 2 kbits organized as 256× 8-bit Single supply with full operation down to 2.5V On-chip voltage multiplier Serial input/output I2 C-bus Write operations: byte write mode 8-byte page write mode (minimizes total write time per byte) Read operations: sequential read random read Internal timer for writing (no external components) Internal power-on reset0 kHz to 100 kHz clock frequency High reliability by using a redundant storage code Endurance: 1,000,000 Erase/Write (E/W) cycles at Tamb =22°C 10 years non-volatile data retention time
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I
2 C-bus interface Pin and address compatible to: PCF8570, PCF8571, PCF8572, PCA8581 and
PCF85102 Pin compatible with a different address to PCF85103 ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Offered in DIP8 and SO8 packages.
Quick reference data Ordering information
4.1 Ordering options
Table 1: Quick reference dataVDD supply voltage 2.5 - 6.0 V
IDDR supply current read fSCL= 100 kHz
VDD= 2.5V - - 60 μA
VDD =6V - - 200 μA
IDDW supply current E/W fSCL= 100 kHz
VDD= 2.5V - - 0.6 mA
VDD=6V - - 2.0 mA
IDD(stb) standby supply current VDD= 2.5V - - 3.5 μA
VDD =6V - - 10 μA
Table 2: Ordering informationPCF8582C-2P/03 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8582C-2T/03 SO8 plastic small outline package 8 leads (straight);
body width 3.9 mm
SOT96-1
Table 3: Ordering optionsPCF8582C-2P/03 PCF8582C-2
PCF8582C-2T/03 8582C-2
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I
2 C-bus interface Block diagram
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface Pinning information
6.1 Pinning
6.2 Pin description Device addressing
[1] The Most Significant Bit (MSB) ‘b7’ is sent first.
A2, A1, A0 are hardware selectable pins.
A system could have up to eight PCF8582C-2 devices on the same I2 C-bus,
equivalent to a 16 kbit EEPROM or 8 pages of 256 bytes of memory.
The eight addresses are defined by the state of the A0, A1, A2 inputs (logic level ‘1’
when connected to VDD, logic level ‘0’ when connected to GND). Figure 3 shows the
various address combinations.
Table 4: Pin description 1 address input 0 2 address input 1 3 address input 2
VSS 4 negative supply voltage
SDA 5 serial data input/output (I2 C-bus)
SCL 6 serial clock input (I2 C-bus)
PTC 7 programming time control output
VDD 8 positive supply voltage
Table 5: Device address code
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I
2 C-bus interface
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface Functional description
8.1I2 C-bus protocol
TheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The
serial bus consists of two bidirectional lines; one for data signals (SDA), and one for
clock signals (SCL).
Both the SDA and SCL lines must be connected to a positive supply voltage via a
pull-up resistor.
The following protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is
HIGH. Changes in the data line while the clock line is HIGH will be interpreted as
control signals.
8.1.1 Bus conditions
The following bus conditions have been defined:
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — A change in the state of the data line, from HIGH-to-LOW,
while the clock is HIGH, defines the ST ART condition.
Stop data transfer — A change in the state of the data line, from LOW-to-HIGH,
while the clock is HIGH, defines the STOP condition.
Data valid — The state of the data line represents valid data when, after a START
condition, the data line is stable for the duration of the HIGH period of the clock
signal. There is one clock pulse per bit of data.
8.1.2 Data transfer
Each data transfer is initiated with a START condition and terminated with a STOP
condition. The number of the data bytes, transferred between the START and STOP
conditions is limited to 7 bytes in the E/W mode and 8 bytes in the Page E/W mode.
Data transfer is unlimited in the read mode. The information is transmitted in bytes
and each receiver acknowledges with a ninth bit.
Within theI2 C-bus specifications,a standard-speed mode (100 kHz clock rate) anda
fast speed mode (400 kHz clock rate) are defined. The PCF8582C-2 operatesin only
the standard-speed mode.
By definition, a device that sends a signal is called a ‘transmitter’, and the device
which receives the signalis calleda ‘receiver’. The device which controls the signalis
called the ‘master’. The devices that are controlled by the master are called ‘slaves’.
Each byte is followed by one acknowledge bit. This acknowledge bit is a HIGH level,
puton the busby the transmitter. The master generatesan extra acknowledge related
clock pulse. The slave receiver which is addressed is obliged to generate an
acknowledge after the reception of each byte.
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges hasto pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
endof datato the slave transmitterby not generatingan acknowledgeon the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3 Device addressing
Following a ST ART condition, the bus master must output the address of the slave it
is accessing. The address of the PCF8582C-2 is shown in Figure 4. To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either VDD or VSS.
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
8.1.4 Write operations
Byte/word write: Fora write operation, the PCF8582C-2 requiresa second address
field. This address field is a word address providing access to the 256 words of
memory. Upon receipt of the word address, the PCF8582C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I2 C-bus.
Fig 4. Slave address.
002aaa173
FIXED HARDWARE
SELECTABLE
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface
Page write: The PCF8582C-2 is capable of an eight-byte page write operation. It is
initiatedin the same manneras the byte write operation. The master can transit eight
data bytes within one transmission. After receipt of each byte, the PCF8582C-2 will
respond with an acknowledge. The typical E/W time in this mode is× 3.5 ms= 31.5 ms. Erasing a block of 8 bytes in page mode takes typical 3.5 ms
and sequential writing of these 8 bytes another typical 28 ms.
After the receipt of each data byte, the three low-order bits of the word address are
internally incremented. The high-order five bits of the address remain unchanged.
The slave acknowledges the reception of each data byte with an ACK. The I2 C-bus
data transfer is terminated by the master after the 8th byte with a STOP condition. If
the master transmits more than eight bytes prior to generating the STOP condition,
no acknowledge will be given on the ninth (and following) data bytes and the whole
transmission will be ignored and no programming will be done. As in the byte write
operation, all inputs are disabled until completion of the internal write cycles.
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface
8.1.5 Read operations
Read operations are initiated in the same manner as write operations with the
exception that the LSB of the slave address is set to logic1.
There are three basic read operations: current address read, random read, and
sequential read.
Remark: The lower 8 bits of the word address are incremented after each
transmission of a data byte (read or write). The MSB of the word address, which is
definedin the slave address,is not changed when the word address count overflows.
Thus, the word address overflows from 255 to 0, and from 511 to 256.
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface Limiting values
10. Characteristics
Table 6: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.3 +6.5 V input voltage on any input pin |Zi|> 500Ω VSS− 0.8 +6.5 V input current on any input pin - 1 mA output current - 10 mA
Tstg storage temperature −65 +150 °C
Tamb operating ambient temperature −40 +85 °C
Table 7: Characteristics
VDD= 2.5to 6.0 V; VSS =0V; Tamb= −40 to +85 °C; unless otherwise specified.
Supplies
VDD supply voltage 2.5 - 6.0 V
IDDR supply current read fSCL= 100 kHz
VDD= 2.5V - - 60 μA
VDD= 6.0V - - 200 μA
IDDW supply current E/W fSCL= 100 kHz
VDD= 2.5V - - 0.6 mA
VDD= 6.0V - - 2.0 mA
IDD(stb) standby supply current VDD= 2.5V - - 3.5 μA
VDD= 6.0 V - - 10 μA
PTC output (pin 7)
VIL LOW level input voltage −0.8 - 0.1VDD V
VIH HIGH level input voltage 0.9VDD -VDD+ 0.8 V
SCL input (pin 6)
VIL LOW level input voltage −0.8 - 0.3VDD V
VIH HIGH level input voltage 0.7VDD - +6.5 V
ILI input leakage current VI =VDDor VSS -- ±1 μA
fSCL clock input frequency 0 - 100 kHz input capacitance VI =VSS --7 pF
Philips Semiconductors PCF8582C-2
256 × 8-bit CMOS EEPROM with I2 C-bus interface
11.I2 C-bus characteristics
[1] The hold time required (not greater than 300ns)to bridgethe undefined regionofthe falling edgeof SCL mustbe internally providedby
a transmitter.
SDA input/output (pin 5)
VIL LOW level input voltage −0.8 - 0.3VDD V
VIH HIGH level input voltage 0.7VDD - +6.5 V
VOL LOW level output voltage IOL=3 mA; VDD(min) - - 0.4 V
ILO output leakage current VOH =VDD --1 μA input capacitance VI =VSS --7 pF
Data retention time data retention time Tamb =55 °C10 −− years
Table 7: Characteristics…continued
VDD= 2.5to 6.0 V; VSS =0V; Tamb= −40 to +85 °C; unless otherwise specified.
Table 8: I2C-bus characteristics
All of the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH
with an input voltage swing from VSS to VDD; see Figure9.
fSCL clock frequency 0 100 kHz
tBUF bus free time between a STOP and
START condition
4.7 −μs
tHD;STA START condition hold time after
which first clock pulse is generated
4.0 −μs
tLOW LOW level clock period 4.7 −μs
tHIGH HIGH level clock period 4.0 −μs
tSU;STA set-up time for START condition repeated start 4.7 −μs
tHD;DAT data hold time
for bus compatible masters 5 −μs
for bus devices [1] 0 − ns
tSU;DAT data set-up time 250 − ns SDA and SCL rise time − 1 μs SDA and SCL fall time − 300 ns
tSU;STO set-up time for STOP condition 4.0 −μs
