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PCF8579T
LCD column driver for dot matrix graphic displays
General descriptionThe PCF8579 is a low power CMOS1 LCD column driver, designed to drive dot matrix
graphic displays at multiplex rates of 1:8, 1:16, 1:24 or 1:32. The device has 40 outputs
and can drive 32× 40 dots in a 32 row multiplexed LCD. Up to 16 PCF8579s can be
cascaded and up to 32 devices may be used on the same I2 C-bus (using the two slave
addresses). The device is optimized for use with the PCF8578 LCD row/column driver.
Together these devices forma general purpose LCD dot matrix driver chip set, capableof
driving displays of up to 40960 dots. The PCF8579 is compatible with most
microcontrollers and communicates via a two-line bidirectional bus (I2 C-bus). To allow
partial VDD shutdown the ESD protection systemof the SCL and SDA pins does not usea
diode connected to VDD. Communication overhead is minimized by a display RAM with
auto-incremented addressing and display bank switching.
Features LCD column driver Used in conjunction with the PCF8578, this device forms part of a chip set capable of
driving up to 40960 dots 40 column outputs Selectable multiplex rates; 1:8, 1:16, 1:24 or 1:32 Externally selectable bias configuration, 5 or 6 levels Easily cascadable for large applications (up to 32 devices) 1280-bit RAM for display data storage Display memory bank switching Auto-incremented data loading across hardware subaddress boundaries (with
PCF8578) Power-On Reset (POR) blanks display Logic voltage supply range 2.5Vto6V Maximum LCD supply voltage 9V Low power consumptionI2 C-bus interface Compatible with most microcontrollers Optimized pinning for single plane wiring in multiple device applications (with
PCF8578) Space saving 56-lead small outline package and 64-pin quad flat pack
PCF8579
LCD column driver for dot matrix graphic displays
Rev. 05 — 11 May 2009 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section15.
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays Applications Automotive information systems Telecommunication systems Point-of-sale terminals Industrial computer terminals Instrumentation
Ordering information[1] Should not be used for new designs.
Marking
Table 1. Ordering informationPCF8579T/1 VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8579H/1 LQFP64 plastic low profile quad flat package; 64 leads;
body 10×10× 1.4 mm[1] SOT314-2
PCF8579HT/1 TQFP64 plastic thin quad flat package; 64 leads;
body10×10× 1.0 mm
SOT357-1
Table 2. Marking codesPCF8579T/1 PCF8579T
PCF8579H/1 PCF8579H
PCF8579HT/1 PCF8579HT
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays Block diagram
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays Pinning information
7.1 Pinning
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
7.2 Pin description[1] The TEST pin must be connected to VSS.
[2] Do not connect, these pins are reserved.
Functional descriptionThe PCF8579 column driver is designed for use with the PCF8578. Together they form a
general purpose LCD dot matrix chip set.
Typicallyupto16 PCF8579s maybe used with one PCF8578 (examplesof cascading the
devices see Table 16, Figure 21, Figure 22, Figure 23 and Figure 24). Each of the
PCF8579s is identified by a unique 4-bit hardware subaddress, set by pins A0 to A3.
The PCF8578 can operate with up to 32 PCF8579s when using two I2 C-bus slave
addresses. The two slave addresses are set by the logic level on input SA0.
8.1 Power-on resetAt power-on the PCF8579 resets to a defined starting condition as follows: Display blank (in conjunction with PCF8578) 1:32 multiplex rate Start bank 0 selected Data pointer is set to X, Y address0,0 Character mode Subaddress counter is set to 0I2 C-bus interface is initialized
Table 3. Pin descriptionSDA 1 7 I2 C-bus serial data input/output
SCL 2 8 I2 C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
VSS 5 11 ground
TEST[1] 6 12 test pin
SA0 7 13 I2 C-bus slave address input (bit0)
A3 to A0 8 to 11 14, 16 to 18 I2 C-bus subaddress inputs
VDD 12 20 supply voltage
n.c.[2] 13 15, 19,21,25
to 29, 34
not connected
V3, V4 14, 15 22, 23 LCD bias voltage inputs
VLCD 16 24 LCD supply voltage
C39 to C0 17to56 30 to 33, 35
to 64, 1 to 6
LCD column driver outputs
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
Remark: Do not transfer data on the I2 C-bus for at least 1 ms after power-on to allow the
reset action to complete.
8.2 Multiplexed LCD bias generationThe bias levels required to produce maximum contrast depend on the multiplex rate and
the LCD threshold voltage (Vth). Vth is typically defined as the RMS voltage at which the
LCD exhibits 10 % contrast.T able 4 shows the optimum voltage bias levels and Table5
the discrimination ratios (D) for the different multiplex rates as functions of Voper.
(1)
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
(2)
and the RMS off-state voltage (Voff(RMS)) with the equation
(3)
where the values for n are determined by the multiplex rate (1:n). Valid values for n are:= 8 for 1:8 multiplex= 16 for 1:16 multiplex= 24 for 1:24 multiplex= 32 for 1:32 multiplex
Table 4. Optimum LCD voltages0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150 oper VDD V LCD–=on RMS()Voper=off RMS()Voper=2 oper--------------3 oper--------------4 oper--------------5 oper--------------
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displaysFigure 5 shows the values of Table 4 as graphs.
Table 5. Discrimination ratios0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.190off RMS() oper-------------------------on RMS() oper----------------------- operth--------------
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
8.3 LCD drive mode waveforms
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
8.4 Timing generatorThe timing generatorof the PCF8579 organizes the internal data flow from the RAMto the
display drivers. An external synchronization pulse SYNC is received from the PCF8578.
This signal maintains the correct timing relationship between cascaded devices.
8.5 Column driversOutputs C0to C39 are column drivers which must be connected to the LCD. Unused
outputs should be left open-circuit.
8.6 Characteristics of the I2 C-busTheI2 C-busisfor bidirectional, two-line communication between different ICsor modules.
The two lines are a Serial Data Line (SDA) and a Serial Clock Line (SCL) which must be
connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
8.6.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this
moment will be interpreted as control signals.
8.6.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH, is defined as the START condition (S). LOW-to-HIGH transitionof the data line while the clockis HIGH,is definedas the STOP
condition (P).
8.6.3 System configurationA device transmitting a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message flow is the master and the devices which
are controlled by the master are the slaves.
8.6.4 AcknowledgeThe number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generatesan extra acknowledge related clock pulse.A slave receiver
which is addressed must generate an acknowledge after the reception of each byte. Also
a master must generate an acknowledge after the reception of each byte that has been
clocked out of the slave transmitter. The device that acknowledges must pull down the
SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during
the HIGH period of the acknowledge related clock pulse (set-up and hold times must be
taken into consideration).A master receiver must signal the endofa data transmissionto
the transmitter by
not generating an acknowledge on the last byte that has been clockedout of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition.
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
8.6.5I2 C-bus controllerTheI2 C-bus controller detects theI2 C-bus protocol, slave address, commands and display
data bytes. It performs the conversion of the data input (serial-to-parallel) and the data
output (parallel-to-serial). The PCF8579 acts as an I2 C-bus slave transmitter/receiver.
Device selection depends on the I2 C-bus slave address, the hardware subaddress and
the commands transmitted.
8.6.6 Input filtersTo enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
8.6.7I2 C-bus protocolTwo 7-bit slave addresses (0111100 and 0111101) are reserved for both the PCF8578
and PCF8579. The least significantbitof the slave addressis setby connecting input SA0 either logic0 (VSS)or logic1 (VDD). Therefore, two typesof PCF8578or PCF8579 can
be distinguished on the same I2 C-bus which allows: One PCF8578to operate withupto32 PCF8579son the sameI2 C-busfor very large
applications (seeT able 16). The use of two types of LCD multiplex schemes on the same I2 C-bus.
In most applications the PCF8578 will have the same slave address as the PCF8579.
TheI2 C-bus protocolis shownin Figure 13.All communications are initiated witha START
condition (S) from theI2 C-bus master, whichis followedby the desired slave address and
read/write bit.All devices with this slave address acknowledgein parallel.All other devices
ignore the bus transfer.
In WRITE mode (indicated by setting the read/write bit LOW) one or more commands
follow the slave address acknowledgement. The commands are also acknowledgedbyall
addressed devices on the bus. The last command must clear the continuation bitC.
After the last command a series of data bytes may follow. The acknowledgement after
each byteis made onlyby the (A0, A1, A2 and A3) addressed PCF8579or PCF8578 with
its implicit subaddress 0. After the last data byte has been acknowledged, the I2 C-bus
master issues a STOP condition (P). READ mode, indicatedby setting the read/writebit HIGH, data bytes maybe read from
the RAM following the slave address acknowledgement. After this acknowledgement the
master transmitter becomes a master receiver and the PCF8579 becomes a slave
transmitter. The master receiver must acknowledge the receptionof each bytein turn. The
master receiver must signal an end of data to the slave transmitter, by not generating an
acknowledge on the last byte clocked out of the slave. The slave transmitter then leaves
the data line HIGH, enabling the master to generate a STOP condition (P).
Display bytes are written into, or read from the RAM at the address specified by the data
pointer and subaddress counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be transferred either to, or from
the intended devices.
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays multiple device applications, the hardware subaddress pinsof the PCF8579s (A0to A3)
are connectedto VSSor VDDto represent the desired hardware subaddress code.If twoor
more devices share the same slave address, then each device
must be allocated aunique hardware subaddress.
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
8.7 Display RAMThe PCF8579 contains a 32× 40-bit static RAM which stores the display data. The RAM
is divided into 4 banks of 40 bytes(4×8×40 bits). During RAM access, data is
transferred to or from the RAM via the I2 C-bus.
8.7.1 Data pointerThe addressing mechanism for the display RAM is realized using the data pointer. This
allowsan individual data byteora seriesof data bytestobe written into,or read from, the
display RAM, controlled by commands sent on the I2 C-bus.
8.7.2 Subaddress counterThe storage and retrieval of display data is dependent on the content of the subaddress
counter. Storage and retrieval take place only when the contents of the subaddress
counter matches with the hardware subaddress at pins A0, A1, A2 and A3.
8.8 Command decoderThe command decoder identifies command bytes that arrive on the I2 C-bus.
The five commands available to the PCF8579 are defined in Table6.
The most-significant bit of a command is the continuation bit C (see Table 7 and
Figure 14). Commands are transferred in WRITE mode only.
Table 6. Definition of PCF8579 commands
Table 7. C bit description C continue bit last control byte in the transfer; next byte will be regarded
as display data control bytes continue; next byte will be a command too
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays[1] Useful for scrolling, pseudo-motion and background preparation of new display content.
[1] Values shown in decimal.
Table 8. Set-mode - command bit description C 0, 1 see Table7
6, 5 - 10 fixed value T display mode PCF8578 row only PCF8578 mixed mode
3, 2 E[1:0] display status blank normal all segments on inverse video
1, 0 M[1:0] LCD drive mode 1:8 MUX (8 rows) 1:16 MUX (16 rows) 1:24 MUX (24 rows) 1:32 MUX (32 rows)
Table 9. Set-start-bank - command bit description C 0, 1 see Table7
6 to 2 - 11111 fixed value
1, 0 B[1:0] start bank pointer (see Figure 18)[1] bank 0 bank 1 bank 2 bank 3
Table 10. Device-select - command bit description C 0, 1 see Table7
6 to 4 - 110 fixed value
3 to 0 A[3:0] 0 to 15[1] hardware subaddress;
4 bit binary value; transferred to the subaddress
counter to define oneof sixteen hardware
subaddresses
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays[1] See operation code for set-start-bank in Table9.
[2] Values shown in decimal.
[1] Values shown in decimal.
Table 11. RAM-access - command bit description C 0, 1 see Table7
6 to 4 - 111 fixed value
3, 2 G[1:0] RAM access mode;
defines the auto-increment behavior of the
address for RAM access (see Figure 17) character half-graphic full-graphic not allowed[1]
1, 0 Y[1:0] 0 to 3[2] RAM row address;
two bits of immediate data, transferred to the
Y-address pointer to define one of four display
RAM rows (see Figure 15)
Table 12. Load-X-address - command bit description C 0, 1 see Table7 - 0 fixed value
5 to 0 X[5:0] 0 to 39[1] RAM column address;
six bits of immediate data, transferred to the
X-address pointer to define one of forty display
RAM columns (see Figure 15)
NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
8.9 RAM accessThere are three RAM-access modes:
Character
Half-graphic
Full-graphic
These modes are specified by the bits G[1:0] of the RAM-access command. The
RAM-access command controls the orderin which datais writtentoor read from the RAM
(see Figure 17).
To store RAM data, the user specifies the location into which the first byte will be loaded
(see Figure 16):
Device subaddress (specified by the device-select command)
RAM X-address (specified by the bits X[5:0] of the load-X-address command)
RAM bank (specified by the bits Y[1:0] of the RAM-access command)
Subsequent data bytes willbe writtenor read accordingto the chosen RAM-access mode.
Device subaddresses are automatically incremented between devices until the last device reached.If the last device has subaddress 15, further display data transfers will leadto
a wrap-around of the subaddress to0.
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NXP Semiconductors PCF8579
LCD column driver for dot matrix graphic displays
