PCF8578H ,LCD row/column driver for dot matrix graphic displaysLIMITING VALUES11 HANDLING12 DC CHARACTERISTICS13 AC CHARACTERISTICS14 APPLICATION INFORMATION15 CH ..
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PCF8578H
LCD row/column driver for dot matrix graphic displays
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
CONTENTS FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
7.1 Mixed mode
7.2 Row mode
7.3 Multiplexed LCD bias generation
7.4 Power-on reset
7.5 Internal clock
7.6 External clock
7.7 Timing generator
7.8 Row/column drivers
7.9 Display mode controller
7.10 Display RAM
7.11 Data pointer
7.12 Subaddress counter
7.13 I2 C-bus controller
7.14 Input filters
7.15 RAM access
7.16 Display control
7.17 TEST pin
8I2C-BUS PROTOCOL
8.1 Command decoder CHARACTERISTICS OF THE I2 C-BUS
9.1 Bit transfer
9.2 Start and stop conditions
9.3 System configuration
9.4 Acknowledge LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD
LOCATIONS CHIP-ON GLASS INFORMATION PACKAGE OUTLINE SOLDERING
18.1 Introduction
18.2 Reflow soldering
18.3 Wave soldering
18.3.1 LQFP
18.3.2 VSO
18.3.3 Method (LQFP and VSO)
18.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
FEATURES Single chip LCD controller/driver Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible) 40 driver outputs, configurable as 32⁄8, 24⁄16, 16⁄24 or⁄32 rows/columns Selectable multiplex rates; 1: 8, 1: 16, 1: 24 or 1:32 Externally selectable bias configuration, 5 or 6 levels 1280-bit RAM for display data storage and scratch pad Display memory bank switching Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579) Provides display synchronization for PCF8579 On-chip oscillator, requires only 1 external resistor Power-on reset blanks display Logic voltage supply range 2.5to6V Maximum LCD supply voltage 9V Low power consumptionI2 C-bus interface TTL/CMOS compatible Compatible with most microcontrollers Optimized pinning for single plane wiring in multiple
device applications (with PCF8579) Space saving 56-lead plastic mini-pack and 64 pin quad
flat pack Compatible with chip-on-glass technology.
APPLICATIONS Automotive information systems Telecommunication systems Point-of-sale terminals Computer terminals Instrumentation.
GENERAL DESCRIPTIONThe PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1: 8, 1: 16, 1: 24 or 1: 32. The device
has 40 outputs, of which 24 are programmable,
configurable as 32⁄8,24⁄16,16 ⁄24 or8⁄32 rows/columns.
The PCF8578 can function as a stand-alone LCD
controller/driver for use in small systems, or for larger
systems can be used in conjunction with up to PCF8579s for which it has been optimized. Together
these two devices form a general purpose LCD dot matrix
driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
microcontrollers and communicates via a two-line
bidirectional bus (I2C-bus). Communication overheads are
minimized by a display RAM with auto-incremented
addressing and display bank switching.
ORDERING INFORMATION
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
BLOCK DIAGRAM
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
PINNING
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578 FUNCTIONAL DESCRIPTION
The PCF8578 row/column driver is designed for use in one
of three ways: Stand-alone row/column driver for small displays
(mixed mode) Row/column driver with cascaded PCF8579s
(mixed mode) Row driver with cascaded PCF8579s (mixed mode).
7.1 Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications, or for larger displays with up to 15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
7.2 Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
connected between OSC and VSS.
Commands sent on the I2 C-bus from the host
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579 also have subaddresses. The subaddress of the
PCF8578 is only defined in mixed mode and is fixed at0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
Table 1 Possible displays configurations
Notes Using 15 PCF8579s. Using 16 PCF8579s.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
7.3 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of Vop (Vop =VDD− VLCD), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for Vop is obtained by equating Voff(rms) with Vth. Figure4
shows the first 4 rows of Table 2 as graphs. Table 3 shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2 Optimum LCD voltages
Table 3 Multiplex rates and resistor values for Fig.5
7.4 Power-on reset
At power-on the PCF8578 resets to a defined starting
condition as follows: Display blank1: 32 multiplex rate, row mode Start bank, 0 selected Data pointer is set to X, Y address0,0 Character mode Subaddress counter is set to 0I2 C-bus interface is initialized.
Data transfers on the I2 C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
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Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
7.5 Internal clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor ROSC, see Fig.9.
For normal use a value of 330 kΩ is recommended.
The clock signal, for cascaded PCF8579s, is output at CLK
and has a frequency1 ⁄6 (multiplex rate 1: 8, 1: 16 and: 32) or1 ⁄8 (multiplex rate 1: 24) of the oscillator
frequency.
7.6 External clock
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table4
summarizes the nominal CLK and SYNC frequencies.
7.7 Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8 Row/column drivers
Outputs R0to R7 and C32to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmable outputs (R8/C8to R31/C31) are defined as
row drivers and the outputs C32to C39 should be left
open-circuit.
Using a 1: 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16, R1 and R17/C17 etc. Similarly, using a multiplex
rate of 1: 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.1: 8 R0to R7 are rows; in 1: 16 R0to R15/C15 are
rows; in 1: 24 R0to R23/C23 are rows; in 1:32to R31/C31 are rows.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note1.
Notes A clock signal must always be present, otherwise the LCD may be frozen in a DC state. ROSC= 330 kΩ.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
7.9 Display mode controller
The configuration of the outputs (row or column) and the
selection of the appropriate driver waveforms are
controlled by the display mode controller.
7.10 Display RAM
The PCF8578 contains a 32x 40-bit static RAM which
stores the display data. The RAM is divided into 4 banks40 bytes(4x8x40 bits). During RAM access, data is
transferred to/from the RAM via the I2 C-bus. The first
eight columns of data (0to 7) cannot be displayed but
are available for general data storage and provide
compatibility with the PCF8579. There is a direct
correspondence between X-address and column output
number.
7.11 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
data byte or a series of data bytes to be written into, or read
from, the display RAM, controlled by commands sent on
the I2 C-bus.
7.12 Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes
place only when the contents of the subaddress counter
agree with the hardware subaddress. The hardware
subaddress of the PCF8578, valid in mixed mode only, is
fixed at 0000.
7.13I2 C-bus controller
The I2 C-bus controller detects the I2 C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8578 acts as an2 C-bus slave transmitter/receiver in mixed mode, and as
a slave receiver in row mode. A slave device cannot
control bus communication.
7.14 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.15 RAM access
RAM operations are only possible when the PCF8578 is mixed mode.
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
used in conjunction with the PCF8578 must start at 0001.
There are three RAM ACCESS modes: Character Half-graphic Full-graphic.
These modes are specified by bits G1to G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.10).
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.11): Device subaddress (specified by the DEVICE SELECT
command) RAM X-address (specified by the LOAD X-ADDRESS
command) RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subsequent data bytes will be written or read according to
the chosen RAM ACCESS mode. Device subaddresses
are automatically incremented between devices until the
last device is reached. If the last device has
subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to0.
7.16 Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits and B0 of the SET START BANK command. This is
shown in Fig.12. This feature is useful when scrolling in
alphanumeric applications.
7.17 TEST pin
The TEST pin must be connected to VSS.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
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Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
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Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
8I2C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
input SA0 to either 0 (VSS) or 1 (VDD). Therefore, two types
of PCF8578 or PCF8579 can be distinguished on the
same I2 C-bus which allows: One PCF8578 to operate with up to 32 PCF8579s on
the same I2 C-bus for very large applications The use of two types of LCD multiplex schemes on the
same I2 C-bus.
In most applications the PCF8578 will have the same slave
address as the PCF8579.
The I2 C-bus protocol is shown in Fig.13.
All communications are initiated with a start condition (S)
from the I2 C-bus master, which is followed by the desired
slave address and read/write bit. All devices with this slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bitC.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has been acknowledged, the I2C-bus master issues a stop
condition (P).
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowledgement. After this
acknowledgement the master transmitter becomes a
master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop condition
(P).
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter. Both the data pointer and subaddress counter are
automatically incremented, enabling a stream of data to be
transferred either to, or from, the intended devices.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
8.1 Command decoder
The command decoder identifies command bytes that
arrive on the I2 C-bus. The most-significant bit of a
command is the continuation bit C (see Fig.14). When this
bit is set, it indicates that the next byte to be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
The five commands available to the PCF8578 are defined
in Tables5 and6.
Table 5 Summary of commands
Note C= command continuation bit. D= may be a logic1or0.
Philips Semiconductors Product specification
LCD row/column driver for dot matrix
graphic displays PCF8578
Table 6 Definition of PCF8578/PCF8579 commands
