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PCF8577CP-PCF8577CT
LCD direct/duplex driver with I2C-bus interface
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
6.1 Hardware subaddress A0, A1, A2
6.2 Oscillator A0/OSC
6.3 User-accessible registers
6.4 Auto-incremented loading
6.5 Direct drive mode
6.6 Duplex mode
6.7 Power-on reset
6.8 Slave address
6.9 I2 C-bus protocol
6.10 Display memory mapping CHARACTERISTICS OF THE I2C-BUS
7.1 Bit transfer
7.2 Start and stop conditions
7.3 System configuration
7.4 Acknowledge LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS APPLICATION INFORMATION CHIP DIMENSIONS AND BONDING PAD
LOCATIONS PACKAGE OUTLINES SOLDERING
15.1 Plastic dual in-line packages
15.1.1 By dip or wave
15.1.2 Repairing soldered joints
15.2 Plastic small outline packages
15.2.1 By wave
15.2.2 By solder paste reflow
15.2.3 Repairing soldered joints (by hand-held
soldering iron or pulse-heated solder tool) DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
FEATURES Direct/duplex drive modes with up to
32/64 LCD-segment drive capability per device Operating supply voltage: 2.5to6V Low power consumptionI2 C-bus interface Optimized pinning for single plane wiring Single-pin built-in oscillator Auto-incremented loading across device subaddress
boundaries Display memory switching in direct drive mode May be used as I2 C-bus output expander System expansion up to 256 segments Power-on reset blanks displayI2 C-bus address: 0111 0100.
GENERAL DESCRIPTIONThe PCF8577C is a single chip, silicon gate CMOS circuit.
It is designed to drive liquid crystal displays with up to segments directly, or 64 segments in a duplex
configuration.
The two-line I2 C-bus interface substantially reduces wiring
overheads in remote display applications. I2 C-bus traffic is
minimized in multiple IC applications by automatic address
incrementing, hardware subaddressing and display
memory switching (direct drive mode).To allow partial VDD
shutdown the ESD protection system of the SCL and SDA
pins does not use a diode connected to VDD.
ORDERING INFORMATION BLOCK DIAGRAM
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
PINNING
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C FUNCTIONAL DESCRIPTION
6.1 Hardware subaddress A0, A1, A2
The hardware subaddress lines A0, A1 and A2 are used to
program the device subaddress for each PCF8577C
connected to the I2 C-bus. Lines A0 and A2 are shared with
OSC and BP2 respectively to reduce pin-out
requirements. Line A0 is defined as LOW (logic 0) when this pin is
used for the local oscillator or when connected to VSS.
Line A0 is defined as HIGH (logic 1) when connected
to VDD. Line A1 must be defined as LOW (logic 0) or as HIGH
(logic 1) by connection to VSS or VDD respectively. In the direct drive mode the second backplane signal
BP2 is not used and the A2/BP2 pin is exclusively the
A2 input. Line A2 is defined as LOW (logic 0) when
connected to VSS or, if this is not possible, by leaving
it unconnected (internal pull-down). Line A2 is defined
as HIGH (logic 1) when connected to VDD. In the duplex drive mode the second backplane signal
BP2 is required and the A2 signal is undefined. In this
mode device selection is made exclusively from
lines A0 and A1.
6.2 Oscillator A0/OSC
The PCF8577C has a single-pin built-in oscillator which
provides the modulation for the LCD segment driver
outputs. One external resistor and one external capacitor
are connected to the A0/OSC pin to form the oscillator (see
Figs15 and 16). For correct start-up of the oscillator after
power on, the resistor and capacitor must be connected to
the same VSS/VDD as the chip. In an expanded system
containing more than one PCF8577C the backplane
signals are usually common to all devices and only one
oscillator is required. The devices which are not used for
the oscillator are put into the cascade mode by connecting
the A0/OSC pin to either VDD or VSS depending on the
required state for A0. In the cascade mode each
PCF8577C is synchronized from the backplane signal(s).
6.3 User-accessible registers
There are nine user-accessible 1-byte registers. The first
is a control register which is used to control the loading of
data into the segment byte registers and to select display
options. The other eight are segment byte registers, split
into two banks of storage, which store the segment data.
The set of even numbered segment byte registers is called
BANK A. Odd numbered segment byte registers are called
BANKB.
There is one slave address for the PCF8577C (see Fig.6).
All addressed devices load the second byte into the control
register and each device maintains an identical copy of the
control byte in the control register at all times (see I2 C-bus
protocol, Fig.7), i.e. all addressed devices respond to
control commands sent on the I2 C-bus.
The control register is shown in more detail in Fig.3.
The least-significant bits select which device and which
segment byte register is loaded next. This part of the
register is therefore called the Segment Byte Vector
(SBV).
The upper three bits of the SBV (V5to V3) are compared
with the hardware subaddress input signals A2, A1
and A0. If they are the same then the device is enabled for
loading, if not the device ignores incoming data but
remains active.
The three least-significant bits of the SBV (V2to V0)
address one of the segment byte registers within the
enabled chip for loading segment data.
The control register also has two display control bits.
These bits are named MODE and BANK. The MODE bit
selects whether the display outputs are configured for
direct or duplex drive displays. The BANK bit allows the
user to display BANK A or BANKB.
6.4 Auto-incremented loading
After each segment byte is loaded the SBV is incremented
automatically. Thus auto-incremented loading occurs if
more than one segment byte is received in a data transfer.
Since the SBV addresses both device and segment
registers in all addressed chips, auto-incremented loading
may proceed across device boundaries provided that the
hardware subaddresses are arranged contiguously.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
6.5 Direct drive mode
The PCF8577C is set to the direct drive mode by loading
the MODE control bit with logic 0. In this mode only four
bytes are required to store the data for the 32 segment
drivers. Setting the BANK bit to logic 0 selects even bytes
(BANK A), setting the BANK bit to logic 1 selects odd bytes
(BANK B).
In the direct drive mode the SBV is auto-incremented by
two after the loading of each segment byte register. This
means that auto-incremented loading of BANK A or
BANK B is possible. Either bank may be completely or
partially loaded irrespective of which bank is being
displayed. Direct drive output waveforms are shown in
Fig.4.
6.6 Duplex mode
The PCF8577C is set to the duplex mode by loading the
MODE bit with logic 1. In this mode a second backplane
signal (BP2) is needed and pin A2/BP2 is used for this;
therefore A2 and its equivalent SBV bit V5 are undefined.
The SBV auto-increments by one between loaded bytes.
All of the segment bytes are required to store data for the segment drivers and the BANK bit is ignored.
Duplex mode output waveforms are shown in Fig.5.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
6.7 Power-on reset
At power-on reset the PCF8577C resets to a defined
starting condition as follows: Both backplane outputs are set to VSS in master mode;
to 3-state in cascade mode All segment outputs are set to VSS The segment byte registers and control register are
cleared The I2 C-bus interface is initialized.
6.8 Slave address
The PCF8577C slave address is shown in Fig.6.
Before any data is transmitted on the I2 C-bus, the device
which should respond is addressed first. The addressing is
always done with the first byte transmitted after the start
procedure.
6.9 I2C-bus protocol
The PCF8577C I2 C-bus protocol is shown in Fig.7.
The PCF8577C is a slave receiver and has a fixed slave
address (see Fig.6). All PCF8577Cs with the same slave
address acknowledge the slave address in parallel.
The second byte is always the control byte and is loaded
into the control register of each PCF8577C connected to
the I2 C-bus. All addressed devices acknowledge the
control byte. Subsequent data bytes are loaded into the
segment registers of the selected device. Any number of
data bytes may be loaded in one transfer and in an
expanded system rollover of the SBV from 111 111 to
000 000 is allowed. If a stop (P) condition is given after the
control byte acknowledge the segment data will remain
unchanged. This allows the BANK bit to be toggled without
changing the segment register contents. During loading of
segment data only the selected PCF8577C gives an
acknowledge. Loading is terminated by generating a stop
(P) condition.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
6.10 Display memory mapping
The mapping between the eight segment registers and the segment outputs S1to S32 is given in Tables1 and2.
Since only one register bit per segment is needed in the direct drive mode, the BANK bit allows swapping of display
information. If BANK is set to logic 0 even bytes (BANK A) are displayed; if BANK is set to logic 1 odd bytes (BANKB)
are displayed. BP1 is always used for the backplane output in the direct drive mode. In duplex mode even bytes
(BANK A) correspond to backplane 1 (BP1) and odd bytes (BANK B) correspond to backplane 2 (BP2).
Table 1 Segment byte-segment driver mapping in direct drive mode
Mapping example: bit 0 of register 7 controls the LCD segment S25 if BANK bit is a logic1.
Table 2 Segment byte-segment driver mapping in duplex mode
Note Where X= don’t care.
Mapping example: bit 7 of register 5 controls the LCD segment S24/BP2.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C CHARACTERISTICS OF THE I2C-BUS
The I2 C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the I2 C-bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
7.2 Start and stop conditions
Both data and clock lines remain HIGH when the I2 C-bus
is not busy. A HIGH-to-LOW transition of the data line,
while the clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the stop condition (P).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.4 Acknowledge
The number of data bytes transferred between the start
and stop conditions from transmitter to receiver is not
limited. Each byte is followed by one acknowledge bit.
The acknowledge bit is a HIGH level put on the I2C-bus by
the transmitter whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is
addressed must generate an acknowledge after the
reception of each byte. Also a master must generate an
acknowledge after the reception of each byte that has
been clocked out of the slave transmitter. The device that
acknowledges has to pull down the SDA line during the
acknowledge clock pulse, set-up and hold times must be
taken into account. A master receiver must signal an end
of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a stop
condition.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
Note Reduce by 7.7 mW/K when Tamb >60 °C. HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe it is
desirable to take normal precautions appropriate to handling MOS devices. Advice can be found in Data Handbook IC12
under “Handling MOS Devices”. DC CHARACTERISTICS
VDD= 2.5to6 V; VSS =0V; Tamb= −40to85 °C; unless otherwise specified.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C
Notes Typical conditions: VDD=5 V; Tamb =25 °C. Resets all logic when VDD< VPOR. Periodically sampled, not 100% tested. Outputs measured one at a time. Outputs measured one at a time; VDD=5 V; Iload= 100 μA.
Philips Semiconductors Product specification
LCD direct/duplex driver with2 C-bus interface PCF8577C AC CHARACTERISTICS
VDD= 2.5to6 V; Tamb= −40to85 °C; unless otherwise specified. All the timing values are valid within the operating
supply voltage and ambient temperature range and refer to VIL and VIH with an input voltage swing of VSSto VDD.
Note Typical conditions: VDD = 5 V; Tamb = 25 °C.
