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PCF8576T
Universal LCD driver for low multiplex rates
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
6.1 Power-on reset
6.2 LCD bias generator
6.3 LCD voltage selector
6.4 LCD drive mode waveforms
6.5 Oscillator
6.5.1 Internal clock
6.5.2 External clock
6.6 Timing
6.7 Display latch
6.8 Shift register
6.9 Segment outputs
6.10 Backplane outputs
6.11 Display RAM
6.12 Data pointer
6.13 Subaddress counter
6.14 Output bank selector
6.15 Input bank selector
6.16 Blinker CHARACTERISTICS OF THE I2 C-BUS
7.1 Bit transfer (see Fig.12)
7.2 START and STOP conditions (see Fig.13)
7.3 System configuration (see Fig.14)
7.4 Acknowledge (see Fig.15)
7.5 PCF8576 I2C-bus controller
7.6 Input filters
7.7 I2 C-bus protocol
7.8 Command decoder
7.9 Display controller
7.10 Cascaded operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS
11.1 Typical supply current characteristics
11.2 Typical characteristics of LCD outputs APPLICATION INFORMATION
12.1 Chip-on-glass cascadability in single plane BONDING PAD INFORMATION TRAY INFORMATION: PCF8576U TRAY INFORMATION: PCF8576U/2 PACKAGE OUTLINES SOLDERING
17.1 Introduction to soldering surface mount
packages
17.2 Reflow soldering
17.3 Wave soldering
17.4 Manual soldering
17.5 Suitability of surface mount IC packages for
wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
FEATURES Single-chip LCD controller/driver Selectable backplane drive configuration: staticor 2/3/4
backplane multiplexing Selectable display bias configuration: static,1 ⁄2 or1⁄3 Internal LCD bias generation with voltage-follower
buffers 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements 40× 4-bit RAM for display data storage Auto-incremented display data loading across device
subaddress boundaries Display memory bank switching in static and duplex
drive modes Versatile blinking modes LCD and logic supplies may be separated Wide power supply range: from 2 V for low-threshold
LCDs and up to 9 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs Low power consumption Power-saving mode for extremely low power
consumption in battery-operated and telephone
applicationsI2 C-bus interface TTL/CMOS compatible Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers May be cascaded for large LCD applications (up to
2560 segments possible) Cascadable with 24-segment LCD driver PCF8566 Optimized pinning for plane wiring in both single and
multiple PCF8576 applications Space-saving 56-lead plasticvery small outlinepackage
(VSO56) Very low external component count (at most one
resistor, even in multiple device applications) Compatible with chip-on-glass technology Manufactured in silicon gate CMOS process.
GENERAL DESCRIPTIONThe PCF8576 is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containingupto four backplanes andup40 segments and can easilybe cascadedfor larger LCD
applications. The PCF8576 is compatible with most
microprocessors/microcontrollersand communicatesviaa
two-line bidirectional I2 C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
ORDERING INFORMATION
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
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BLOCK DIAGRAM
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
PINNING
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576 FUNCTIONAL DESCRIPTION
The PCF8576isa versatile peripheral device designedto
interface to any microprocessor/microcontroller to a wide
variety of LCDs. It can directly drive any static or
multiplexed LCD containingupto four backplanes andup
to 40 segments. The display configurations possible with
the PCF8576 depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table.
All of the display configurations given in Table can be
implemented in the typical system shown in Fig.3.
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the PCF8576.
The internal oscillator is selected by connecting pin OSC
to pin VSS. The appropriate biasing voltages for the
multiplexed LCD waveforms are generated internally. The
only other connections required to complete the system
are to the power supplies (VDD, VSS and VLCD) and the
LCD panel chosen for the application.
Selection of display configurations
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.1 Power-on reset power-on the PCF8576 resetstoa starting conditionas
follows: All backplane outputs are set to VDD. All segment outputs are set to VDD. The drive mode‘1:4 multiplex with1 ⁄3bias’is selected. Blinking is switched off. Input and output bank selectors are reset (as defined
in Table4). The I2 C-bus interface is initialized. The data pointer and the subaddress counter are
cleared.
Data transferson theI2 C-bus shouldbe avoidedfor1 ms
following power-onto allow completionof the reset action.
6.2 LCD bias generator
The full-scale LCD voltage (Vop) is obtained from
VDD− VLCD. The LCD voltage may be temperature
compensated externally through the VLCD supplyto pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected betweenVDD and VLCD. The centre resistor can
be switched out of the circuit to provide a1 ⁄2bias voltage
level for the 1:2 multiplex configuration.
6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexingof
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop =VDD− VLCD and the
resulting discrimination ratios (D), are given in Table1. practical valuefor Vopis determinedby equating Voff(rms)
witha defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast.In the static
drive mode a suitable choice is Vop >3Vth approximately.
Multiplex drive ratios of 1: 3 and 1: 4 with1 ⁄2bias are
possible but the discrimination and hence the contrast
ratios are smaller ( = 1.732 for 1: 3 multiplex or 1.528 for 1: 4 multiplex).
The advantage of these modes is a reduction of the LCD
full-scale voltage Vop as follows:1: 3 multiplex (1 ⁄2bias):
Vop= = 2.449 Voff(rms)1: 4 multiplex (1 ⁄2bias):
Vop= = 2.309 Voff(rms)
These compare with Vop =3Voff(rms) when 1⁄3biasis used.----------off rms〈〉××-
Table 1 Preferred LCD drive modes: summary of characteristics
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.4 LCD drive mode waveforms
The static LCD drive mode is used when a single
backplaneis providedin the LCD.Backplaneand segment
drive waveforms for this mode are shown in Fig.4.
When two backplanes are provided in the LCD, the 1:2
multiplex mode applies. The PCF8576 allows use of ⁄2bias or1 ⁄3bias in this mode as shown in Figs5 and6.
When three backplanes are providedin the LCD, the1:3
multiplex drive mode applies, as shown in Fig.7.
When four backplanes are provided in the LCD, the 1:4
multiplex drive mode applies, as shown in Fig.8.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.5 Oscillator
6.5.1 INTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576 are timed eitherby the internal oscillatoror from
an external clock. When the internal oscillator is used,
pin OSC shouldbe connectedto pin VSS.In this event, the
output from pin CLK provides the clock signal for
cascaded PCF8566s in the system.
Where resistor Roscto VSSis present, the internal oscillator
is selected. The relationship between the oscillator
frequency on pin CLK (fclk) and Rosc is shown in Fig.9.
6.5.2 EXTERNAL CLOCK
The condition for external clock is made by connecting
pin OSC to pin VDD; pin CLK then becomes the external
clock input.
The clock frequency (fclk) determines the LCD frame
frequency and the maximum rate for data reception from
the I2 C-bus. To allow I2 C-bus transmissions at their
maximum data rateof 100 kHz,fclk shouldbe chosentobe
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6 Timing
The timingof the PCF8576 organizestheinternal dataflow
of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576s in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 2). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to
pin CLK when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating.In the power-saving mode the reduction ratiois
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
resultsina significant reductionin power dissipation. The
lower clock frequency has the disadvantageof increasing
the response time when large amountsof display data are
transmitted on the I2C-bus.
When a device is unable to digest a display data byte
before the next one arrives,it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2 C-bus but no data loss occurs.
Table 2 LCD frame frequencies
6.7 Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. Thereisa
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.8 Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.9 Segment outputs
The LCD drive section includes 40 segment outputs
pinsS0to S39 which should be connected directly to the
LCD. The segment output signals are generated in
accordance with the multiplexed backplane signals and
with data resident in the display latch. When less than segment outputs are required the unused segment
outputs should be left open-circuit.
6.10 Backplane outputs
The LCD drive section includes four backplane outputs
BP0to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode.If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1: 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be connected together to give
enhanced drive capabilities. In the 1: 2 multiplex drive
mode BP0 and BP2, BP1 and BP3 respectively carry the
same signals and may alsobe pairedto increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
6.11 Display RAM
The display RAM is a static 40× 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bitsofa RAM
word and the backplane outputs. The first RAM column
correspondsto the40 segments operated with respectto
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576 the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode. To
illustrate the filling order, an example of a 7-segment
numeric display showingall drive modesis givenin Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.
With referenceto Fig.11,in the static drive mode the eight
transmitted data bits are placedinbit0of eight successive
display RAM addresses.In the1:2 multiplex drive mode
the eight transmitted data bits are placedin bits0 and1of
four successive display RAM addresses. In the 1:3
multiplex drive mode these bits are placed in
bits0,1 and2of three successive addresses, withbit2of
the third address left unchanged. This last bit may, if
necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding
adjacent data because fullbytes are always transmitted.In
the 1: 4 multiplex drive mode the eight transmitted data
bits are placed in bits0,1,2 and 3 of two successive
display RAM addresses.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.12 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of individual display data byte,ora seriesof display data
bytes, into any locationof the display RAM. The sequence
commences with the initializationof the data pointerby the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incrementedin accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode),by four(1:2 multiplex drive mode)or
by two (1: 4 multiplex drive mode).
6.13 Subaddress counter
The storageof display datais conditionedby the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to A0, A1
and A2. The subaddress counter value is defined by the
DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddressdo not
agree then data storageis inhibited but the data pointeris
incremented as if data storage had taken place. The
subaddress counter is also incremented when the data
pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576 occurs when
the last RAM addressis exceeded. Subaddressing across
device boundariesis successful evenif the changeto the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1: 3 multiplex mode).
6.14 Output bank selector
This selects oneof the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence. In 1:4
multiplex, all RAM addresses of bit 0 are the first to be
selected, these are followed by the contents of bit1,bit2
and then bit 3. Similarly in 1: 3 multiplex, bits0,1 and2
are selected sequentially. In 1: 2 multiplex, bits0 and1
are selected and, in the static mode, bit 0 is selected.
The PCF8576 includes a RAM bank switching feature in
the static and 1: 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1: 2 drive mode, the contents of
bits2 and3 maybe selected insteadof bits0 and1. This
gives the provisionfor preparing display informationinan
alternative bank and to be able to switch to it once it is
assembled.
6.15 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data canbe loadedinbit2in static
drive mode or in bits2 and 3 in 1: 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
6.16 Blinker
The display blinking capabilities of the PCF8576 are very
versatile. The whole display canbe blinkedat frequencies
selectedby the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies dependon the
mode in which the device is operating, as shown in
Table3.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and:2 LCD drive modes and can be implemented without
any communication overheads. By means of the output
bank selector, the displayed RAM banks are exchanged
with alternate RAM banks at the blinking frequency. This
mode can also be specified by the BLINK command. the1:3 and1:4 multiplex modes, whereno alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this canbe effectively
performedby resetting and setting the display enablebitE
at the required rate using the MODE SET command.
Table 3 Blinking frequencies
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Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576 CHARACTERISTICS OF THE I2 C-BUS
The I2 C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines mustbe connectedtoa positive supply viaa pull-up
resistor when connectedto the output stagesofa device.
Data transfer may be initiated only when the bus is not
busy.
7.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse. The
dataon the SDA line must remain stable during the HIGH
periodof the clock pulseas changesin the data lineat this
time will be interpreted as a control signal.
7.2 START and STOP conditions (see Fig.13)
Both data and clock lines remain HIGH when the busis not
busy.A HIGH-to-LOW transitionof the data line, while the
clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transitionof the data line while the clockis
HIGH is defined as the STOP condition (P).
7.3 System configuration (see Fig.14) device generatinga messageisa ‘transmitter’,a device
receiving a message is the ‘receiver’. The device that
controls the messageis the ‘master’ andthe devices which
are controlled by the master are the ‘slaves’.
7.4 Acknowledge (see Fig.15)
The numberof data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal puton the busby the transmitter during which time
the master generatesan extra acknowledge related clock
pulse.A slave receiver whichis addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse,so that the SDA lineis stable LOW during the HIGH
periodof the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked outof the slave.In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
7.5 PCF8576 I2 C-bus controller
The PCF8576 acts as an I2 C-bus slave receiver. It does
not initiate I2C-bus transfersor transmit datatoan I2C-bus
master receiver. The only data output from the PCF8576
are the acknowledge signals of the selected devices.
Device selection depends on the I2 C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0,A1 andA2 are normally connectedto VSS which
defines the hardware subaddress 0. In multiple device
applications A0,A1 andA2 are connectedto VSSor VDDin
accordance witha binary coding scheme such thatno two
devices with a common I2 C-bus slave address have the
same hardware subaddress. the power-saving modeitis possible that the PCF8576
is not able to keep up with the highest transmission rates
when large amountsof display data are transmitted.If this
situation occurs, the PCF8576 forces the SCL lineto LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2 C-bus and
servesto slow down fast transmitters. Data loss does not
occur.
7.6 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7 I2 C-bus protocol
TwoI2 C-bus slaveaddresses (0111000 and 0111001)are
reserved for the PCF8576. The least significant bit of the
slave address thata PCF8576 willrespondtois definedby
the level connected at its input pin SA0. Therefore, two
types of PCF8576 can be distinguished on the same2 C-bus which allows: Upto16 PCF8576son the sameI2 C-busfor very large
LCD applications The use of two types of LCD multiplex on the same2 C-bus.
TheI2 C-bus protocolis shownin Fig.16. The sequenceis
initiated with a START condition (S) from the I2C-bus
master whichis followedby oneof the two PCF8576 slave
addresses available. AllPCF8576s withthecorresponding
SA0 level acknowledge in parallel with the slave address
butall PCF8576s with the alternative SA0 level ignore the
whole I2C-bus transfer.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
After acknowledgement, oneor more command bytes (m)
follow which define the statusof the addressed PCF8576s.
The last command byte is tagged with a cleared most
significant bit, the continuationbitC. The command bytes
are also acknowledged byall addressed PCF8576son the
bus.
After the last command byte,a seriesof display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576 device. The
acknowledgement after each byteis made onlyby the (A0,
A1 and A2) addressed PCF8576. After the last display
byte, the I2 C-bus master issues a STOP condition (P).
7.8 Command decoder
The command decoder identifies command bytes that
arrive on the I2 C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When thisbitis set,it indicates that the next byte
of the transfer to arrive will also represent a command. If
this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands availableto the PCF8576 are defined
in Table4.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
Philips Semiconductors Product specification
Universal LCD driver for low multiplex rates PCF8576
