PCF8576CTT ,Universal LCD driver for low multiplex ratesapplications) Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing1 ..
PCF8576CU/2/F2 ,PCF8576C; Universal LCD driver for low multiplex rates
PCF8576CU/2/F2 ,PCF8576C; Universal LCD driver for low multiplex rates
PCF8576DH , Universal LCD driver for low multiplex rates
PCF8576DH , Universal LCD driver for low multiplex rates
PCF8576DT ,Universal LCD driver for low multiplex ratesapplications Single chip LCD controller and driver Selectable backplane drive configuration: stat ..
PHB110NQ08T ,N-channel TrenchMOS standard level FETapplications Uninterruptible power supplies1.4 Quick reference data Table 1. Quick referenceSymbol ..
PHB130N03LT ,TrenchMOS transistor Logic level FET
PHB130N03LT ,TrenchMOS transistor Logic level FET
PHB130N03T ,TrenchMOS transistor Standard level FET
PHB152NQ03LT ,TrenchMOS(tm) logic level FET
PHB160N03T ,N-channel enhancement mode field-effect transistor
PCF8576CTT
Universal LCD driver for low multiplex rates
1. General descriptionThe PCF8576C is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments and can easily
be cascaded for larger LCD applications. The PCF8576C is compatible with most
microcontrollers and communicates via the two-line bidirectional I2 C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing and by
hardware subaddressing.
For a selection of NXP LCD segment drivers, see Table 24 on page 52.
2. Features and benefits Single-chip LCD controller and driver 40 segment drives: Up to twenty 7-segment alphanumeric characters Up to ten 14-segment alphanumeric characters Any graphics of up to 160 elements Versatile blinking modes No external components required (even in multiple device applications) Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing Selectable display bias configuration: static, 1 ⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 40 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Wide logic LCD supply range: From 2 V for low-threshold LCDs Up to 6 V for high-threshold twisted nematic LCDs Low power consumption May be cascaded for large LCD applications (up to 2560 elements possible) No external components required Separate or combined LCD and logic supplies Optimized pinning for plane wiring in both single and multiple PCF8576C applications Power-saving mode for extremely low power consumption in battery-operated and
telephone applications
PCF8576C
Universal LCD driver for low multiplex rates
Rev. 13 — 16 December 2013 Product data sheet The definition of the abbreviations and acronyms used in this data sheet can be found in Section20.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
3. Ordering information
3.1 Ordering options
4. Marking
Table 1. Ordering informationPCF8576CHL/1 LQFP64 plastic low profile quad flat package;
64 leads; body1010 1.4 mm
SOT314-2
PCF8576CT/1 VSO56 plastic very small outline package, 56 leads SOT190-1
PCF8576CU/2/F2 bare die bare die; 56 bumps; 3.2 2.92 0.40 mm PCF8576CU/2
PCF8576CU/F1 bare die wire bond die; 56 bonding pads; 3.2 2.92 0.38 mm PCF8576CU
Table 2. Ordering optionsPCF8576CHL/1 935290305118 PCF8576CHL/1,118 1 tape and reel, 13 inch
935290305157 PCF8576CHL/1,157 1 tray pack
PCF8576CT/1 935278818518 PCF8576CT/1,518 1 tape and reel, 13 inch, dry pack
PCF8576CU/2/F2 935261851026 PCF8576CU/2/F2,0261 chips in tray
PCF8576CU/F1 935208600026 PCF8576CU/F1,026 1 chips in tray
Table 3. Marking codesPCF8576CHL/1 PCF8576CHL
PCF8576CT/1 PCF8576CT
PCF8576CU/2/F2 PC8576C-2
PCF8576CU/F1 PC8576C-1
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
5. Block diagramNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
6. Pinning information
6.1 PinningNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
6.2 Pin description[1] The substrate (rear side of the die) is connected to VDD and should be electrically isolated.
Table 4. Pin descriptionInput or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified.
SDA 10 1 1 input/output I2 C-bus serial data input and output
SCL 11 2 2 input I2 C-bus serial clock input
SYNC 12 3 3 input/output cascade synchronization input and
output
CLK 13 4 4 input/output external clock input/output
VDD 14 5 5[1] supply supply voltage
OSC 15 6 6 input internal oscillator enable input
A0 to A2 16 to 18 7to9 7to9 input subaddress inputs
SA0 19 10 10 input I2 C-bus address input; bit0
VSS 20 11 11 supply ground supply voltage
VLCD 21 12 12 supply LCD supply voltage
BP0, BP2,
BP1, BP3
25 to 28 13to16 13to16 output LCD backplane outputs
S0 to S39 2 to 7, 29to 32, to 47, 49 to 64to56 17to56 output LCD segment outputs
n.c. 1, 8, 9, 22to 24,
33, 48 - - not connected; do not connect and
do not use as feed through
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates Functional descriptionThe PCF8576C is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 5). It
can directly drive any static or multiplexed LCD containing up to four backplanes and up to segments.
The possible display configurations of the PCF8576C depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 5. All
of these configurations can be implemented in the typical system shown in Figure6.
Table 5. Selection of possible display configurations
Number of 160 20 10 160 dots (4 40) 120 15 7 120 dots (3 40)
280 10 580 dots (2 40)
140 5240 dots (1 40)
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesThe host microprocessor or microcontroller maintains the 2-line I2 C-bus communication
channel with the PCF8576C.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On-Reset (POR)At power-on the PCF8576C resets to the following starting conditions:
All backplane and segment outputs are set to VDD
The selected drive mode is 1:4 multiplex with 1 ⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2 C-bus interface is initialized
The data pointer and the subaddress counter are cleared
Remark: Do not transfer data on the I2 C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generatorThe full-scale LCD voltage (Voper) is obtained from VDD VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin VLCD.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a 1 ⁄2 bias voltage level for the 1:2 multiplex
configuration.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.3 LCD voltage selectorThe LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table6.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD >3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1 ⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by
a = 1 for 1 ⁄2 bias
a = 2 for 1 ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation1:
(1)
where the values for n are= 1 for static drive mode= 2 for 1:2 multiplex drive mode= 3 for 1:3 multiplex drive mode= 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation3:
Table 6. Biasing characteristicsstatic 1 2 static 0 1
1:2 multiplex2 3 1⁄2 0.354 0.791 2.236
1:2 multiplex2 4 1⁄3 0.333 0.745 2.236
1:3 multiplex3 4 1⁄3 0.333 0.638 1.915
1:4 multiplex4 4 1⁄3 0.333 0.577 1.732
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 biasis⁄2 bias is
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
1:3 multiplex (1 ⁄2 bias):
1:4 multiplex (1 ⁄2 bias):
These compare with 1 ⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performanceSuitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 7. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a (see Equation 1), n (see Equation 3), and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive modeThe static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure8.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive modeWhen two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8576C allows the use of 1 ⁄2 bias or 1 ⁄3 bias (see Figure 9 and Figure 10).
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesNXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive modeWhen three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure 11.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive modeWhen four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 12.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.5 OscillatorThe internal logic and the LCD drive signals of the PCF8576C are timed by the frequency
fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency
fclk(ext).
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from the I2 C-bus. To allow I2 C-bus transmissions at their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clockThe internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8576C in the system.
7.5.2 External clockConnecting pin OSC to VDD enables an external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock, freezes the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 TimingThe timing of the PCF8576C sequences the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8576Cs in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 7). The frame frequency is set by the mode-set command (see Table 10) when an
internal clock is used or by the frequency applied to the pin CLK when an external clock is
used.
[1] The possible values for fclk see Table17.
[2] For fclk = 200 kHz.
[3] For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
power mode in which the device is operating. In the power-saving mode, the reduction
ratio is six times smaller; this allows the clock frequency to be reduced by a factor of six.
The reduced clock frequency results in a significant reduction in power consumption.
Table 7. LCD frame frequencies [1]Normal-power mode 69 [2]
Power-saving mode 65 [3]
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesThe lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I2 C-bus. When a device is unable to
process a display data byte before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the transmission rate of the I2 C-bus
but no data loss occurs.
7.7 Display registerThe display register holds the display data while the corresponding multiplex signals are
generated.
7.8 Shift registerThe shift register transfers display information from the display RAM to the display register
while previous data is displayed.
7.9 Segment outputsThe LCD drive section includes 40 segment outputs, S0to S39, which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data residing in the display register. When less than segment outputs are required, the unused segment outputs should be left open-circuit.
7.10 Backplane outputsThe LCD drive section includes four backplane outputs: BP0to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left as an
open-circuit.
In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
In static drive mode: the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAMThe display RAM is a static 40 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
the bits in the RAM bitmap and the LCD elements
the RAM columns and the segment outputs
the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesThe display RAM bit map Figure 13 shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2,
and BP3 respectively.
When display data is transmitted to the PCF8576C, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triples or
quadruples. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 14; the RAM filling organization depicted
applies equally to other LCD types.
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
x x
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesThe following applies to Figure 14:
In the static drive mode, the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
In the 1:2 multiplex mode, the eight transmitted data bits are placed in pairs into
row0 and 1 of four successive 4-bit RAM words.
In the 1:3 multiplex mode, the eight bits are placed in triples into row0,1, and 2 to
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
In the 1:4 multiplex mode, the eight transmitted data bits are placed in quadruples into
row0,1, 2, and 3 of two successive 4-bit RAM words.
7.12 Data pointerThe addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 11). After this, the data byte is
stored starting at the display RAM address indicated by the data pointer (see Figure 14).
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD configuration.
The contents of the data pointer are incremented as follows:
In static drive mode by eight.
In 1:2 multiplex drive mode by four.
In 1:3 multiplex drive mode by three.
In 1:4 multiplex drive mode by two.
If an I2 C-bus data access terminates early, the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
7.13 Sub-address counterThe storage of display data is conditioned by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value
is defined by the device-select command (see Table 12). If the contents of the subaddress
counter and the hardware subaddress do not match, then data storage is blocked but the
data pointer will be incremented as if data storage had taken place. The subaddress
counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8576C occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.14 Bank selector
7.14.1 Output bank selectorThe output bank selector (see Table 13), selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence.
In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially
by the contents of row1, row 2, and then row3.
In 1:3 multiplex mode: rows0,1, and 2 are selected sequentially.
In 1:2 multiplex mode: rows0 and 1 are selected.
In the static mode: row 0 is selected.
The PCF8576C includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive
mode, the contents of rows2 and 3 may be selected instead of rows0 and 1. This
enables preparation of display information in an alternative bank and the ability to switch
to it once it has been assembled.
7.14.2 Input bank selectorThe input bank selector (see Table 13) loads display data into the display RAM based on
the selected LCD drive configuration. Using the bank-select command, display data can
be loaded in row 2 into static drive mode or in rows2 and 3 into 1:2 multiplex drive mode.
The input bank selector functions independently of the output bank selector.
7.15 BlinkingThe display blinking capabilities of the PCF8576C are very versatile. The whole display
can be blinked at frequencies selected by the blink-select command. The blinking
frequencies are integer fractions of the clock frequency; the ratios between the clock and
blinking frequencies depend on the mode in which the device is operating (see Table8).
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
specified by the blink-select command (see Table 14).
Table 8. Blink frequenciesoff - - blinking off 2 Hz 1 Hz 0.5 Hz
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex ratesIn the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at fixed time
intervals.
If the entire display must be blinked at a frequency other than the nominal blink frequency,
this can be done using the mode-set command to set and reset the display enable bit E at
the required rate (see Table 10).
7.16 Characteristics of the I2 C-busThe I2 C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 15.
7.16.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S). LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 16.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.16.3 System configurationA device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure 17.
7.16.4 AcknowledgeThe number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2 C-bus is illustrated in Figure 18.
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.16.5 PCF8576C I2 C-bus controllerThe PCF8576C acts as an I2 C-bus slave receiver. It does not initiate I2 C-bus transfers or
transmit data to an I2 C-bus master receiver. The only data output from the PCF8576C are
the acknowledge signals of the selected devices. Device selection depends on the 2 C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1, and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications
A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2 C-bus slave address have the same hardware subaddress.
In the power-saving mode, it is possible that the PCF8576C is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2 C-bus and serves
to slow down fast transmitters. Data loss does not occur.
7.16.6 Input filterTo enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.17I2 C-bus protocolTwo I2 C-bus slave addresses (0111000 and 0111001) are reserved for the PCF8576C.
The least significant bit of the slave address that a PCF8576C responds to is defined by
the level tied at its input SA0. Therefore, two types of PCF8576C can be distinguished on
the same I2 C-bus which allows:
Up to 16 PCF8576Cs on the same I2 C-bus for very large LCD applications.
The use of two types of LCD multiplexes on the same I2 C-bus.
The I2 C-bus protocol is shown in Figure 19. The sequence is initiated with a START
condition (S) from the I2 C-bus master which is followed by one of the two PCF8576C
slave addresses available. All PCF8576Cs with the corresponding SA0 level acknowledge
in parallel with the slave address but all PCF8576Cs with the alternative SA0 level ignore
the whole I2 C-bus transfer.
After acknowledgement, one or more command bytes follow which define the status of the
addressed PCF8576Cs.
The last command byte is tagged with a cleared most significant bit, the continuation bit C.
The command bytes are also acknowledged by all addressed PCF8576Cs on the bus.
After the last command byte, a series of display data bytes may follow. These display
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8576C device. The acknowledgement after
each byte is made only by the (A0, A1, and A2) addressed PCF8576C. After the last
display byte, the I2 C-bus master issues a STOP condition (P).
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.18 Command decoderThe command decoder identifies command bytes that arrive on the I2 C-bus. All available
commands carry a continuation bit C in the most significant bit position as shown in
Figure 20. When this bit is set logic 1, it indicates that the next byte of the transfer to arrive
will also represent a command. If this bit is set logic 0, it indicates that the command byte
is the last in the transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8576C are defined in Table9.
Table 9. Definition of PCF8576C commands
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.18.1 Mode-set command[1] The possibility to disable the display allows implementation of blinking under external control.
[2] Bit B is not applicable for the static LCD drive mode.
7.18.2 Load-data-pointer command
7.18.3 Device-select command
Table 10. Mode-set command bit description 0, 1see Figure20
6 to 5 - 10 fixed value
4LP
power dissipation (see Table7) normal-power mode power-saving mode
display status disabled[1] enabled
LCD bias configuration[2] 1 ⁄3 bias 1 ⁄2 bias
1 to 0 M[1:0]
LCD drive mode selection static; BP0 1:2 multiplex; BP0, BP1 1:3 multiplex; BP0, BP1, BP2 1:4 multiplex; BP0, BP1, BP2, BP3
Table 11. Load-data-pointer command bit description 0, 1see Figure20 - 0 fixed value
5 to 0 P[5:0] 000000 to
6-bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Table 12. Device-select command bit description 0, 1see Figure20
6 to 4 - 1100 fixed value
3 to 0 A[2:0] 000 to 111 3-bit binary value, 0 to 7; transferred to the subaddress
counter to define oneof eight hardware subaddresses
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
7.18.4 Bank-select command[1] The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
7.18.5 Blink-select command[1] Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[2] Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.19 Display controllerThe display controller executes the commands identified by the command decoder. It
contains the status registers of the PCF8576C and coordinates their effects. The
controller is also responsible for loading display data into the display RAM as required by
the filling order.
Table 13. Bank-select command bit description C 0, 1 see Figure20
6 to 2 - 11110 fixed value
input bank selection; storage of arriving display data RAM bit 0 RAM bits 0 and 1 RAM bit 2 RAM bits 2 and 3
output bank selection; retrieval of LCD display data RAM bit 0 RAM bits 0 and 1 RAM bit 2 RAM bits 2 and 3
Table 14. Blink-select command bit description 0, 1see Figure20
6 to 3 - 1110 fixed value
2AB
blink mode selection normal blinking[1] alternate RAM bank blinking[2]
1 to 0 BF[1:0]
blink frequency selection off 1 2 3
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
8. Internal circuitry
9. Safety notes
NXP Semiconductors PCF8576C
Universal LCD driver for low multiplex rates
10. Limiting values[1] Values with respect to VDD.
[2] Pass level; Human Body Model (HBM), according to Ref. 8 “JESD22-A114”.
[3] Pass level; Machine Model (MM), according to Ref. 9 “JESD22-A115”.
[4] Pass level; Charged-Device Model (CDM), according to Ref. 10 “JESD22-C101”.
[5] Pass level; latch-up testing according to Ref. 11 “JESD78” at maximum ambient temperature (Tamb(max)).
[6] According to the store and transport requirements (see Ref. 13 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75%.
Table 15. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +8.0 V
VLCD LCD supply voltage [1] VDD 8.0 VDD V input voltage on each of the pins SCL, SDA,
CLK, SYNC, SA0, OSC and toA2
0.5 +8.0 V output voltage on each of the pins to S39 and BP0to BP3
[1] 0.5 +8.0 V input current 20 +20 mA output current 25 +25 mA
IDD supply current 50 +50 mA
ISS ground supply current 50 +50 mA
IDD(LCD) LCD supply current 50 +50 mA
Ptot total power dissipation - 400 mW output power - 100 mW
VESD electrostatic discharge
voltage
HBM [2]- 4000 V
CDM [4]
PCF8576CHL
all pins - 500 V
corner pins - 1000 V
PCF8576CT
all pins - 500 V
corner pins - 750 V
Ilu latch-up current [5]- 150 mA
Tstg storage temperature [6] 65 +150 C
Tamb ambient temperature operating device 40 +85 C
