PCF8576CT ,Universal LCD driver for low multiplex ratesINTEGRATED CIRCUITSDATA SHEETPCF8576CUniversal LCD driver for lowmultiplex rates1998 Jul 30Product ..
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PCF8576DH , Universal LCD driver for low multiplex rates
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PCF8576CH-PCF8576CT
Universal LCD driver for low multiplex rates
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION
6.1 Power-on reset
6.2 LCD bias generator
6.3 LCD voltage selector
6.4 LCD drive mode waveforms
6.4.1 Static drive mode
6.4.2 1: 2 multiplex drive mode
6.4.3 1: 3 multiplex drive mode
6.4.4 1: 4 multiplex drive mode
6.5 Oscillator
6.5.1 Internal clock
6.5.2 External clock
6.6 Timing
6.7 Display latch
6.8 Shift register
6.9 Segment outputs
6.10 Backplane outputs
6.11 Display RAM
6.12 Data pointer
6.13 Subaddress counter
6.14 Output bank selector
6.15 Input bank selector
6.16 Blinker CHARACTERISTICS OF THE I2 C-BUS
7.1 Bit transfer (see Fig.12)
7.2 Start and stop conditions (see Fig.13)
7.3 System configuration (see Fig.14)
7.4 Acknowledge (see Fig.15)
7.5 PCF8576C I2 C-bus controller
7.6 Input filters
7.7 I2 C-bus protocol
7.8 Command decoder
7.9 Display controller
7.10 Cascaded operation LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS
11.1 Typical supply current characteristics
11.2 Typical characteristics of LC D outputs APPLICATION INFORMATION
12.1 Chip-on-glass cascadability in single plane BONDING PAD LOCATIONS PACKAGE OUTLINES SOLDERING
15.1 Introduction
15.2 Reflow soldering
15.3 Wave soldering
15.3.1 LQFP
15.3.2 VSO
15.3.3 Method (LQFP and VSO)
15.4 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
FEATURES Single-chip LCD controller/driver Selectable backplane drive configuration: static or 2/3/4
backplane multiplexing Selectable display bias configuration: static, 1/2 or 1/3 Internal LCD bias generation with voltage-follower
buffers 40 segment drives: up to twenty 8-segment numeric
characters; up to ten 15-segment alphanumeric
characters; or any graphics of up to 160 elements 40× 4-bit RAM for display data storage Auto-incremented display data loading across device
subaddress boundaries Display memory bank switching in static and duplex
drive modes Versatile blinking modes LCD and logic supplies may be separated Wide power supply range: from 2 V for low-threshold
LCDs and up to 6 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs.
A 9 V version is also available on request. Low power consumption Power-saving mode for extremely low power
consumption in battery-operated and telephone
applicationsI2 C-bus interface TTL/CMOS compatible Compatible with any 4-bit, 8-bit or 16-bit
microprocessors/microcontrollers May be cascaded for large LCD applications (up to
2560 segments possible) Cascadable with 24-segment LCD driver PCF8566 Optimized pinning for plane wiring in both and multiple
PCF8576C applications Space-saving 56-lead plastic very small outline package
(VSO56) or 64-lead low profile quad flat package
(LQFP64) No external components Compatible with chip-on-glass technology Manufactured in silicon gate CMOS process.
GENERAL DESCRIPTIONThe PCF8576C is a peripheral device which interfaces to
almost any Liquid Crystal Display (LCD) with low multiplex
rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments and can easily be cascaded for larger LCD
applications. The PCF8576C is compatible with most
microprocessors/microcontrollers and communicates via a
two-line bidirectional I2 C-bus. Communication overheads
are minimized by a display RAM with auto-incremented
addressing, by hardware subaddressing and by display
memory switching (static and duplex drive modes).
ORDERING INFORMATION
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
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BLOCK DIAGRAM
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
PINNING
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C FUNCTIONAL DESCRIPTION
The PCF8576C is a versatile peripheral device designed
to interface to any microprocessor/microcontroller to a
wide variety of LCDs. It can directly drive any static or
multiplexed LCD containing up to four backplanes and up
to 40 segments. The display configurations possible with
the PCF8576C depend on the number of active backplane
outputs required; a selection of display configurations is
given in Table1.
All of the display configurations given in Table 1 can be
implemented in the typical system shown in Fig.4.
The host microprocessor/microcontroller maintains the
2-line I2C-bus communication channel with the
PCF8576C. The internal oscillator is selected by tying
OSC (pin 6) to VSS (pin 11). The appropriate biasing
voltages for the multiplexed LCD waveforms are
generated internally. The only other connections required
to complete the system are to the power supplies (VDD,
VSS and VLCD) and the LCD panel chosen for the
application.
Table 1 Selection of display configurations
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.1 Power-on reset
At power-on the PCF8576C resets to a starting condition
as follows: All backplane outputs are set to VDD. All segment outputs are set to VDD. The drive mode ‘1: 4 multiplex with1 ⁄3bias’ is selected. Blinking is switched off. Input and output bank selectors are reset (as defined
in Table5). The I2 C-bus interface is initialized. The data pointer and the subaddress counter are
cleared.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on to allow completion of the reset action.
6.2 LCD bias generator
The full-scale LCD voltage (Vop) is obtained from
VDD− VLCD. The LCD voltage may be temperature
compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an
internal voltage divider of the three series resistors
connected between VDD and VLCD. The centre resistor can
be switched out of the circuit to provide a1 ⁄2bias voltage
level for the 1: 2 multiplex configuration.
6.3 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of
the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is
controlled by MODE SET commands from the command
decoder. The biasing configurations that apply to the
preferred modes of operation, together with the biasing
characteristics as functions of Vop =VDD− VLCD and the
resulting discrimination ratios (D), are given in Table2.
A practical value for Vop is determined by equating Voff(rms)
with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static
drive mode a suitable choice is Vop >3Vth approximately.
Multiplex drive ratios of 1: 3 and 1: 4 with1 ⁄2bias are
possible but the discrimination and hence the contrast
ratios are smaller ( = 1.732 for 1: 3 multiplex or 1.528 for 1: 4 multiplex).
The advantage of these modes is a reduction of the LCD
full-scale voltage Vop as follows:1: 3 multiplex (1 ⁄2bias):
Vop= = 2.449 Voff(rms)1: 4 multiplex (1 ⁄2bias):
Vop= = 2.309 Voff(rms)
These compare with Vop =3Voff(rms) when 1⁄3bias is used.----------off rms〈〉×× ()-
Table 2 Preferred LCD drive modes: summary of characteristics
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.4 LCD drive mode waveforms
6.4.1 STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive
waveforms for this mode are shown in Fig.5.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.4.2 1:2 MULTIPLEX DRIVE MODE
When two backplanes are provided in the LCD, the 1: 2 multiplex mode applies. The PCF8576C allows use of1 ⁄2bias or ⁄3bias in this mode as shown in Figs 6 and7.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.4.3 1:3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1: 3 multiplex drive mode applies, as shown in Fig.8.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.4.4 1:4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1: 4 multiplex drive mode applies, as shown in Fig.9.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.5 Oscillator
6.5.1 INTERNAL CLOCK
The internal logic and the LCD drive signals of the
PCF8576C are timed either by the built-in oscillator or from
an external clock. When the internal oscillator is used,
OSC (pin 6) should be connected to VSS (pin 11). In this
event, the output from CLK (pin 4) provides the clock
signal for cascaded PCF8566s or PCF8576Cs in the
system.
Note that the PCF8576C is backwards compatible with the
PCF8576. Where resistor Rosc to VSS is present, the
internal oscillator is selected.
6.5.2 EXTERNAL CLOCK
The condition for external clock is made by tying OSC
(pin 6) to VDD; CLK (pin 4) then becomes the external
clock input.
The clock frequency (fclk) determines the LCD frame
frequency and the maximum rate for data reception from
the I2 C-bus. To allow I2 C-bus transmissions at their
maximum data rate of 100 kHz, fclk should be chosen to be
above 125 kHz.
A clock signal must always be supplied to the device;
removing the clock may freeze the LCD in a DC state.
6.6 Timing
The timing of the PCF8576C organizes the internal data
flow of the device. This includes the transfer of display data
from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal SYNC
maintains the correct timing relationship between the
PCF8576Cs in the system. The timing also generates the
LCD frame frequency which it derives as an integer
multiple of the clock frequency (see Table 3). The frame
frequency is set by the MODE SET commands when
internal clock is used, or by the frequency applied to pin4
when external clock is used.
The ratio between the clock frequency and the LCD frame
frequency depends on the mode in which the device is
operating. In the power-saving mode the reduction ratio is
six times smaller; this allows the clock frequency to be
reduced by a factor of six. The reduced clock frequency
results in a significant reduction in power dissipation.
The lower clock frequency has the disadvantage of
increasing the response time when large amounts of
display data are transmitted on the I2 C-bus.
When a device is unable to digest a display data byte
before the next one arrives, it holds the SCL line LOW until
the first display data byte is stored. This slows down the
transmission rate of the I2 C-bus but no data loss occurs.
6.7 Display latch
The display latch holds the display data while the
corresponding multiplex signals are generated. There is a
one-to-one relationship between the data in the display
latch, the LCD segment outputs and one column of the
display RAM.
6.8 Shift register
The shift register serves to transfer display information
from the display RAM to the display latch while previous
data is displayed.
6.9 Segment outputs
The LCD drive section includes 40 segment outputsto S39 (pins17to 56) which should be connected
directly to the LCD. The segment output signals are
generated in accordance with the multiplexed backplane
signals and with data resident in the display latch. When
less than 40 segment outputs are required the unused
segment outputs should be left open-circuit.
6.10 Backplane outputs
The LCD drive section includes four backplane outputs
BP0to BP3 which should be connected directly to the
LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than
four backplane outputs are required the unused outputs
can be left open-circuit. In the 1: 3 multiplex drive mode
BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced
drive capabilities. In the 1: 2 multiplex drive mode BP0
and BP2, BP1 and BP3 respectively carry the same
signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is
carried by all four backplane outputs and they can be
connected in parallel for very high drive requirements.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.11 Display RAM
The display RAM is a static 40× 4-bit RAM which stores
LCD data. A logic 1 in the RAM bit-map indicates the on
state of the corresponding LCD segment; similarly, a
logic 0 indicates the off state. There is a one-to-one
correspondence between the RAM addresses and the
segment outputs, and between the individual bits of a RAM
word and the backplane outputs. The first RAM column
corresponds to the 40 segments operated with respect to
backplane BP0 (see Fig.10). In multiplexed LCD
applications the segment data of the second, third and
fourth column of the display RAM are time-multiplexed
with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8576C the
display bytes received are stored in the display RAM in
accordance with the selected LCD drive mode.
To illustrate the filling order, an example of a 7-segment
numeric display showing all drive modes is given in Fig.11;
the RAM filling organization depicted applies equally to
other LCD types.
With reference to Fig.11, in the static drive mode the eight
transmitted data bits are placed in bit 0 of eight successive
display RAM addresses.
In the 1: 2 multiplex drive mode the eight transmitted data
bits are placed in bits0 and 1 of four successive display
RAM addresses. In the 1:3 multiplex drive mode these
bits are placed in bits0,1 and 2 of three successive
addresses, with bit 2 of the third address left unchanged.
This last bit may, if necessary, be controlled by an
additional transfer to this address but care should be taken
to avoid overriding adjacent data because full bytes are
always transmitted. In the 1: 4 multiplex drive mode the
eight transmitted data bits are placed in bits0,1, 2 and3
of two successive display RAM addresses.
Table 3 LCD frame frequencies
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.12 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows the loading of
an individual display data byte, or a series of display data
bytes, into any location of the display RAM. The sequence
commences with the initialization of the data pointer by the
LOAD DATA POINTER command. Following this, an
arriving data byte is stored starting at the display RAM
address indicated by the data pointer thereby observing
the filling order shown in Fig.11. The data pointer is
automatically incremented in accordance with the chosen
LCD configuration. That is, after each byte is stored, the
contents of the data pointer are incremented by eight
(static drive mode), by four (1: 2 multiplex drive mode) or
by two (1: 4 multiplex drive mode).
6.13 Subaddress counter
The storage of display data is conditioned by the contents
of the subaddress counter. Storage is allowed to take
place only when the contents of the subaddress counter
agree with the hardware subaddress applied to
A0,A1 and A2. The subaddress counter value is defined
by the DEVICE SELECT command. If the contents of the
subaddress counter and the hardware subaddress do not
agree then data storage is inhibited but the data pointer is
incremented as if data storage had taken place.
The subaddress counter is also incremented when the
data pointer overflows.
The storage arrangements described lead to extremely
efficient data loading in cascaded applications. When a
series of display bytes are sent to the display RAM,
automatic wrap-over to the next PCF8576C occurs when
the last RAM address is exceeded. Subaddressing across
device boundaries is successful even if the change to the
next device in the cascade occurs within a transmitted
character (such as during the 14th display data byte
transmitted in 1: 3 multiplex mode).
6.14 Output bank selector
This selects one of the four bits per display RAM address
for transfer to the display latch. The actual bit chosen
depends on the particular LCD drive mode in operation
and on the instant in the multiplex sequence.
In 1:4 multiplex, all RAM addresses of bit 0 are the first to
be selected, these are followed by the contents of
bit1,bit 2 and then bit 3. Similarly in 1: 3 multiplex,
bits0,1 and 2 are selected sequentially. In 1: 2 multiplex,
bits0 and 1 are selected and, in the static mode, bit 0 is
selected.
The PCF8576C includes a RAM bank switching feature in
the static and 1: 2 multiplex drive modes. In the static
drive mode, the BANK SELECT command may request
the contents of bit 2 to be selected for display instead of
bit 0 contents. In the 1: 2 drive mode, the contents of
bits2 and 3 may be selected instead of bits0 and 1. This
gives the provision for preparing display information in an
alternative bank and to be able to switch to it once it is
assembled.
6.15 Input bank selector
The input bank selector loads display data into the display
RAM in accordance with the selected LCD drive
configuration. Display data can be loaded in bit 2 in static
drive mode or in bits2 and 3 in 1: 2 drive mode by using
the BANK SELECT command. The input bank selector
functions independent of the output bank selector.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
6.16 Blinker
The display blinking capabilities of the PCF8576C are very
versatile. The whole display can be blinked at frequencies
selected by the BLINK command. The blinking frequencies
are integer multiples of the clock frequency; the ratios
between the clock and blinking frequencies depend on the
mode in which the device is operating, as shown in
Table4.
An additional feature is for an arbitrary selection of LCD
segments to be blinked. This applies to the static and:2 LCD drive modes and can be implemented without
any communication overheads.
By means of the output bank selector, the displayed RAM
banks are exchanged with alternate RAM banks at the
blinking frequency. This mode can also be specified by the
BLINK command.
In the 1: 3 and 1: 4 multiplex modes, where no alternate
RAM bank is available, groups of LCD segments can be
blinked by selectively changing the display RAM data at
fixed time intervals.
If the entire display is to be blinked at a frequency other
than the nominal blinking frequency, this can be effectively
performed by resetting and setting the display enable bitE
at the required rate using the MODE SET command.
Table 4 Blinking frequencies
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
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Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C CHARACTERISTICS OF THE I2C-BUS
The I2 C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL). Both
lines must be connected to a positive supply via a pull-up
resistor when connected to the output stages of a device.
Data transfer may be initiated only when the bus is not
busy.
7.1 Bit transfer (see Fig.12)
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as a control signal.
7.2 Start and stop conditions (see Fig.13)
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P).
7.3 System configuration (see Fig.14)
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’.
7.4 Acknowledge (see Fig.15)
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each byte of eight bits is followed by an
acknowledge bit. The acknowledge bit is a HIGH level
signal put on the bus by the transmitter during which time
the master generates an extra acknowledge related clock
pulse. A slave receiver which is addressed must generate
an acknowledge after the reception of each byte. Also a
master receiver must generate an acknowledge after the
reception of each byte that has been clocked out of the
slave transmitter. The device that acknowledges must
pull-down the SDA line during the acknowledge clock
pulse, so that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse (set-up and
hold times must be taken into consideration). A master
receiver must signal an end of data to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a STOP condition.
7.5 PCF8576C I2C-bus controller
The PCF8576C acts as an I2 C-bus slave receiver. It does
not initiate I2 C-bus transfers or transmit data to an I2 C-bus
master receiver. The only data output from the PCF8576C
are the acknowledge signals of the selected devices.
Device selection depends on the I2 C-bus slave address,
on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress
inputs A0,A1 and A2 are normally tied to VSS which
defines the hardware subaddress 0. In multiple device
applications A0,A1 and A2 are tied to VSS or VDD in
accordance with a binary coding scheme such that no two
devices with a common I2 C-bus slave address have the
same hardware subaddress.
In the power-saving mode it is possible that the PCF8576C
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8576C forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I2 C-bus and
serves to slow down fast transmitters. Data loss does not
occur.
7.6 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7 I2C-bus protocol
Two I2 C-bus slave addresses (0111000 and 0111001) are
reserved for the PCF8576C. The least significant bit of the
slave address that a PCF8576C will respond to is defined
by the level tied at its input SA0 (pin 10). Therefore, two
types of PCF8576C can be distinguished on the same2 C-bus which allows: Up to 16 PCF8576Cs on the same I2C-bus for very
large LCD applications. The use of two types of LCD multiplex on the same
I2C-bus.
The I2 C-bus protocol is shown in Fig.16. The sequence is
initiated with a START condition (S) from the I2 C-bus
master which is followed by one of the two PCF8675C
slave addresses available. All PCF8576Cs with the
corresponding SA0 level acknowledge in parallel with the
slave address but all PCF8576Cs with the alternative SA0
level ignore the whole I2 C-bus transfer.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
After acknowledgement, one or more command bytes (m)
follow which define the status of the addressed
PCF8576Cs.
The last command byte is tagged with a cleared most
significant bit, the continuation bit C. The command bytes
are also acknowledged by all addressed PCF8576Cs on
the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data is directed to the intended PCF8576C device.
The acknowledgement after each byte is made only by the
(A0,A1 and A2) addressed PCF8576C. After the last
display byte, the I2C-bus master issues a STOP
condition (P).
7.8 Command decoder
The command decoder identifies command bytes that
arrive on the I2 C-bus. All available commands carry a
continuation bit C in their most significant bit position
(Fig.17). When this bit is set, it indicates that the next byte
of the transfer to arrive will also represent a command. this bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8576C are
defined in Table5.
Philips Semiconductors Product specification
Universal LCD driver for low multiplex
rates PCF8576C
