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PCF8574AP-PCF8574AT-PCF8574P-PCF8574T
Remote 8-bit I/O expander for I2C-bus
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
CONTENTS FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING CHARACTERISTICS OF THE I2 C-BUS
6.1 Bit transfer
6.2 Start and stop conditions
6.3 System configuration
6.4 Acknowledge FUNCTIONAL DESCRIPTION
7.1 Addressing
7.2 Interrupt
7.3 Quasi-bidirectional I/Os LIMITING VALUES HANDLING DC CHARACTERISTICS I2 C-BUS TIMING CHARACTERISTICS PACKAGE OUTLINES SOLDERING
13.1 Introduction
13.2 DIP
13.2.1 Soldering by dipping or by wave
13.2.2 Repairing soldered joints
13.3 SO and SSOP
13.3.1 Reflow soldering
13.3.2 Wave soldering
13.3.3 Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2 C COMPONENTS
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
FEATURES Operating supply voltage 2.5to6V Low standby current consumption of 10 μA maximumI2 C to parallel port expander Open-drain interrupt output 8-bit remote I/O port for the I2 C-bus Compatible with most microcontrollers Latched outputs with high current drive capability for
directly driving LEDs Address by 3 hardware address pins for use of up to devices (up to 16 with PCF8574A) DIP16, or space-saving SO16 or SSOP20 packages.
GENERAL DESCRIPTIONThe PCF8574 is a silicon CMOS circuit. It provides general
purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2C).
The device consists of an 8-bit quasi-bidirectional port and
an I2 C-bus interface. The PCF8574 has a low current
consumption and includes latched outputs with high
current drive capability for directly driving LEDs. It also
possesses an interrupt line (INT) which can be connected
to the interrupt logic of the microcontroller. By sending an
interrupt signal on this line, the remote I/O can inform the
microcontroller if there is incoming data on its ports without
having to communicate via the I2 C-bus. This means that
the PCF8574 can remain a simple slave device.
The PCF8574 and PCF8574A versions differ only in their
slave address as shown in Fig.9.
ORDERING INFORMATION
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
BLOCK DIAGRAM
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
PINNING
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574 CHARACTERISTICS OF THE I2C-BUS
The I2 C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer
may be initiated only when the bus is not busy.
6.1 Bit transfer
One data bit is transferred during each clock pulse. The
data on the SDA line must remain stable during the HIGH
period of the clock pulse as changes in the data line at this
time will be interpreted as control signals (see Fig.4).
6.2 Start and stop conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the start condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the stop condition (P) (see Fig.5).
6.3 System configuration
A device generating a message is a ‘transmitter’, a device
receiving is the ‘receiver’. The device that controls the
message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’ (see Fig.6).
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
6.4 Acknowledge
The number of data bytes transferred between the start
and the stop conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the
transmitter by not generating an acknowledge on the last
byte that has been clocked out of the slave. In this event
the transmitter must leave the data line HIGH to enable the
master to generate a stop condition.
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574 FUNCTIONAL DESCRIPTION
7.1 Addressing
For addressing see Figs9,10 and 11.
Each of the PCF8574’s eight I/Os can be independently
used as an input or output. Input data is transferred from
the port to the microcontroller by the READ mode
(see Fig.11). Output data is transmitted to the port by the
WRITE mode (see Fig.10).
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
7.2 Interrupt (see Figs12 and 13)
The PCF8574 provides an open drain output (INT) which
can be fed to a corresponding input of the microcontroller.
This gives these chips a type of master function which can
initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the
port inputs in the input mode. After time tiv the signal INT is
valid.
Resetting and reactivating the interrupt circuit is achieved
when data on the port is changed to the original setting or
data is read from or written to the port which has generated
the interrupt.
Resetting occurs as follows: In the READ mode at the acknowledge bit after the rising
edge of the SCL signal In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal Interrupts which occur during the acknowledge clock
pulse may be lost (or very short) due to the resetting of
the interrupt during this pulse.
Each change of the I/Os after resetting will be detected
and, after the next rising clock edge, will be transmitted as
INT. Reading from or writing to another device does not
affect the interrupt circuit.
7.3 Quasi-bidirectional I/Os (see Fig.14)
A quasi-bidirectional I/O can be used as an input or output
without the use of a control signal for data direction.
At power-on the I/Os are HIGH. In this mode only a current
source to VDD is active. An additional strong pull-up to VDD
allows fast rising edges into heavily loaded outputs. These
devices turn on when an output is written HIGH, and are
switched off by the negative edge of SCL. The I/Os should
be HIGH before being used as inputs.
Philips Semiconductors Product specification
Remote 8-bit I/O expander for I2 C-bus PCF8574
