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PCF8566T
Universal LCD driver for low multiplex rates
General descriptionThe PCF8566isa peripheral device which interfacesto almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containingupto four backplanes andupto24 segments and can easilybe cascaded
for larger LCD applications. The PCF8566 is compatible with most microprocessors or
microcontrollers and communicates via a two-line bidirectional I2 C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes). Features Single-chip LCD controller/driver 24 segment drives: Up to twelve 7-segment numeric characters including decimal pointer Up to six 14-segment alphanumeric characters Any graphics of up to 96 elements Versatile blinking modes No external components required (even in multiple device applications) Selectable backplane drive conﬁguration: static or 2, 3, 4 backplane multiplexing Selectable display bias conﬁguration: static,1 ⁄2 or1⁄3 Internal LCD bias generation with voltage-follower buffers 24× 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes LCD and logic supplies may be separated 2.5 V to 6 V power supply range Low power consumption Power-saving mode for extremely low power consumption in battery-operated and
telephone applicationsI2 C-bus interface TTL and CMOS compatible Compatible with any 4, 8 or 16-bit microprocessor or microcontroller May be cascaded for large LCD applications (up to 1536 segments possible) Cascadable with 40-segment LCD driver PCF8576C Optimized pinning for plane wiring in both and multiple PCF8566 applications Space-saving 40-lead plastic very small outline package (VSO40; SOT158-1) Manufactured in silicon gate CMOS process
PCF8566
Universal LCD driver for low multiplex rates
Rev. 07 — 25 February 2009 Product data sheet
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates Ordering information
[1] Dark-green version.
[2] Chip in tray for chip on board. Marking
Table 1. Ordering information
PCF8566P DIP40 plastic dual in-line package; 40 leads (600 mil) SOT129-1
PCF8566T VSO40 plastic very small outline package; 40 leads SOT158-1
PCF8566TS[1] VSO40 plastic very small outline package; 40 leads SOT158-1
PCF8566U[2] PCF8566U wire bond die; 40 bonding pads;
2.5 × 2.91 × 0.381 mm
PCF8566U
Table 2. Marking codes
PCF8566P PCF8566P
PCF8566T PCF8566T
PCF8566TS PCF8566TS
PCF8566U PC8566-1
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates Block diagram
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates Pinning information
6.1 Pinning
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
6.2 Pin description
Table 3. Pin description
SDA 1 I2 C-bus data input and output
SCL 2 I2 C-bus clock input and output
SYNC 3 cascade synchronization input and output
CLK 4 external clock input and output
VDD 5 positive supply voltage[1]
OSC 6 oscillator select 7 I2 C-bus subaddress inputs 8 9
SA0 10 I2 C-bus slave address bit 0 input
VSS 11 logic ground
VLCD 12 LCD supply voltage
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
[1] The substrate (rear side of the die) is wired to VDD but should not be electrically connected. Functional description
The PCF8566 is a versatile peripheral device designed to interface any
microprocessoror microcontrollertoa wide varietyof LCDs.It can directly drive any static
or multiplexed LCD containing up to 4 backplanes and up to 24 segments.
The display conﬁgurations possible with the PCF8566 depend on the number of active
backplane outputs required. Display conﬁguration selection is shown in Table 4. All of the
display conﬁgurations givenin Table4 canbe implementedin the typical system shownin
Figure4.
The host microprocessor or microcontroller maintains the 2-line I2 C-bus communication
channel with the PCF8566.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (pins VDD, VSS and VLCD) and the LCD panel selected for the application.
BP0 13 LCD backplane outputs
BP2 14
BP1 15
BP3 16
S0 to S23 17 to 40 LCD segment outputs
Table 3. Pin description …continued
Table 4. Display conﬁgurations 96 12 12 6 12 96 (4 × 24)
372 99416 72 (3 × 24)
248 663648 (2 × 24)
124 33110 24
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.1 Power-on reset
At power-on the PCF8566 resets to the following starting conditions: All backplane outputs are set to VDD All segment outputs are set to VDD Drive mode 1:4 multiplex with1⁄3 bias is selected Blinking is switched off Input and output bank selectors are reset (as deﬁned in Table8) The I2 C-bus interface is initialized The data pointer and the subaddress counter are cleared
Do not transfer data on the I2 C-bus after a power-on for at least 1 ms to allow the reset
action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (Voper) is obtained from VDD− VLCD. The LCD voltage may be
temperature compensated externally through the VLCD supply to pin 12.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between VDD and VLCD. The center resistor can be
switched out of the circuit to provide a1 ⁄2 bias voltage level for the 1:2 multiplex
conﬁguration.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive conﬁguration. The operation of the voltage selector is controlled by
mode-set commands from the command decoder. The biasing conﬁgurations that applyto
the preferred modesof operation, together with the biasing characteristicsas functionsof
VLCD and the resulting discrimination ratios (D), are given in Table5.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
A practical value for VLCD is determined by equating Voff(RMS) with a deﬁned LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD >3Vth.
Multiplex drive modes of 1:3 and 1:4 with1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by , where the values for a are
a = 1 for 1 ⁄2 bias
a = 2 for1 ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with the equation
(1)
where VLCD is the resultant voltage at the LCD segment and where the values for n are= 1 for static mode= 2 for 1:2 multiplex= 3 for 1:3 multiplex= 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with the equation:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from the equation:
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with1⁄2 biasis
Table 5. Preferred LCD drive modes: summary of characteristics
static 1 2 static 0 1 ∞
1:2 multiplex 2 3 1⁄2 0.354 0.791 2.236
1:2 multiplex 2 4 1⁄3 0.333 0.745 2.236
1:3 multiplex 3 4 1⁄3 0.333 0.638 1.915
1:4 multiplex 4 4 1⁄3 0.333 0.577 1.732+-------------on RMS()LCD=off RMS()VLCD=on RMS()off RMS()------------------------= 1.732=
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates 1:4 multiplex with1⁄2 bias is
The advantageof these LCD drive modesisa reductionof the LCD full scale voltage VLCD
as follows: 1:3 multiplex (1 ⁄2 bias): 1:4 multiplex (1 ⁄2 bias):
These compare with when1 ⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.---------- 1.528= LCDoff RMS()× 2.449Voff RMS()== LCD 43× () ---------------------- 2.309Voff RMS()== LCD 3Voff RMS()=
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
Backplane and segment drive waveforms for this mode are shown in Figure5.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCF8566 allows the use of1⁄2 bias or1⁄3 bias (see Figure 6 and Figure 7).
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies as
shown in Figure8.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.4.4 1:4 multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure9.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.5 Oscillator
The internal logic and the LCD drive signals of the PCF8566 are timed by the frequency
fclk, which equals either the built-in oscillator frequency foscor the external clock frequency
fclk(ext).
The clock frequency (fclk) determines the LCD frame frequency (ffr) and the maximum rate
for data reception from theI2 C-bus.To allowI2 C-bus transmissionsat their maximum data
rate of 100 kHz, fclk should be chosen to be above 125 kHz.
7.5.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the
output from pin CLK is the clock signal for any cascaded PCF8566s or PCF8576s in the
system.
7.5.2 External clock
Connecting pin OSCto VDD enablesan external clock source. Pin CLK then becomes the
external clock input.
Remark: A clock signal must always be supplied to the device. Removing the clock,
freezes the LCD in a DC state.
7.6 Timing
The timing of the PCF8566 sequences the internal data ﬂow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the synchronization signal (SYNC) maintains the correct timing
relationship between the PCF8566s in the system. The timing also generates the LCD
frame frequency which is derived as an integer division of the clock frequency (see
Table 6). The frame frequencyis setby the mode set commands whenan internal clockis
used or by the frequency applied to the pin CLK when an external clock is used.
[1] The possible values for fclk see Table20.
[2] For fclk = 200 kHz.
[3] For fclk = 31 kHz.
The ratio between the clock frequency and the LCD frame frequency depends on the
modein which the deviceis operating.In the power-saving mode the reduction ratiois six
times smaller; this allows the clock frequency to be reduced by a factor of six. The
reduced clock frequency results in a signiﬁcant reduction in power dissipation.
Table 6. LCD frame frequencies[1]
normal mode 69[2]
power saving mode 65[3]frclk
2880-------------=frclk
480----------=
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
The lower clock frequency has the disadvantage of increasing the response time when
large amounts of display data are transmitted on the I2 C-bus. When a device is unable to
processa display data byte before the next one arrives,it holds the SCL line LOW until the
ﬁrst display data byte is stored. This slows down the transmission rate of the I2 C-bus but
no data loss occurs.
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. Thereisa one-to-one relationship between the datain the display register, the
LCD segment outputs and one column of the display RAM.
7.8 Shift register
The shift register transfers display information from the display RAMto the display register
while previous data is displayed.
7.9 Segment outputs
The LCD drive section includes 24 segment outputs S0to S23 which must be connected
directly to the LCD. The segment output signals are generated based on the multiplexed
backplane signals and with data resident in the display register. When less than segment outputs are required, the unused segment outputs shouldbe left open-circuit.
7.10 Backplane outputs
The LCD drive section includes four backplane outputs: BP0to BP3. The backplane
output signals are generated based on the selected LCD drive mode. In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required the unused outputs can be left as an
open-circuit. In 1:3 multiplex drive mode: BP3 carries the same signalas BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities. In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities. In static drive mode: the same signalis carriedbyall four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.11 Display RAM
The display RAMisa static24× 4-bit RAM which stores LCD data. Logic1in the RAMbit
map indicates the on-stateof the corresponding LCD segment; similarly, logic0 indicates
the off-state. There is a direct relationship between the RAM addresses and the segment
outputs, and between the individual bits of a RAM word and the backplane outputs. The
ﬁrst RAM row corresponds to the 24 segments operated with respect to backplane BP0
(see Figure 10). In multiplexed LCD applications, the segment data of rows 1 to 4 of the
display RAM are time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
When display datais transmittedto the PCF8566 the display bytes received are storedin
the display RAM based on the selected LCD drive mode. An example of a 7-segment
numeric display illustrating the storage order for all drive modes is shown in Figure 11.
The RAM storage organization applies equally to other LCD types.
The following applies to Figure 11: Static drive mode: the eight transmitted data bits are placed in row 0 to eight
successive display RAM addresses. 1:2 multiplex drive mode: the eight transmitted data bits are placed in row 0 and 1 to
four successive display RAM addresses. 1:3 multiplex drive mode: the eight transmitted data bits are placedin row0,1 and2of
three successive addresses, withbit2of the third address left unchanged. This lastbit
can, if necessary, be controlled by an additional transfer to this address but avoid
overriding adjacent data because always full bytes are transmitted. 1:4 multiplex drive mode: the eight transmitted data bits are placed in row 0, 1, 2 and
3 to two successive display RAM addresses.
7.12 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load data pointer command (see Table 13). After this, the data byte is
stored starting at the display RAM address indicated by the data pointer (see Figure 11).
Once each byte is stored, the data pointer is automatically incremented based on the
selected LCD conﬁguration.
The contents of the data pointer are incremented as follows: In static drive mode by eight. In 1:2 multiplex drive mode by four. In 1:3 multiplex drive mode by three. In 1:4 multiplex drive mode by two.
If an I2 C-bus data access terminates early, the state of the data pointer is unknown.
Consequently, the data pointer must be rewritten prior to further RAM accesses.
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NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
7.13 Sub-address counter
The storage of display data is conditioned by the contents of the subaddress counter.
Storageis allowedto take place only when the contentsof the subaddress counter match
with the hardware subaddress appliedto A0, A1 and A2. The subaddress counter valueis
deﬁned by the device select command (see Table 14 and Table 21). If the contents of the
subaddress counter and the hardware subaddress do not match then data storage is
blocked but the data pointer will be incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overﬂows.
The storage arrangements described leadto extremely efﬁcient data loadingin cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF8566 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
7.14 Output bank selector
The output bank selector (see Table 15), selects one of the four bits per display RAM
address for transfer to the display register. The actual bit selected depends on the LCD
drive mode in operation and on the instant in the multiplex sequence. In 1:4 multiplex mode: all RAM addresses of bit 0 are selected, followed sequentially
by the contents of bit1,bit 2 and then bit3. In 1:3 multiplex mode: bits0,1 and 2 are selected sequentially. In 1:2 multiplex mode: bits0 and 1 are selected. In the static mode: bit 0 is selected.
The PCF8566 includesa RAM bank switching featurein the static and 1:2 multiplex drive
modes. In the static drive mode, the bank select command may request the contents of
bit2tobe selectedfor display insteadof the contentsofbit0.In 1:2 multiplex drive mode,
the contents of bits2 and 3 may be selected instead of bits0 and 1. This enables
preparationof display informationinan alternative bank and the abilityto switchtoit once
it has been assembled.
7.15 Input bank selector
The input bank selector loads display data into the display RAM based on the selected
LCD drive conﬁguration. Using the bank select command, display data can be loaded in
bit2 into static drive modeorin bits2 and3 into 1:2 multiplex drive mode. The input bank
selector functions independently of the output bank selector.
7.16 Blinker
The display blinking capabilitiesof the PCF8566 are very versatile. The whole display can
be blinked at frequencies selected by the blink command. The blinking frequencies are
integer fractions of the clock frequency; the ratios between the clock and blinking
frequencies depend on the mode in which the device is operating (see Table7).
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
An additional feature is for an arbitrary selection of LCD segments to be blinked. This
applies to the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. Using the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blinking frequency. This mode can also be
speciﬁed by the blink select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can be blinked by selectively changing the display RAM data at ﬁxed time
intervals.
If the entire display needs to be blinked at a frequency other than the nominal blinking
frequency, this can be done using the mode set command to set and reset the display
enable bit E at the required rate (seeT able9). Basic architecture
8.1 Characteristics of the I2 C-bus
The I2 C-bus provides bidirectional, two-line communication between different IC or
modules. The two lines area Serial Data line (SDA) anda Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
8.1.1 Bit transfer
One databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH periodof the clock pulse. Changesin the data lineat this time will
be interpreted as a control signal. Bit transfer is illustrated in Figure 12.
Table 7. Blink frequencies
off - - blinking off 2 Hz 1 Hz 0.5 Hz blinkclk
92160----------------= f blinkelk
15360----------------= blinkclk
184320--------------------= f blinkclk
30720----------------= blinkclk
368640--------------------= f blinkclk
61440----------------=
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
8.1.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the busis not busy.A HIGH-to-LOW change
of the data line, while the clock is HIGH, is deﬁned as the START condition (S). LOW-to-HIGH change of the data line, while the clock is HIGH, is deﬁned as the STOP
condition (P). The START and STOP conditions are illustrated in Figure 13.
8.1.2 System conﬁguration
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system conﬁguration is illustrated in
Figure 14.
8.1.3 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during
which time the master generates an extra acknowledge related clock pulse. (See
Figure 15).
Acknowledgement on the I2 C-bus is illustrated in A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.A master receiver must generatean acknowledge after the receptionof each byte that
has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates A master receiver must signal an end-of-data to the transmitter by not generating an
acknowledgeon the last byte that has been clocked outof the slave.In this event, the
master receiver must leave the data line HIGH during the 9th pulse to not
acknowledge. The master will now generate a STOP condition.
8.1.4 PCF8566 I2 C-bus controller
The PCF8566 acts as an I2 C-bus slave receiver. It does not initiate I2 C-bus transfers or
transmit data to an I2 C-bus master receiver. The only data output from the PCF8566 are
the acknowledge signals of the selected devices. Device selection depends on the2 C-bus slave address, the transferred command data and the hardware subaddress.
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which deﬁnes the hardware subaddress 0. In multiple device applications
A0, A1 and A2 are tied to VSS or VDD using a binary coding scheme so that no two
devices with a common I2 C-bus slave address have the same hardware subaddress.
In the power-saving mode it is possible that the PCF8566 is not able to keep up with the
highest transmission rates when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW until its internal operations are
completed. This is known as the clock synchronization feature of the I2 C-bus and serves
to slow down fast transmitters. Data loss does not occur.
8.1.5 Input ﬁlter
To enhance noise immunity in electrically adverse environments, RC low-pass ﬁlters are
provided on the SDA and SCL lines.
8.2I2 C-bus protocol
Two I2 C-bus 7 bit slave addresses (0111 110 and 0111 111) are reserved for the
PCF8566. The least signiﬁcant bit after the slave address is bit R/W. The PCF8566 is a
write-only device.It will not respondtoa read access,so thisbit should alwaysbe logic0.
The second bit of the slave address is deﬁned by the level tied at input SA0.
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
Two displays controlled by PCF8566 can be recognized on the same I2 C-bus which
allows: Up to 16 PCF8566s on the same I2 C-bus for very large LCD applications (see
Section 13) The use of two types of LCD multiplex on the same I2 C-bus
The I2 C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2 C-bus master which is followed by one of the PCF8566 slave
addresses. All PCF8566s with the same SA0 level acknowledge in parallel to the slave
address. All PCF8566s with the alternative SA0 level ignore the whole I2 C-bus transfer.
After acknowledgement, oneor more command bytes (m) follow which deﬁne the statusof
the addressed PCF8566s. The last command byte is tagged with a cleared most
signiﬁcant bit, the continuation bit C. The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes (n) may follow. These display
bytes are stored in the display RAM at the address speciﬁed by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data is directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8566. After the last display byte, the I2 C-bus master issues a STOP condition (P).
NXP Semiconductors PCF8566
Universal LCD driver for low multiplex rates
8.3 Command decoder
The command decoder identiﬁes command bytes that arrive on the I2 C-bus. All available
commands carry a continuation bit C in their most signiﬁcant bit position as shown in
Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will
also representa command.If thisbitis reset,it indicates that the command byteis the last
in the transfer. Further bytes will be regarded as display data.
The ﬁve commands available to the PCF8566 are deﬁned in Table8.
8.3.1 Mode set command
Table 8. Deﬁnition of PCF8566 commands
Mode set C 1 0 LP E B M1 M0 Section 8.3.1 deﬁnes LCD drive mode, LCD bias
conﬁguration, display status and
power dissipation mode
Load data
pointer 0 0 P4P3P2P1P0 Section 8.3.2 data pointer to deﬁne oneof24
display RAM addresses
Device select C 1100A2 A1 A0 Section 8.3.3 deﬁne oneof eight hardware
subaddresses
Bank select C 11110I O Section 8.3.4 bit I: deﬁnes input bank selection
(storage of arriving display data);
bit O: deﬁnes output bank selection
(retrieval of LCD display data)
Blink C 1110A BF1 BF0 Section 8.3.5 deﬁnesthe blink frequency and blink
mode
Table 9. LCD drive mode command bit description
static BP0 0 1
1:2 BP0, BP1 1 0
1:3 BP0, BP1. BP2 1 1
1:4 BP0, BP1. BP2, BP3 0 0

Partno	Mfg	Dc	Qty	Available	Descript
PCF8566T	NXP	N/a	2500	avai	Universal LCD driver for low multiplex rates