PCF2113DH ,LCD controller/driverFEATURES • MUX rates 1 : 18 (for normal operation) and 1 : 2(for icon-only mode)• Single-chip LCD c ..
PCF2113DH ,LCD controller/driverLIMITING VALUES8.8 Registers14 HANDLING8.9 Busy Flag15 DC CHARACTERISTICS8.10 Address Counter (AC)1 ..
PCF2113DH ,LCD controller/driverFeaturesn Single-chip LCD controller/drivern 2-line display of up to 12 characters + 120 icons, or ..
PCF2113DH/F4 ,LCD controllers/drivers
PCF2113DU/F2 ,LCD controller/driverapplicationsingle chip, including on-chip generation of LCD bias2• 4 or 8-bit parallel bus and 2-wi ..
PCF2113DU/F4 ,PCF2113x; LCD controllers/drivers
PGA205BU ,Programmable Gain INSTRUMENTATION AMPLIFIERFEATURES DESCRIPTIONThe PGA204 and PGA205 are low cost, general pur-l DIGITALLY PROGRAMMABLE GAIN:p ..
PGA206PA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA206UA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA206UAG4 ,High-Speed Programmable Gain Instrumentation Amplifier 16-SOIC PGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA207UA ,High-Speed Programmable Gain INSTRUMENTATION AMPLIFIERPGA207PGA206®PGA206PGA207High-Speed Programmable GainINSTRUMENTATION AMPLIFIER
PGA207UAE4 ,High-Speed Programmable Gain Instrumentation Amplifier 16-SOIC FEATURES DESCRIPTIONThe PGA206 and PGA207 are digitally programmablel DIGITALLY PROGRAMMABLE GAINS: ..
PCF2113DH
LCD controllers/drivers
General descriptionThe PCF2113x is a low-power CMOS LCD controller and driver, designed to drive a dot
matrix LCD display of 2 lines of 12 characters or 1 line of 24 characters with 5×8 dot
format. All necessary functions for the display are provided in a single chip, including
on-chip generation of LCD bias voltages, resulting in a minimum of external components
and lower system current consumption. The PCF2113x interfaces to most
microcontrollers via a 4-bitor 8-bit bus or via the 2-wire I2 C-bus. The chip contains a
character generator and displays alphanumeric and kana (Japanese) characters.
The letter ‘x’ in PCF2113x characterizes the built-in character set. Various character sets
can be manufactured on request.
Features Single-chip LCD controller/driver 2-line display of up to 12 characters+ 120 icons, or 1-line display of up to characters+ 120 icons5×7 character format plus cursor; 5× 8 for kana (Japanese) and user-defined
symbols Icon mode for e.g. additional segment display section: reduced current consumption
while displaying icons only Icon blink function Very low current consumption (20 μAto200 μA): Icon mode: < 25 μA Power-down mode: < 2 μA On-chip: Configurable 4,3or 2 voltage multiplier, generating LCD supply voltage VLCD,
independent of VDD, programmable by instruction (external supply also possible) Temperature compensation of on-chip generated VLCD: −0.16 %/Kto −0.24 %/K
(programmable by instruction) Generation of intermediate LCD bias voltages Oscillator requires no external components (external clock also possible) Display data RAM: 80 characters Character generator ROM: 240 characters of 5×8 dots Character generator RAM: 16 characters of 5×8 dots; 3 characters used to drive
120 icons, 6 characters used if icon blink feature is used in application 4-bitor 8-bit parallel bus and 2-wire I2 C-bus interface 18 row and 60 column outputs
PCF2113x
LCD controllers/drivers
Rev. 04 — 4 March 2008 Product data sheet
NXP Semiconductors PCF2113x
LCD controllers/drivers Multiplex rates (MUX) 1:18 (for normal operation), 1:9 (for single-line operation) and
1:2 (for Icon-only mode) Uses common 11 code instruction set (extended) Logic supply voltage range VDD1− VSS1= 1.8 V to 5.5 V (chip may be driven with two
battery cells) VLCD generator supply voltage range VDD2− VSS2= 2.2 V to 4.0V Display supply voltage range VLCD− VSS2= 2.2 V to 6.5V Direct mode to save current consumption for Icon mode and MUX 1:9 (depending on
VDD2 and LCD liquid properties) CMOS compatible
Remark: Icon modeisa wayto save current. When only icons are displayed (i.e. only
the lower two rows are active), a much lower operating voltage VLCD can be used and
the switching frequency of the LCD outputs is reduced. In most applications it is
possible to use VDD as VLCD.
Applications Telecom equipment Point-of-sale terminals Portable instruments
Ordering information Marking
Table 1. Ordering informationPCF2113AU/10/F4- chip on flexible film carrier -
PCF2113DU/F4 - chip in tray -
PCF2113DH/4 LQFP100 plastic low profile quadflat package; 100 leads;
body14×14× 1.4 mm
SOT407-1
PCF2113DU/2/F4 - chip with bumps in tray -
PCF2113EU/2/F4 - chip with bumps in tray -
PCF2113WU/2/F4- chip with bumps in tray -
Table 2. Marking codesPCF2113DH/4 PCF2113DH
NXP Semiconductors PCF2113x
LCD controllers/drivers Block diagram
NXP Semiconductors PCF2113x
LCD controllers/drivers Pinning information
7.1 Pinning
NXP Semiconductors PCF2113x
LCD controllers/drivers
Table 3. Pin (LQFP100 package) or pad allocation table
NXP Semiconductors PCF2113x
LCD controllers/drivers[1] Fab 1 identification starts with nnnnnn, where n represents a number between 0 and 9 (8 inch wafer).
[2] Fab2 identification starts with AXnnnn,where Xrepresentsa letterora number andn representsa number
between 0 and 9 (6 inch wafer).
Table 4. Bonding pad dimensionsType galvanic pure Au
Bump dimensions (50 ± 6)× (90 ± 6)× (17.5 ± 5) μm
Height difference in one die < 2 μm
Convex deformation < 5 μm
Pad size (aluminium) 62× 100 μm
Passivation opening 36×76 μm
Pad pitch −635.0 μm
Wafer thickness (excluding bumps) 380±25 μm
Fab 1[1] Fab 2[2]Die size X 3.52 3.47 mm
Die size Y 3.36 3.31 mm
Table 3. Pin (LQFP100 package) or pad allocation table …continued
Table 5. Pin and bonding pad descriptionAll x/y coordinates represent the position of the center of each pad with respect to the center (x/y= 0) of the chip (see
Figure3).
VDD1 1P 1 −1345 −1550 supply voltage 1 for all except VLCD
generator
OSC 2 I 2 −1155 −1550 oscillator and external clock input [1] 3 I 3 −1055 −1550 power-down select input; for normal
operation PD is LOW - I 4 −845 −1550 test pad; open circuit and not user
accessible 4 I 5 −765 −1550 test pin; must be connected to VSS1 - I 6 −665 −1550 test pad; must be connected to VSS1
VSS1 5P 7 −525 −1550 ground 1 for all except VLCD generator
NXP Semiconductors PCF2113x
LCD controllers/driversVSS2 6P 8 −455 −1550 ground 2 for VLCD generator
VLCDOUT 7O 9 −295 −1550 VLCD output if VLCD is generated internally [2]
VLCDSENSE -I 10 −145 −1550 input (VLCD) for voltage multiplier regulation [2][3]
VLCDIN 8 I 11 15 −1550 input for generation of LCD bias levels [2] 9 O 12 175 −1550 LCD row driver output
R10 10 O 13 245 −1550 LCD row driver output
R11 11 O 14 315 −1550 LCD row driver output
R12 12 O 15 385 −1550 LCD row driver output
R13 13 O 16 455 −1550 LCD row driver output
R14 14 O 17 525 −1550 LCD row driver output
R15 15 O 18 595 −1550 LCD row driver output
R16 16 O 19 665 −1550 LCD row driver output
R18 17 O 20 735 −1550 LCD row driver output
C60 18 O 21 805 −1550 LCD column driver output
C59 19 O 22 875 −1550 LCD column driver output
C58 20 O 23 995 −1550 LCD column driver output
C57 21 O 24 1065 −1550 LCD column driver output
C56 22 O 25 1135 −1550 LCD column driver output
C55 23 O 26 1205 −1550 LCD column driver output
C54 24 O 27 1275 −1550 LCD column driver output
C53 25 O 28 1345 −1550 LCD column driver output
dummy pad1 - - 29 1435 −1550 -
dummy pad2 - - 30 1630 −1395 -
C52 26 O 31 1630 −1255 LCD column driver output
C51 27 O 32 1630 −1155 LCD column driver output
C50 28 O 33 1630 −1055 LCD column driver output
C49 29 O 34 1630 −955 LCD column driver output
C48 30 O 35 1630 −735 LCD column driver output
C47 31 O 36 1630 −635 LCD column driver output
C46 32 O 37 1630 −535 LCD column driver output
C45 33 O 38 1630 −435 LCD column driver output
C44 34 O 39 1630 −335 LCD column driver output
C43 35 O 40 1630 −235 LCD column driver output
C42 36 O 41 1630 −135 LCD column driver output
C41 37 O 42 1630 −35 LCD column driver output
C40 38 O 43 1630 65 LCD column driver output
C39 39 O 44 1630 165 LCD column driver output
C38 40 O 45 1630 265 LCD column driver output
C37 41 O 46 1630 365 LCD column driver output
Table 5. Pin and bonding pad description …continuedAll x/y coordinates represent the position of the center of each pad with respect to the center (x/y= 0) of the chip (see
Figure3).
NXP Semiconductors PCF2113x
LCD controllers/driversC36 42 O 47 1630 465 LCD column driver output
C35 43 O 48 1630 565 LCD column driver output
C34 44 O 49 1630 665 LCD column driver output
C33 45 O 50 1630 765 LCD column driver output
C32 46 O 51 1630 865 LCD column driver output
C31 47 O 52 1630 965 LCD column driver output
C30 48 O 53 1630 1065 LCD column driver output
C29 49 O 54 1630 1165 LCD column driver output
C28 50 O 55 1630 1265 LCD column driver output
dummy pad3 - - 56 1630 1335 -
dummy pad4 - - 57 1435 1550 -
C27 51 O 58 1335 1550 LCD column driver output
C26 52 O 59 1225 1550 LCD column driver output
C25 53 O 60 1115 1550 LCD column driver output
C24 54 O 61 1005 1550 LCD column driver output
C23 55 O 62 765 1550 LCD column driver output
C22 56 O 63 665 1550 LCD column driver output
C21 57 O 64 565 1550 LCD column driver output
C20 58 O 65 465 1550 LCD column driver output
C19 59 O 66 365 1550 LCD column driver output
C18 60 O 67 265 1550 LCD column driver output
C17 61 O 68 165 1550 LCD column driver output
C16 62 O 69 65 1550 LCD column driver output
C15 63 O 70 −35 1550 LCD column driver output
C14 64 O 71 −135 1550 LCD column driver output
C13 65 O 72 −235 1550 LCD column driver output
C12 66 O 73 −335 1550 LCD column driver output
C11 67 O 74 −435 1550 LCD column driver output
C10 68 O 75 −535 1550 LCD column driver output 69 O 76 −635 1550 LCD column driver output 70 O 77 −735 1550 LCD column driver output 71 O 78 −835 1550 LCD column driver output 72 O 79 −965 1550 LCD column driver output 73 O 80 −1065 1550 LCD column driver output 74 O 81 −1165 1550 LCD column driver output 75 O 82 −1265 1550 LCD column driver output
dummy pad5 - - 83 −1465 1550 -
dummy pad6 - - 84 −1630 1355 - 76 O 85 −1630 1255 LCD column driver output
Table 5. Pin and bonding pad description …continuedAll x/y coordinates represent the position of the center of each pad with respect to the center (x/y= 0) of the chip (see
Figure3).
NXP Semiconductors PCF2113x
LCD controllers/drivers[1] When the on-chip oscillator is used this pad must be connected to VDD1.
[2] When VLCD is generated internally, pins VLCDIN, VLCDOUT and VLCDSENSE must be connected together. When an external VLCD is
supplied, this should be done via VLCDIN. In this case only pins VLCDOUT and VLCDSENSE must be connected together.
[3] In the LQFP100 version this signal is connected internally and is not accessible.
[4] When the I2C-bus is used, the parallel interface pin E must be LOW. In the I2C-bus read mode pins DB7 to DB0 must be connected to
VDD1 or left open-circuit.
When the parallel bus is used, the pins SCL and SDA must be connected to pin VSS1 or pin VDD1; they must not be left open-circuit.
Whenthe 4-bit interfaceis used without readingout fromthe PCF2113x(bit R/Wisset permanentlyto logic0),the unused ports DB0to
DB3 can either be connected to VSS1 or VDD1 instead of leaving them open-circuit.
[5] DB7 may be used as the busy flag, signalling that internal operations are not yet completed. In 4-bit operations the four higher order
lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit except for I2C-bus operations (see Table note4).
[6] VDD2 and VDD3 must always be equal. 77 O 86 −1630 1185 LCD column driver output 78 O 87 −1630 1115 LCD row driver output 79 O 88 −1630 1045 LCD row driver output 80 O 89 −1630 975 LCD row driver output 81 O 90 −1630 905 LCD row driver output 82 O 91 −1630 835 LCD row driver output 83 O 92 −1630 765 LCD row driver output 84 O 93 −1630 695 LCD row driver output 85 O 94 −1630 625 LCD row driver output
R17 86 O 95 −1630 555 LCD row driver output
SCL 87 I 96 −1630 375 I2 C-bus serial clock input [4]
SDA 88 I/O 97 −1630 305 I2 C-bus serial data input/output [4]
E89 I 98 −1630 85 data bus clock input [4] 90 I 99 −1630 −15 register select input
R/W 91 I 100 −1630 −115 read or write input
DB7 92 I/O 101 −1630 −215 8-bit bidirectional bus bit 7 [5]
DB6 93 I/O 102 −1630 −315 8-bit bidirectional bus bit 6
DB5 94 I/O 103 −1630 −415 8-bit bidirectional bus bit 5
DB4 95 I/O 104 −1630 −515 8-bit bidirectional bus bit 4
DB3/SA0 96 I/O 105 −1630 −615 8-bit bidirectional bus bit 3 or I2 C-bus
address input
[4][5]
DB2 97 I/O 106 −1630 −715 8-bit bidirectional bus bit 2
DB1 98 I/O 107 −1630 −815 8-bit bidirectional bus bit 1
DB0 99 I/O 108 −1630 −915 8-bit bidirectional bus bit 0
VDD2 100 P 109 −1630 −1015 supply voltage 2 for VLCD generator [6]
VDD3 - P 110 −1630 −1235 supply voltage 3 for VLCD generator [3][6]
dummy pad7 - - 111 −1630 −1395 -
dummy pad8 - - 112 −1465 −1550 -
Table 5. Pin and bonding pad description …continuedAll x/y coordinates represent the position of the center of each pad with respect to the center (x/y= 0) of the chip (see
Figure3).
NXP Semiconductors PCF2113x
LCD controllers/drivers Functional description
8.1 LCD supply voltage generatorThe LCD supply voltage (VLCD) may be generated on-chip. The VLCD generator is
controlled by two internal 6-bit registers: VA and VB. Section 10.10.1 shows how to
program these registers. The nominal LCD operating voltageat room temperatureis given
by the relationship:
Voper(nom)= (integer value of register× 0.08 V)+ 1.82V
With a programmed value from 1to 63, Voper(nom)= 1.90 V to 6.86 V at Tamb =27 °C.
Values producing more than 6.5 V at operating temperature are not allowed. Operation
above this voltage may damage the device. When programming the operating voltage the
VLCD tolerance and temperature coefficient must be taken into account.
Values below 2.2 V are below the specified operating range of the chip and therefore are
not allowed.
Value0for VA and VB switchesoff the generator (i.e. VA=0in Character mode, VB=0in
Icon mode).
Usually register VA is programmed with the voltage for Character mode and register VB
with the voltage for Icon mode.
When VLCD is generated on-chip, the VLCD pins must be decoupled to VSS with a suitable
capacitor.
The generated VLCD is independent of VDD and is temperature compensated. When the
VLCD generator and the Direct mode are switched off,an external voltage maybe supplied
at pins VLCDIN and VLCDOUT (which are connected together). VLCDIN and VLCDOUT may be
higher or lower than VDD2.
During Direct mode (program DM bit) the internal VLCD generator is turned off and the
VLCDOUT output voltage is directly connected to VDD2. This reduces the current
consumption during Icon mode and MUX 1:9 (depending on VDD2 and LCD liquid
properties).
The VLCD generator ensures that, as long as VDD is in the valid range (2.2 V to4 V), the
required peak operating voltage of 6.5 V can be generated at any time.
8.2 LCD bias voltage generatorThe intermediate bias voltages for the LCD display are also generated on-chip. This
removes the needforan external resistive bias chain and significantly reduces the system
current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD
threshold voltage (Vth) and the numberof bias levels. Usinga 5-level bias schemefor 1:18
maximum rate allows VLCD<5Vfor most LCD liquids. The intermediate bias levelsfor the
different multiplex rates are shown in Table 6. These bias levels are automatically set to
the given values when switching to the corresponding multiplex rate.
NXP Semiconductors PCF2113x
LCD controllers/drivers[1] The values in the table are given relative to VLCD− VSS, e.g.3⁄4 means {3⁄4× (VLCD− VSS)}+ VSS.
8.3 OscillatorThe on-chip oscillator provides the clock signal for the display system. No external
components are required and the OSC pin must be connected to VDD1.
8.4 External clockIf an external clock is to be used, this input is at the OSC pin. The resulting display frame
frequency is given by:
Only in the Power-down mode is the clock allowed to be stopped (pin OSC connected to
VSS), otherwise the LCD is frozen in a DC state.
8.5 Power-on resetThe on-chip power-on reset block initializes the chip after power-on or power failure. This
is a synchronous reset and requires 3 oscillator cycles to be executed.
8.6 RegistersThe PCF2113x has two 8-bit registers: an Instruction Register (IR) and a Data
Register (DR). The Register Select (RS) signal determines which register will be
accessed. The instruction register stores instruction codes suchas ‘display clear’, ‘cursor
shift’, and address information for the Display Data RAM (DDRAM) and Character
Generator RAM (CGRAM). The instruction register can be written to but not read from by
the system controller.
The data register temporarily stores datatobe read from the DDRAM and CGRAM. When
reading, data from the DDRAMor CGRAM correspondingto the addressin the instruction
register is written to the data register prior to being read by the ‘read data’ instruction.
8.7 Busy flagThe busy flag indicates the internal status of the PCF2113x. A logic 1 indicates that the
chip is busy and further instructions will not be accepted. The busy flag is output to
pin DB7 whenbit RS=0 andbit R/W=1. Instructions must onlybe written after checking
that the busy flag is at logic 0 or waiting for the required number of cycles.
Table 6. Bias levels as a function of multiplex rate1:18 5 VLCD 3⁄4 1⁄2 1⁄2 1⁄4 VSS
1:9 5 VLCD 3⁄4 1⁄2 1⁄2 1⁄4 VSS
1:2 4 VLCD 2⁄3 2⁄3 1⁄3 1⁄3 VSSfr LCD()osc
3072------------=
NXP Semiconductors PCF2113x
LCD controllers/drivers
8.8 Address counterThe Address Counter (AC) assigns addresses to the DDRAM and CGRAM for reading
and writing andis setby the commands ‘set DDRAM address’ and ‘set CGRAM address’.
After a read/write operation the address counter is automatically incremented or
decremented by 1. The address counter contents are output to the bus (DB6to DB0)
when bit RS= 0 and bit R/W=1.
8.9 Display data RAMThe Display Data RAM (DDRAM) stores up to 80 characters of display data represented 8-bit character codes. RAM locations which are not usedfor storing display data canbe
usedas general purpose RAM. The basic RAMto display addressing schemeis shownin
Figure4. Withno display shift the characters representedby the codesin the first24 RAM
locations starting at address 00h in line 1 are displayed. Figure 5 and Figure6 show the
display mapping for right and left shift respectively.
When datais writtentoor read from the DDRAM, wrap-around occurs from the endof one
line to the start of the next line. When the display is shifted each line wraps around within
itself, independentlyof the others. Thusall lines are shifted and wrapped around together.
The address ranges and wrap-around operations for the various modes are shown in
Table7.
NXP Semiconductors PCF2113x
LCD controllers/drivers
8.10 Character generator ROMThe Character Generator ROM (CGROM) generates 240 character patternsina5×8 dot
format from 8-bit character codes. Figure7, Figure8, Figure 9 and Figure10 show the
character sets that are currently implemented.
Table 7. Address space and wrap-around operationAddress space 00h to 4Fh 00h to 27h; 40h to 67h 00h to 27h
Read/write wrap-around
(moves to next line)
4Fh to 00h 27h to 40h; 67h to 00h 27h to 00h
Display shift wrap-around
(stays within line)
4Fh to 00h 27h to 00h; 67h to 40h 27h to 00h
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
8.11 Character generator RAMUp to 16 user-defined characters may be stored in the Character Generator RAM
(CGRAM). Some CGRAM characters (see Figure18 and Figure 19) are also usedto drive
icons(6if icons blink and both icon rows are usedin the application;3ifno blink but both
icon rows are used in the application; 0 if no icons are driven by the icon rows). The
CGROM and CGRAM usea common address space,of which the first columnis reserved
for the CGRAM (see Figure7, Figure8, Figure 9 and Figure 10).
Figure11 shows the addressing principle for the CGRAM.
8.12 Cursor control circuitThe cursor control circuit generates the cursor underline and/or cursor blink as shown in
Figure 12 at the DDRAM address contained in the address counter.
When the address counter contains the CGRAM address the cursor will be inhibited.
NXP Semiconductors PCF2113x
LCD controllers/drivers
8.13 Timing generatorThe timing generator produces the various signals required to drive the internal circuitry.
Internal chip operation is not disturbed by operations on the data buses.
8.14 LCD row and column driversThe PCF2113x contains 18 row and 60 column drivers, which connect the appropriate
LCD bias voltagesin sequenceto the displayin accordance with the datatobe displayed.
R17 and R18 drive the icon rows.
The bias voltages and the timing are selected automatically when the number of lines in
the display is selected. Figure 14, Figure 15, Figure 16 and Figure17 show typical
waveforms. Unused outputs should be left unconnected.
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
NXP Semiconductors PCF2113x
LCD controllers/drivers
8.15 Power-down modeThe chip can be put into Power-down mode by applying an external HIGH level to the pin. In Power-down mode all static currents are switched off (no internal oscillator, no
bias level generation and all LCD outputs are internally connected to VSS).
During power-down, informationin the RAMs and the chip state are preserved. Instruction
execution during power-down is possible when pin OSC is externally clocked.
8.16 Reset functionThe PCF2113x automatically initializes (resets) when power is turned on. The chip
executesa reset sequence, includinga ‘clear display’, requiring 165 oscillator cycles. After
the reset the chip has the state shown in Table8.
NXP Semiconductors PCF2113x
LCD controllers/drivers InstructionsOnly two PCF2113x registers, the Instruction Register (IR) and the Data Register (DR),
can be directly controlled by the microcontroller. Before internal operation, control
information is stored temporarily in these registers to allow interfacing to various types of
microcontrollers which operate at different speeds or to allow interfacing to peripheral
control ICs.
The instruction set for I2 C-bus commands is given in Table9. Section 11.2.1 discusses
how these control and command bytes are embedded in the I2 C-bus protocol.
[1] R/W is set together with the slave address.
[2] For explanation, see Table11.
The PCF2113x operationis controlledby the instructions showninT able10 together with
their execution time. Details are explained in subsequent sections.
Table 8. State after reset clear display entry mode set I/D = 1 +1 (increment)
S = 0 no shift display control D = 0 display off
C = 0 cursor off
B = 0 cursor character blink off function set DL = 1 8-bit interface
M = 0 1-line display
H = 0 normal instruction set
SL = 0 MUX 1:18 mode default address pointer
to DDRAM
the Busy Flag (BF) indicates
the busy state (BF= 1) until
initialization ends
the busy state lasts 2 ms; the chip
may alsobe initializedby software;
see Table 26 (8-bit interface) and
Table 27 (4-bit interface). icon control IM = 0; IB = 0; DM = 0 icons, icon blink and Direct mode
disabled display or screen
configuration
L = 0; P = 0; Q = 0 default configurations
8VLCD temperature
coefficient
TC1 = 0; TC2 = 0 default temperature coefficient set VLCD VA = 0; VB = 0 VLCD generator off I2 C-bus interface reset set HVgen stages S1 = 1; S0 = 0 VLCD generator voltage multiplier
set at factor4
Table 9. Instruction set for I2 C-bus commands[1] Co[2] RS 000000 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 [1]
NXP Semiconductors PCF2113x
LCD controllers/driversThere are 4 types of instructions:
Designate PCF2113x functions such as display format, data length
Set internal RAM addresses
Perform data transfer with internal RAM
Other functions
In normal use, data transfer instructions are used most frequently. However, automatic
incrementingby1 (or decrementingby1)of internal RAM addresses after each data write
lessens the microcontroller program load. The display shiftin particular canbe performed
concurrently with display data write, enabling the designerto develop systemsin minimum
time with maximum programming efficiency.
During internal operation, no instructions other than the ‘read busy flag’ and ‘read
address’ instructions will be executed. Because the busy flag is set to logic 1 while an
instruction is being executed, check to ensure it is logic 0 before sending the next
instruction or wait for the maximum instruction execution time, as given in Table 10. An
instruction sent while the busy flag is logic 1 will not be executed.
Table 10. Instruction set with parallel bus commands
H = 0 or 1 (basic and extended functions)
H = 0 (basic functions)
NXP Semiconductors PCF2113x
LCD controllers/drivers[1] For explanation of symbols, see Table11.
H = 1 (extended functions)
Table 10. Instruction set with parallel bus commands …continued
NXP Semiconductors PCF2113x
LCD controllers/drivers
9.1 Clear display‘Clear display’ writes character code 20h intoall DDRAM addresses (the character pattern
for character code 20h must be a blank pattern), sets the DDRAM address counter to0
and returns the display to its original position, if it was shifted. Thus, the display
disappears and the cursoror blink position goesto the left edgeof the display. Sets entry
mode I/D= 1 (increment mode). S of entry mode does not change.
The instruction ‘clear display’ requires extra execution time. This may be allowed by
checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed.
The latter must be applied where no read-back options are foreseen, as in some
Chip-On-Glass (COG) applications.
Table 11. Explanation of symbols last control byte another control byte follows after
data/command select instruction register select data register data length: 4 bits data length: 8 bits
M (no impact if SL=1) 1 line × 24 character display 2 line × 12 character display MUX 1:18 (1 line×24 character
or 2 line×12 character display)
MUX 1:9 (1 line×12 character
display) use basic instruction set use extended instruction set
I/D decrement increment display freeze display shift display off display on cursor off cursor on cursor character blink off;
character at cursor position does
not blink
cursor character blink on;
characterat cursor position blinks
S/C cursor move display shift
R/L left shift right shift
L (no impact if M= 1 or=1)
left/right screen;
standard connection
left/right screen;
mirrored connectionst 12 characters of 24;
columns are from 1to60st 12 characters of 24;
columns are from 60to1nd 12 characters of 24;
columns are from 1to60nd 12 characters of 24;
columns are from 60to1 column data; left to right; column
data is displayed from 1to60
column data; right to left; column
data is displayed from 60to1 row data; topto bottom; row data displayed from1to16 and icon
row data is in 17 and 18
row data; topto bottom; row data displayed from16to1 and icon
row data is in 18 and 17 Character mode; full display Icon mode; only icons displayed icon blink disabled icon blink enabled Direct mode disabled Direct mode enabled set VA set VB
NXP Semiconductors PCF2113x
LCD controllers/drivers
9.2 Return home‘Return home’ sets the DDRAM address counterto0 and returns the displaytoits original
position if it was shifted. DDRAM contents do not change. The cursor or blink position
goes to the left of the first display line. I/D and S of entry mode do not change.
9.3 Entry mode set
9.3.1 Bit I/DWhen I/D=1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when
data is written into or read from the DDRAM or CGRAM. The cursor or blink position
moves to the right when incremented and to the left when decremented. The cursor
underline and cursor character blink are inhibited when the CGRAM is accessed.
9.3.2 Bit SWhen S= 1, the entire display shifts either to the right (I/D= 0) or to the left (I/D=1)
duringa DDRAM write. Thusit appearsasif the cursor stands still and the display moves.
The display does not shift when reading from the DDRAM, or when writing to or reading
from the CGRAM.
When S= 0, the display does not shift.
9.4 Display control (and partial Power-down mode)
9.4.1 Bit DThe display is on when D= 1 and off when D= 0. Display data in the DDRAM is not
affected and can be displayed immediately by settingD=1.
When the display is off (D= 0) the chip is in partial Power-down mode:
The LCD outputs are connected to VSS
The LCD generator and bias generator are turned off
Three oscillator cycles are required after sending the ‘display off’ instruction to ensure all
outputs are at VSS, afterwards the oscillator can be stopped. If the oscillator is running
during partial Power-down mode (‘display off’) the chip can still execute instructions. Even
lower current consumption is obtained by inhibiting the oscillator (pin OSC= VSS).
To ensure IDD<1 μA, pin PD and the parallel bus pins DB7to DB0 should be connected VDD, pins RS and R/W to VDD or left open-circuit.
Recovery from Power-down mode: connect pin PD back to VSS, if necessary pin OSC
back to VDD and send a ‘display control’ instruction with D=1.
9.4.2 Bit CThe cursor is displayed when C= 1 and inhibited when C= 0. The cursor is displayed
using 5 dots in the 8th line (see Figure 12). Even if the cursor disappears, the display
functions like I/D, remain in operation during display data write.
NXP Semiconductors PCF2113x
LCD controllers/drivers
9.4.3 Bit BThe character indicated by the cursor blinks when B= 1. The cursor character blink is
displayed by switching between display characters and all dots on with a period of
approximately 1 s, with Hz.
The cursor underline and the cursor character blink can be set to display simultaneously.
9.5 Cursor or display shift‘Cursor/display shift’ moves the cursor position or the display to the right or left without
writing or reading display data. This function is used to correct a character or move the
cursor through the display. In 2-line displays, the cursor moves to the next line when it
passes the last positionof the line. When the displayed datais shifted repeatedlyall lines
shift at the same time; displayed characters do not shift into the next line.
The Address Counter (AC) content does not change if the only action performed is shift
display, but increments or decrements with the ‘cursor display shift’.
9.6 Function set
9.6.1 Bit DL (parallel mode only)Sets interface data width. Data is sent or received in bytes (DB7to DB0) when DL= 1 or
in two nibbles (DB7to DB4) when DL= 0. When 4-bit width is selected, data is
transmitted in two cycles using the parallel bus. In a 4-bit application DB3to DB0 should
be left open-circuit (internal pull-ups). Hence in the first ‘function set’ instruction after
power-onM, SL and H are set to logic 1. A second ‘function set’ must then be sent nibbles) to set M, SL and H to their required values.
‘Function set’ from the I2 C-bus interface sets the DL bit to logic1.
9.6.2 Bit MSelects either1 line×24 character display(M=0)or2 line×12 character display (M= 1).
9.6.3 Bit SLSelects MUX 1:9,1 line×12 character display (independentofM andL). Only rows1to8
and 17 are to be used. All other rows must be left open-circuit. The DDRAM map is the
same as in the 2 line × 12 character display mode, however, the second line is not
displayed.
9.6.4 Bit HWhen H= 0 the chip can be programmed via the standard 11 instruction codes used in
the PCF2116 and other LCD controllers.
When H= 1 the extended range of instructions will be used. These are mainly for
controlling the display configuration and the icons, as shown in Section 10.
9.7 Set CGRAM address‘Set CGRAM address’ writes bits DB5to DB0 of the CGRAM address ACG into the
address counter (A5hto A0h). Data can then be written to or read from the CGRAM. blinkosc
104448------------------=
NXP Semiconductors PCF2113x
LCD controllers/drivers
Remark: the CGRAM address uses the same address register as the DDRAM address
and consists of 7 bits (A6hto A0h). With the ‘set CGRAM address’ command, only
bits DB5to DB0 are set. Bit DB6 can be set using the ‘set DDRAM address’ command
first,orby using the auto-increment feature during CGRAM write.All bits DB6to DB0 can
be read using the ‘read busy flag’ and ‘read address’ command.
When writing to the lower part of the CGRAM, ensure that bit DB6 of the address is not
set (e.g. by an earlier DDRAM write or read action).
9.8 Set DDRAM address‘Set DDRAM address’ writes the DDRAM address ADD into the address counter
(A6hto A0h). Data can then be written to or read from the DDRAM.
9.9 Read busy flag and read address‘Read busy flag and address counter’ reads the Busy Flag (BF) and Address
Counter (AC). BF= 1 indicates that an internal operation is in progress. The next
instruction will not be executed until BF= 0. It is recommended that the BF status is
checked before the next write operation is executed.
At the same time, the value of the address counter (A6hto A0h) is read out, into DB6 to
DB0. The address counter is used by both CGRAM and DDRAM, and its value is
determined by the previous instruction.
9.10 Write data to CGRAM or DDRAM‘Write data’ writes binary 8-bit data DB7to DB0 to the CGRAM or the DDRAM.
Whether the CGRAM or DDRAM is to be written into is determined by the previous ‘set
CGRAM address’ or ‘set DDRAM address’ command. After writing, the address
automatically increments or decrements by 1, in accordance with the entry mode. Only
bits DB4to DB0 of CGRAM data are valid, bits DB7to DB5 are ‘not relevant’.
9.11 Read data from CGRAM or DDRAM‘Read data’ reads binary 8-bit data DB7to DB0 from the CGRAM or DDRAM.
The most recent ‘set address’ command determines whether the CGRAMor DDRAMisto
be read.
The ‘read data’ instruction gates the content of the Data Register (DR) to the bus while
pinEis HIGH. After pinE goes LOW again, internal operation increments(or decrements)
the AC and stores RAM data corresponding to the new AC into the DR.
There are only three instructions that update the DR:
‘Set CGRAM address’
‘Set DDRAM address’
‘Read data’ from CGRAM or DDRAM
Other instructions (e.g. ‘write data’, ‘cursor/display shift’, ‘clear display’ and ‘return home’)
do not modify the data register content.
NXP Semiconductors PCF2113x
LCD controllers/drivers
10. Extended function set instructions and features
10.1 New instructions= 1 sets the chip into Extended instruction set mode.
10.2 Icon controlThe PCF2113x can drive up to 120 icons. See Figure 18 and Figure 19 for CGRAM to
icon mapping.
NXP Semiconductors PCF2113x
LCD controllers/drivers
10.3 Bit IMWhenIM=0, the chipisin Character mode.In Character mode, characters and icons are
driven (MUX 1:18 or MUX 1:9). The VLCD generator, if used, produces the VLCD voltage
programmed in register VA.
When IM= 1, the chip is in Icon mode. In Icon mode only the icons are driven (MUX 1:2)
and the VLCD generator,if used, produces the VLCD voltageas programmedin register VB.
10.4 Bit IBIcon blink control is independent of the cursor/character blink function.
When IB= 0, the icon blink is disabled. Icon data is stored in CGRAM characters 0to2×8×5= 120 bits for 120 icons).
When IB= 1, the icon blink is enabled. In this case each icon is controlled by two bits.
Blink consists of two half phases (corresponding to the cursor on and off phases called
even and odd phases hereafter).
Table 12. Character/Icon mode operation Character mode defined in VA Icon mode defined in VB
NXP Semiconductors PCF2113x
LCD controllers/driversIcon states for the even phase are stored in CGRAM characters 0to2×8×5= 120 bitsfor 120 icons). These bits also define icon state when icon blinkis not
used (see Table 13).
Icon statesfor the odd phase are storedin CGRAM characters4to6 (another 120 bitsfor
the 120 icons). When icon blink is disabled CGRAM characters 4to 6 may be used as
normal CGRAM characters.
10.5 Direct modeWhen DM= 0, the chip is not in the Direct mode. Either the internal VLCD generator or an
external voltage may be used to achieve VLCD.
When DM=1, the chipisin Direct mode. The internal VLCD generatoris turnedoff and the
output VLCDOUT is directly connected VDD2 (i.e. the VLCD generator supply voltage).
The Direct mode can be used to reduce the current consumption when the required
output voltage VLCDOUT is close to the VDD2 supply voltage. This can be the case in Icon
mode or in MUX 1:9 (depending on LCD liquid properties).
10.6 Voltage multiplier control
10.6.1 Bits S1 and S0A software configurable voltage multiplier is incorporated in the VLCD generator and can
be set via the ‘Set HVgen stages’ command.
The voltage multiplier control can be used to reduce current consumption by
disconnecting internal voltage multiplier stages, dependingon the required output voltage
VLCD (see Table 14).
10.7 Screen configuration
10.7.1 Bit L= 0: the two halves of a split screen are connected in a standard way i.e. column 1/61,
2/62to 60/120; default.= 1: the two halves of a split screen are connected in a mirrored way i.e. column 1/120,
2/119to 60/61. This allows single layer PCB or glass layout.
Table 13. Blink effect for icons and cursor character blinkCursor character blink block (all on) normal (display character)
Icons state 1; CGRAM character0to2 state 2; CGRAM character4to6
Table 14. S1 and S0 control of voltage multiplier 0 set VLCD generator stages to 1 (2 × voltage multiplier) 1 set VLCD generator stages to 2 (3 × voltage multiplier) 0 set VLCD generator stages to 3 (4 × voltage multiplier) 1 do not use
