PCA9673BS-PCA9673D-PCA9673PW Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9673PW ,Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and resetGeneral descriptionThe PCA9673 provides general purpose remote I/O expansion for most microcontroll ..
PCA9674ABS ,Remote 8-bit I/O expander for Fm+ I虏C-bus with interruptapplications and the latched output ports have 25 mA high current sink drive capability for directl ..
PCA9674AD ,Remote 8-bit I/O expander for Fm+ I虏C-bus with interruptFeatures and benefits2 I C-bus to parallel port expander2 2 1MHz I C-bus interface (Fast-mode Plu ..
PCA9674APW ,Remote 8-bit I/O expander for Fm+ I虏C-bus with interruptGeneral descriptionThe PCA9674/74A provides general-purpose remote I/O expansion via the two-wire 2 ..
PCA9674BS ,Remote 8-bit I/O expander for Fm+ I虏C-bus with interruptapplications and the latched output ports have 25 mA high current sink drive capability for directl ..
PCA9674D ,Remote 8-bit I/O expander for Fm+ I虏C-bus with interruptFeatures and benefits2 I C-bus to parallel port expander2 2 1MHz I C-bus interface (Fast-mode Plu ..
PF08127B , MOS FET Power Amplifier Module for E-GSM and DCS1800/1900 Triple Band Handy Phone
PF38F5070M0Y0B0 , Numonyx Wireless Flash Memory (W18) with AD Multiplexed IO
PF38F5070M0Y1V0 , StrataFlash® Cellular Memory
PF48F3000P0ZTQ0 , Numonyx StrataFlash Embedded Memory
PF5001 ,Top Electronics - 50A 1/2 PRESS-FIT DIODE
PF5001 ,Top Electronics - 50A 1/2 PRESS-FIT DIODE

PCA9673BS-PCA9673D-PCA9673PW
Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
1. General description
The PCA9673 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2 C-bus) and is a part of the Fast-mode Plus
family.
The PCA9673 is a drop in upgrade for the PCF8575 providing higher Fast-mode Plus
(Fm+) I2 C-bus speeds (1 MHz versus 400 kHz) so that the output can support PWM
dimming of LEDs, higher I2 C-bus drive (30 mA versus 3 mA) so that many more devices
can be on the bus without the need for bus buffers, higher total package sink capacity
(400 mA versus 100 mA) that supports having all 25 mA LEDs on at the same time and
more device addresses (16 versus 8) are available to allow many more devices on the
bus without address conflicts.
The difference between the PCA9673 and the PCF8575 is that the A2 address pin is
replaced by a RESET input on the PCA9673.
The device consists of a 16-bit quasi-bidirectional port and an I2 C-bus interface. The
PCA9673 has a low current consumption and includes latched outputs with 25 mA high
current drive capability for directly driving LEDs.
It also possesses an interrupt line (INT) which can be connected to the interrupt logic of
the microcontroller. By sending an interrupt signal on this line, the remote I/O can inform
the microcontroller if there is incoming data on its ports without having to communicate via
the I2 C-bus.
The internal Power-On Reset (POR), hardware reset pin (RESET) or software reset
sequence initializes the I/Os as inputs.
2. Features and benefits 1MHz I2 C-bus interface Compliant with the I2 C-bus Fast and Standard modes SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 16-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 400 mA Active LOW open-drain interrupt output 16 programmable slave addresses using 2 address pins Readable device ID (manufacturer, device type, and revision)
PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and
reset
Rev. 2 — 29 September 2011 Product data sheet
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset Low standby current 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA Packages offered: SO24, TSSOP24, HVQFN24, DHVQFN24
3. Applications LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones Gaming machines Instrumentation and test measurement
4. Ordering informationTable 1. Ordering information
PCA9673D PCA9673D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA9673PW PCA9673PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9673BQ 9673 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad
flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm
SOT815-1
PCA9673BS 9673 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 44 0.85 mm
SOT616-1
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
5. Block diagram
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
6. Pinning information
6.1 Pinning
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
6.2 Pin description
[1] HVQFN24 and DHVQFN24 package die supply ground is connected to both the VSS pin and the exposed
center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 2. Pin description
INT 1 22 interrupt output (active LOW)
AD1 2 23 address input 1
RESET 3 24 reset input (active LOW)
P00 4 1 quasi-bidirectional I/O 00
P01 5 2 quasi-bidirectional I/O 01
P02 6 3 quasi-bidirectional I/O 02
P03 7 4 quasi-bidirectional I/O 03
P04 8 5 quasi-bidirectional I/O 04
P05 9 6 quasi-bidirectional I/O 05
P06 10 7 quasi-bidirectional I/O 06
P07 11 8 quasi-bidirectional I/O 07
VSS 12[1] 9[1] supply ground
P10 13 10 quasi-bidirectional I/O 10
P11 14 11 quasi-bidirectional I/O 11
P12 15 12 quasi-bidirectional I/O 12
P13 16 13 quasi-bidirectional I/O 13
P14 17 14 quasi-bidirectional I/O 14
P15 18 15 quasi-bidirectional I/O 15
P16 19 16 quasi-bidirectional I/O 16
P17 20 17 quasi-bidirectional I/O 17
AD0 21 18 address input 0
SCL 22 19 serial clock line input
SDA 23 20 serial data line input/output
VDD 24 21 supply voltage
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
7. Functional description
Refer to Figure 1 “Block diagram of PCA9673”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9673 is shown in Figure 7. Slave address pins AD1 and AD0 choose 1 of 16 slave
addresses. To conserve power, no internal pull-up resistors are incorporated on AD1 and
AD0. Address values depending on AD1 and AD0 can be found in Table 3 “PCA9673
address map”.
Remark: The General Call address (0000 0000b) and the Device ID address
(1111 100Xb) are reserved and cannot be used as device address. Failure to follow this
requirement will cause the PCA9673 not to acknowledge.
Remark: Reserved I2 C-bus addresses must be used with caution since they can interfere
with: “reserved for future use” I2 C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) slave devices that use the 10-bit addressing scheme (1111 0xx) High speed mode (Hs-mode) master code (0000 1xx)
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is applied.
7.1.1 Address maps
Table 3. PCA9673 address map
SCL VSS 00 10 10 028h
SCL VDD 00 10 10 12Ah
SDA VSS 00 10 11 02Ch
SDA VDD 00 10 11 12Eh
SCL SCL 00 11 10 038h
SCL SDA 00 11 10 13Ah
SDA SCL 00 11 11 03Ch
SDA SDA 00 11 11 13Eh
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
7.2 Software Reset call, and Device ID addresses
Two other different addresses can be sent to the PCA9673. General Call address: allows to reset the PCA9673 through the I2 C-bus upon
reception of the right I2 C-bus sequence. See Section 7.2.1 “Software Reset” for more
information. Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 “Device ID (PCA9673 ID field)” for more
information.
VSS VSS 01 00 10 048h
VSS VDD 01 00 10 14Ah
VDD VSS 01 00 11 04Ch
VDD VDD 01 00 11 14Eh
VSS SCL 0 10 11 00 58h
VSS SDA 0 10 11 01 5Ah
VDD SCL 0 10 11 10 5Ch
VDD SDA 0 10 11 11 5Eh
Table 3. PCA9673 address map …continued
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2 C-bus to be reset to the power-up
state value through a specific formatted I2 C-bus command. To be performed correctly, it
implies that the I2 C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following: A START command is sent by the I2 C-bus master. The reserved General Call I2 C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2 C-bus master. The PCA9673 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to
the I2 C-bus master. Once the General Call address has been sent and acknowledged, the master sends byte. The value of the byte must be equal to 06h. The PCA9673 acknowledges this value only. If the byte is not equal to 06h, the
PCA9673 does not acknowledge it.
If more than 1 byte of data is sent, the PCA9673 does not acknowledge any more. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9673 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed.
The I2 C-bus master must interpret a non-acknowledge from the PCA9673 (at any time) as
a ‘Software Reset Abort’. The PCA9673 does not initiate a reset of its registers.
The unique sequence that initiates a Software Reset is described in Figure 10.
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
7.2.2 Device ID (PCA9673 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:8 bits with the manufacturer name, unique per manufacturer (for example,
NXP Semiconductors). 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example, PCA9673 16-bit
quasi-output I/O expander).3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows: START command The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to 0 (write). The master sends the I2 C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2 C-bus slave address). The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed.
Remark: A STOP command or a Re-START command followed by an access to
another slave device will reset the slave state machine and the Device ID read cannot
be performed. The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to 1 (read). The device ID read can be done, starting with the 8 manufacturer bits (first byte+ MSB of the second byte), followed by the 13 part identification bits and then the die revision bits (3 LSB of the third byte). The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
Remark: If the master continues to ACK the bytes after the third byte, the PCA9673
rolls back to the first byte and keeps sending the Device ID sequence until a NACK
has been detected.
For the PCA9673, the Device ID is as shown in Figure 11.
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
The PCA9673’s 16 ports (see Figure 2) are entirely independent and can be used either
as input or output ports. Input data is transferred from the ports to the microcontroller in
the Read mode (see Figure 15). Output data is transmitted to the ports in the Write mode
(see Figure 14).
Every data transmission from the PCA9673 must consist of an even number of bytes, the
first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third
will be referred to as P07 to P00, and so on.
This quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data directions. At power-on the I/Os are HIGH. In this mode only a current
source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising
edges into heavily loaded outputs. These devices turn on when an output is written HIGH,
and are switched off by the negative edge of SCL. The I/Os should be HIGH before being
used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as
inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the
write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large
current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the Write mode is entered. The
PCA9673 acknowledges and the master sends the first data byte for P07 to P00. After the
first data byte is acknowledged by the PCA9673, the second data byte P17 to P10 is sent
by the master. Once again, the PCA9673 acknowledges the receipt of the data. Each 8-bit
data is presented on the port lines after it has been acknowledged by the PCA9673.
The number of data bytes that can be sent successively is not limited. After every two
bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data
byte in every pair refers to Port 1 (P17 to P10). See Figure 13.
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports. If the data on the input
port changes faster than the master can read, this data may be lost.
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
xxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
x x
x
x x
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
x x
xxxx
xxx
xxx
xxxx
xxx
x xx
xx
xx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
xx x
xxx
xx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xx
xxxx
xxx
xxx
x x
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xxx
xxx
xxxx
xx
xxxx
xxx
xxx
xxx
xxxx
xxx
xxxx
xxx
xxxx
xx
xxx
xxxx
xxx
xxxx
xxx
x xx
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9673 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9673 registers and I2 C-bus/SMBus state machine will initialize to their default
states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)
The PCA9673 provides an open-drain interrupt (INT) which can be fed to a corresponding
input of the microcontroller (see Figure 15, Figure 16, and Figure 17). This gives these
chips a kind of master function which can initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port inputs. After time t(v)D the
signal INT is valid.
The interrupt disappears when data on the port is changed to the original setting or data is
read from or written to the device which has generated the interrupt.
In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as
an INT.
8.6 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9673 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
NXP Semiconductors PCA9673
Remote 16-bit I/O expander for Fm+ I2 C-bus with interrupt and reset
9. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 18).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 19).
9.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 20).

Partno	Mfg	Dc	Qty	Available	Descript
PCA9673BS	PHILIS	N/a	705	avai	Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
PCA9673D	PHILIS	N/a	387	avai	Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset
PCA9673PW	NXP	N/a	1670	avai	Remote 16-bit I/O expander for Fm+ I2C-bus with interrupt and reset