PCA9671BS-PCA9671PW Fast Delivery |IC PHOENIX CO.,LIMITED

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PCA9671BS-PCA9671PW
Remote 16-bit I/O expander for Fm+ I2C-bus with reset
1. General description
The PCA9671 provides general purpose remote I/O expansion for most microcontroller
families via the two-line bidirectional bus (I2 C-bus) and is a part of the Fast-mode Plus
(Fm+) family.
The PCA9671 is a drop in upgrade for the PCF8575 providing higher I2 C-bus speeds MHz versus 400 kHz) so that the output can support PWM dimming of LEDs, higher 2 C-bus drive (30 mA versus 3 mA) so that many more devices can be on the bus without
the need for bus buffers, higher total package sink capacity (400 mA versus 100 mA) that
supports having all 25 mA LEDs on at the same time and more device addresses
(64 versus 8) to allow many more devices on the bus without address conflicts.
The difference between the PCA9671 and the PCF8575 is that the interrupt output on the
PCF8575 is replaced by a RESET input on the PCA9671.
The device consists of a 16-bit quasi-bidirectional port and an I2 C-bus interface. The
PCA9671 has a low current consumption and includes latched outputs with 25 mA high
current drive capability for directly driving LEDs. The internal Power-On Reset (POR),
hardware reset pin (RESET) or software reset sequence initializes the I/Os as inputs.
2. Features and benefits 1MHz I2 C-bus interface Compliant with the I2 C-bus Fast-mode and Standard-mode SDA with 30 mA sink capability for 4000 pF buses 2.3 V to 5.5 V operation with 5.5 V tolerant I/Os 16-bit remote I/O pins that default to inputs at power-up Latched outputs with 25 mA sink capability for directly driving LEDs Total package sink capability of 400 mA Active LOW reset input 64 programmable slave addresses using 3 address pins Readable device ID (manufacturer, device type, and revision) Low standby current 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC standard JESD78 which exceeds 100 mA Packages offered: SO24, TSSOP24, HVQFN24, DHVQFN24
PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
Rev. 3 — 29 September 2011 Product data sheet
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
3. Applications LED signs and displays Servers Industrial control Medical equipment PLCs Cellular telephones Gaming machines Instrumentation and test measurement
4. Ordering informationTable 1. Ordering information
PCA9671D PCA9671D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1
PCA9671PW PCA9671PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9671BQ 9671 DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad
flat package; no leads; 24 terminals; body 3.5 5.5 0.85 mm
SOT815-1
PCA9671BS 9671 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; terminals; body 44 0.85 mm
SOT616-1
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
5. Block diagram
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
6. Pinning information
6.1 Pinning
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
6.2 Pin description
[1] HVQFN24 and DHVQFN24 package die supply ground is connected to both the VSS pin and the exposed
center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced
thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using
a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 2. Pin description
RESET 1 22 reset input (active LOW)
AD1 2 23 address input 1
AD2 3 24 address input 2
P00 4 1 quasi-bidirectional I/O 00
P01 5 2 quasi-bidirectional I/O 01
P02 6 3 quasi-bidirectional I/O 02
P03 7 4 quasi-bidirectional I/O 03
P04 8 5 quasi-bidirectional I/O 04
P05 9 6 quasi-bidirectional I/O 05
P06 10 7 quasi-bidirectional I/O 06
P07 11 8 quasi-bidirectional I/O 07
VSS 12[1] 9[1] supply ground
P10 13 10 quasi-bidirectional I/O 10
P11 14 11 quasi-bidirectional I/O 11
P12 15 12 quasi-bidirectional I/O 12
P13 16 13 quasi-bidirectional I/O 13
P14 17 14 quasi-bidirectional I/O 14
P15 18 15 quasi-bidirectional I/O 15
P16 19 16 quasi-bidirectional I/O 16
P17 20 17 quasi-bidirectional I/O 17
AD0 21 18 address input 0
SCL 22 19 serial clock line input
SDA 23 20 serial data line input/output
VDD 24 21 supply voltage
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
7. Functional description
Refer to Figure 1 “Block diagram of PCA9671”.
7.1 Device address
Following a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9671 is shown in Figure 7. Slave address pins AD2, AD1, and AD0 choose 1 of slave addresses. To conserve power, no internal pull-up resistors are incorporated on
AD2, AD1, and AD0. Address values depending on AD2, AD1, and AD0 can be found in
Table 3 “PCA9671 address map”.
Remark: The General Call address (0000 0000) and the Device ID address (1111 100X)
are reserved and cannot be used as device address. Failure to follow this requirement will
cause the PCA9671 not to acknowledge.
Remark: Reserved I2 C-bus addresses must be used with caution since they can interfere
with: “reserved for future use” I2 C-bus addresses (0000 011, 1111 101, 1111 110, 1111 111) slave devices that use the 10-bit addressing scheme (1111 0xx) High speed mode (Hs-mode) master code (0000 1xx)
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while a logic 0 selects a write operation.
When AD2, AD1 and AD0 are held to VDD or VSS, the same address as the PCF8575 is
applied.
7.1.1 Address maps
Table 3. PCA9671 address map
VSS SCL VSS 0 01000 020h
VSS SCL VDD 0 01000 122h
VSS SDA VSS 0 01001 024h
VSS SDA VDD 0 01001 126h
VDD SCL VSS 0 01010 028h
VDD SCL VDD 0 01010 12Ah
VDD SDA VSS 0 01011 02Ch
VDD SDA VDD 0 01011 12Eh
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
VSS SCL SCL 0 01100 030h
VSS SCL SDA 0 01100 132h
VSS SDA SCL 0 01101 034h
VSS SDA SDA 0 01101 136h
VDD SCL SCL 0 01110 038h
VDD SCL SDA 0 01110 13Ah
VDD SDA SCL 0 01111 03Ch
VDD SDA SDA 0 01111 13Eh
VSS VSS VSS 0 10000 040h
VSS VSS VDD 0 10000 142h
VSS VDD VSS 0 10001 044h
VSS VDD VDD 0 10001 146h
VDD VSS VSS 0 10010 048h
VDD VSS VDD 0 10010 14Ah
VDD VDD VSS 0 10011 04Ch
VDD VDD VDD 0 10011 14Eh
VSS VSS SCL 0 10100 050h
VSS VSS SDA 0 10100 152h
VSS VDD SCL 0 10101 054h
VSS VDD SDA 0 10101 156h
VDD VSS SCL 0 10110 058h
VDD VSS SDA 0 10110 15Ah
VDD VDD SCL 0 10111 05Ch
VDD VDD SDA 0 10111 15Eh
SCL SCL VSS 1 01000 0A0h
SCL SCL VDD 1 01000 1A2h
SCL SDA VSS 1 01001 0A4h
SCL SDA VDD 1 01001 1A6h
SDA SCL VSS 1 01010 0A8h
SDA SCL VDD 1 01010 1AAh
SDA SDA VSS 1 01011 0ACh
SDA SDA VDD 1 01011 1AEh
SCL SCL SCL 1 01100 0B0h
SCL SCL SDA 1 01100 1B2h
SCL SDA SCL 1 01101 0B4h
SCL SDA SDA 1 01101 1B6h
SDA SCL SCL 1 01110 0B8h
SDA SCL SDA 1 01110 1BAh
SDA SDA SCL 1 01111 0BCh
SDA SDA SDA 1 01111 1BEh
Table 3. PCA9671 address map …continued
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
7.2 Software Reset call, and device ID addresses
Two other different addresses can be sent to the PCA9671. General Call address: allows to reset the PCA9671 through the I2 C-bus upon
reception of the right I2 C-bus sequence. See Section 7.2.1 “Software Reset” for more
information. Device ID address: allows to read ID information from the device (manufacturer, part
identification, revision). See Section 7.2.2 “Device ID (PCA9671 ID field)” for more
information.
SCL VSS VSS 1 10000 0C0h
SCL VSS VDD 1 10000 1C2h
SCL VDD VSS 1 10001 0C4h
SCL VDD VDD 1 10001 1C6h
SDA VSS VSS 1 10010 0C8h
SDA VSS VDD 1 10010 1CAh
SDA VDD VSS 1 10011 0CCh
SDA VDD VDD 1 10011 1CEh
SCL VSS SCL 1 11000 0E0h
SCL VSS SDA 1 11000 1E2h
SCL VDD SCL 1 11001 0E4h
SCL VDD SDA 1 11001 1E6h
SDA VSS SCL 1 11010 0E8h
SDA VSS SDA 1 11010 1EAh
SDA VDD SCL 1 11011 0ECh
SDA VDD SDA 1 11011 1EEh
Table 3. PCA9671 address map …continued
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
7.2.1 Software Reset
The Software Reset Call allows all the devices in the I2 C-bus to be reset to the power-up
state value through a specific formatted I2 C-bus command. To be performed correctly, it
implies that the I2 C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following: A START command is sent by the I2 C-bus master. The reserved General Call I2 C-bus address ‘0000 000’ with the R/W bit set to logic0
(write) is sent by the I2 C-bus master. The PCA9671 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is
returned to the I2 C-bus master. Once the General Call address has been sent and acknowledged, the master sends byte. The value of the byte must be equal to 06h. The PCA9671 acknowledges this value only. If the byte is not equal to 06h, the
PCA9671 does not acknowledge it.
If more than 1 byte of data is sent, the PCA9671 does not acknowledge any more. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9671 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed.
The I2 C-bus master must interpret a non-acknowledge from the PCA9671 (at any time) as
a ‘Software Reset Abort’. The PCA9671 does not initiate a reset of its registers.
The unique sequence that initiates a Software Reset is described in Figure 10.
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
7.2.2 Device ID (PCA9671 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:8 bits with the manufacturer name, unique per manufacturer (for example,
NXP Semiconductors). 13 bits with the part identification, assigned by manufacturer, the 7 MSBs with the
category ID and the 6 LSBs with the feature ID (for example, PCA9671 16-bit
quasi-output I/O expander).3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows: START command. The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to logic 0 (write). The master sends the I2 C-bus slave address of the slave device it needs to identify.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2 C-bus slave address). The master sends a Re-START command.
Remark: A STOP command followed by a START command will reset the slave state
machine and the Device ID read cannot be performed.
Remark: A STOP command or a Re-START command followed by an access to
another slave device will reset the slave state machine and the Device ID read cannot
be performed. The master sends the Reserved Device ID I2 C-bus address ‘1111 100’ with the R/W
bit set to logic 1 (read). The device ID read can be done, starting with the 8 manufacturer bits (first byte+ MSB of the second byte), followed by the 13 part identification bits and then the die revision bits (3 LSB of the third byte). The master ends the reading sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
Remark: If the master continues to ACK the bytes after the third byte, the PCA9671
rolls back to the first byte and keeps sending the Device ID sequence until a NACK
has been detected.
For the PCA9671, the Device ID is as shown in Figure 11.
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
8. I/O programming
8.1 Quasi-bidirectional I/O architecture
The PCA9671’s 16 ports (see Figure 2) are entirely independent and can be used either
as input or output ports. Input data is transferred from the ports to the microcontroller in
the Read mode (see Figure 15). Output data is transmitted to the ports in the Write mode
(see Figure 14).
Every data transmission from the PCA9671 must consist of an even number of bytes, the
first byte will be referred to as P07 to P00, and the second byte as P17 to P10. The third
will be referred to as P07 to P00, and so on.
This quasi-bidirectional I/O can be used as an input or output without the use of a control
signal for data directions. At power-on the I/Os are HIGH. In this mode only a current
source (IOH) to VDD is active. An additional strong pull-up to VDD (Itrt(pu)) allows fast rising
edges into heavily loaded outputs. These devices turn on when an output is written HIGH,
and are switched off by the negative edge of SCL. The I/Os should be HIGH before being
used as inputs. After power-on, as all the I/Os are set HIGH, all of them can be used as
inputs. Any change in setting of the I/Os as either inputs or outputs can be done with the
write mode.
Remark: If a HIGH is applied to an I/O which has been written earlier to LOW, a large
current (IOL) will flow to VSS.
8.2 Writing to the port (Output mode)
To write, the master (microcontroller) first addresses the slave device. By setting the last
bit of the byte containing the slave address to logic 0 the Write mode is entered. The
PCA9671 acknowledges and the master sends the first data byte for P07 to P00. After the
first data byte is acknowledged by the PCA9671, the second data byte P17 to P10 is sent
by the master. Once again, the PCA9671 acknowledges the receipt of the data. Each 8-bit
data is presented on the port lines after it has been acknowledged by the PCA9671.
The number of data bytes that can be sent successively is not limited. After every two
bytes, the previous data is overwritten.
The first data byte in every pair refers to Port 0 (P07 to P00), whereas the second data
byte in every pair refers to Port 1 (P17 to P10). See Figure 13.
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
8.3 Reading from a port (Input mode)
All ports programmed as input should be set to logic 1. To read, the master
(microcontroller) first addresses the slave device after it receives the interrupt. By setting
the last bit of the byte containing the slave address to logic 1 the Read mode is entered.
The data bytes that follow on the SDA are the values on the ports.
If the data on the input port changes faster than the master can read, this data may be
lost.
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NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
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NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
NXP Semiconductors PCA9671
Remote 16-bit I/O expander for Fm+ I2 C-bus with reset
8.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9671 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9671 registers and I2 C-bus/SMBus state machine will initialize to their default
states. Thereafter VDD must be lowered below 0.2 V to reset the device.
8.5 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9671 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
9. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 17).
9.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 18).

Partno	Mfg	Dc	Qty	Available	Descript
PCA9671BS	PHILIS	N/a	812	avai	Remote 16-bit I/O expander for Fm+ I2C-bus with reset
PCA9671PW	NXP	N/a	696	avai	Remote 16-bit I/O expander for Fm+ I2C-bus with reset