PCA9634PW ,8-bit Fm+ I2C-bus LED driverFeaturesn 8 LED drivers. Each output programmable at:u Offu Onu Programmable LED brightnessu Progra ..
PCA9635PW ,16-bit Fm+ I2C-bus LED driverFeaturesn 16 LED drivers. Each output programmable at:u Offu Onu Programmable LED brightnessu Progr ..
PCA9665BS ,Fm+ parallel bus to I2C-bus controllerApplications2 Add I C-bus port to controllers/processors that do not have one2 2 Add additional I ..
PCA9665D ,Fm+ parallel bus to I2C-bus controllerFeatures and benefits2 Parallel-bus to I C-bus protocol converter and interface Both master and s ..
PCA9665PW ,Fm+ parallel bus to I2C-bus controllerBlock diagram dataD7 D6 D5 D4 D3 D2 D1 D0PCA9665/PCA9665ABUS BUFFERSDAdirect registersFILTERA1 A0SD ..
PCA9670BS ,Remote 8-bit I/O expander for Fm+ I虏C-bus with resetApplications LED signs and displays Servers Keypads Industrial control Medical equipment PLCs ..
PF0560.104NLT , SMT POWER INDUCTORS
PF0560.152NL , SMT POWER INDUCTORS Shielded Drum Core - PF0560NL Series
PF0560.382NL , SMT POWER INDUCTORS Shielded Drum Core - PF0560NL Series
PF0560.382NLT , SMT POWER INDUCTORS
PF08127B , MOS FET Power Amplifier Module for E-GSM and DCS1800/1900 Triple Band Handy Phone
PF38F5070M0Y0B0 , Numonyx Wireless Flash Memory (W18) with AD Multiplexed IO
PCA9634BS-PCA9634PW
8-bit Fm+ I2C-bus LED driver
General descriptionThe PCA9634 is an I2 C-bus controlled 8-bit LED driver optimized for
Red/Green/Blue/Amber (RGBA) color mixing applications. Each LED output has its own
8-bit resolution (256 steps) fixed frequency Individual PWM controller that operates at kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the LED to be set
to a specific brightness value. An additional 8-bit resolution (256 steps) Group PWM
controller has both a fixed frequency of 190 Hz and an adjustable frequency between Hzto once every 10.73 seconds witha duty cycle thatis adjustable from0%to 99.6%
that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its Individual PWM controller
value or at both Individual and Group PWM controller values. The LED output driver is
programmed to be either open-drain with a 25 mA current sink capability at 5 V or
totem-pole witha25 mA sink,10 mA source capabilityat5V. The PCA9634 operates with
a supply voltage range of 2.3 V to 5.5 V and the outputs are 5.5 V tolerant. LEDs can be
directly connected to the LED output (up to 25 mA, 5.5 V) or controlled with external
drivers anda minimum amountof discrete componentsfor larger currentor higher voltage
LEDs.
The PCA9634 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)
family. Fm+ devices offer higher frequency (upto1 MHz) and more densely populated bus
operation (up to 4000 pF).
The active LOW Output Enable input pin (OE) allows asynchronous control of the LED
outputs and can be used to set all the outputs to a defined I2 C-bus programmable logic
state. The OE can also be used to externally PWM the outputs, which is useful when
multiple devices need to be dimmed or blinked together using software control.
Software programmable LED Group and three Sub Call I2 C-bus addresses allow all or
defined groups of PCA9634 devices to respond to a common I2 C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2 C-bus commands. Seven hardware address pins allow up to
126 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9634
through theI2 C-bus, identicalto the Power-On Reset (POR) that initializes the registersto
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
PCA9634
8-bit Fm+ I2 C-bus LED driver
Rev. 06 — 12 September 2008 Product data sheet
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver Features 8 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness1 MHz Fast-mode Plus compatible I2 C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 97 kHz PWM signal 256-step group brightness control allows general dimming (using a 190 Hz PWM
signal) from fully off to maximum brightness (default) 256-step group blinking with frequency programmable from24 Hzto 10.73s and duty
cycle from 0 % to 99.6% Eight totem-pole outputs (sink 25 mA and source 10 mA at 5 V) with software
programmable open-drain LED outputs selection (default at totem-pole). No input
function. Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’). Active LOW Output Enable (OE) input pin. LED outputs programmable to 1, 0 or
‘high-impedance’ (default at power-up) when OE is HIGH, thus allowing hardware
blinking and dimming of the LEDs. 7 hardware address pins allow 126 devices to be connected to the same I2 C-bus 4 software programmable I2 C-bus addresses (one LED Group Call address and three
LED Sub Call addresses) allow groupsof devicestobe addressedat the same timein
any combination (for example, one register usedfor ‘All Call’so thatall the PCA9634s
on the I2 C-bus can be addressed at the same time and the second register used for
three different addresses so that1 ⁄3 of all devices on the bus can be addressed at the
same time in a group). Software enable and disable for I2 C-bus address. Software Reset feature (SWRST Call) allows the device to be reset through the2 C-bus 25 MHz internal oscillator requires no external components Internal power-on reset Noise filter on SDA/SCL inputs Edge rate control on outputs No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V 5.5 V tolerant inputs −40 °C to +85 °C operation ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO20, TSSOP20, HVQFN20
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver Applications RGB or RGBA LED drivers LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices
Ordering information
Table 1. Ordering informationPCA9634D PCA9634D SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
PCA9634PW PCA9634 TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
PCA9634BS 9634 HVQFN20 plastic thermal enhanced very thin quadflat package;no leads; terminals; body5×5× 0.85 mm
SOT662-1
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver Block diagram
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver Pinning information
6.1 Pinning
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
6.2 Pin description[1] HVQFN20 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSSpin mustbe connectedto supply groundfor proper device operation.For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Table 2. Pin description 1 19 I address input 0 2 20 I address input 1 3 1 I address input 2 4 2 I address input 3 5 3 I address input 4
LED0 6 4 O LED driver 0
LED1 7 5 O LED driver 1
LED2 8 6 O LED driver 2
LED3 9 7 O LED driver 3
VSS 10 8[1] power supply supply ground
LED4 11 9 O LED driver 4
LED5 12 10 O LED driver 5
LED6 13 11 O LED driver 6
LED7 14 12 O LED driver 7 15 13 I active LOW output enable 16 14 I address input 5 17 15 I address input 6
SCL 18 16 I serial clock line
SDA 19 17 I/O serial data line
VDD 20 18 power supply supply voltage
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver Functional descriptionRefer to Figure 1 “Block diagram of PCA9634”.
7.1 Device addressesFollowing a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 128 possible programmable addresses using the 7 hardware
address pins. Two of these addresses, Software Reset and LED All Call, cannot be used
because their default power-up state is ON, leaving a maximum of 126 addresses. Using
other reserved addresses, as well as any other Sub Call address, will reduce the total
number of possible addresses even further.
7.1.1 Regular I2 C-bus slave addressThe I2 C-bus slave address of the PCA9634 is shown in Figure 5. T o conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
Remark: Using reservedI2 C-bus addresses will interfere with other devices, but onlyif the
devices areon the bus and/or the bus willbe opento otherI2 C-bus systemsat some later
date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9634 treats them like any other address. The
LEDAll Call, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
PCA9634 LED All Call address (1110 000) and Software Reset (0000 0110) which
are active on start-up
PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
‘reserved for future use’ I2 C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX).
The lastbitof the address byte defines the operationtobe performed. When setto logic1
a read is selected, while a logic 0 selects a write operation.
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.1.2 LED All Call I2 C-bus address Default power-up value (ALLCALLADR register): E0h or 1110 000X
Programmable through I2 C-bus (volatile programming)
At power-up, LEDAll CallI2 C-bus addressis enabled. PCA9634 sendsan ACK when
E0h (R/W= 0) or E1h (R/W= 1) is sent by the master.
See Section 7.3.8 “ALLCALLADR: LED All Call I2 C-bus address” for more detail.
Remark: The default LEDAll CallI2 C-bus address (E0hor 1110 000X) must notbe used
as a regular I2 C-bus slave address since this address is enabled at power-up. All the
PCA9634s on the I2 C-bus will acknowledge the address if sent by the I2 C-bus master.
7.1.3 LED Sub Call I2 C-bus addresses 3 different I2 C-bus addresses can be used
Default power-up values:
SUBADR1 register: E2h or 1110 001X
SUBADR2 register: E4h or 1110 010X
SUBADR3 register: E8h or 1110 100X
Programmable through I2 C-bus (volatile programming)
At power-up, Sub Call I2 C-bus addresses are disabled. PCA9634 does not send an
ACK when E2h (R/W= 0) or E3h (R/W= 1), E4h (R/W= 0) or E5h (R/W= 1), or
E8h (R/W= 0) or E9h (R/W= 1) is sent by the master.
See Section 7.3.7 “SUBADR1 to SUBADR3: I2 C-bus subaddress 1to 3” for more detail.
Remark: The default LED Sub Call I2 C-bus addresses may be used as regular I2 C-bus
slave addresses as long as they are disabled.
7.1.4 Software Reset I2 C-bus addressThe address shown in Figure 6 is used when a reset of the PCA9634 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W= 0. If R/W= 1, the PCA9634 does not acknowledge the SWRST. See Section 7.6
“Software Reset” for more detail.
Remark: The Software ResetI2 C-bus addressisa reserved address and cannotbe used
as a regular I2 C-bus slave address or as an LED All Call or LED Sub Call address.
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.2 Control registerFollowing the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9634, which will be
stored in the Control register.
The lowest 5 bits are used as a pointer to determine which register will be accessed
(D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]).
When the Auto-Increment flagis set (AI2=1), the five low order bitsof the Control register
are automatically incremented after a read or write. This allows the user to program the
registers sequentially. Four different types of Auto-Increment are possible, depending on
AI1 and AI0 values.
Remark: Other combinations not shown in Table 3 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0]= 000 is used when the same register must be accessed several times during a
singleI2 C-bus communication,for example, changes the brightnessofa single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0]= 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0]= 101 is used when the four LED drivers must be individually programmed with
different values during the same I2 C-bus communication, for example, changing color
setting to another color setting.
Table 3. Auto-Increment options 0 0 no Auto-Increment 0 0 Auto-Increment for all registers. D[4:0] roll over to ‘0 0000’ after the last
register (1 0001) is accessed. 0 1 Auto-Increment for individual brightness registers only. D[4:0] roll over to 0010’ after the last register (0 1001) is accessed. 1 0 Auto-Increment for global control registers only. D[4:0] roll over to 1010’ after the last register (0 1011) is accessed. 1 1 Auto-Increment for individual and global control registers only. D[4:0] roll
over to ‘0 0010’ after the last register (0 1011) is accessed.
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driverAI[2:0]= 110 is used when the LED drivers must be globally programmed with different
settings during the same I2 C-bus communication, for example, global brightness or
blinking change.
AI[2:0]= 111 is used when individual and global changes must be performed during the
sameI2 C-bus communication,for example, changinga color and global brightnessat the
same time.
Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0 0000 and 1 0001 (as defined in Table 4). When AI[2]= 1, the Auto-Increment
flagis set and the rollover valueat which the register increment stops and goesto the next
one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control
register = 1110 1100 (ECh), then the register addressing sequence will be (in hex):→…→11→00→…→ 0B→02→…→ 0B→02→…→ 0B→02→ … as long
as the master keeps sending or reading data.
7.3 Register definitions
Table 4. Register summaryOnly D[4:0]=0 0000to1 0001 are allowed and will be acknowledged.
D[4:0]=1 0010 to 1 1111 are reserved and will not be acknowledged. 0 0 0 0 0 MODE1 read/write Mode register 1 0 0 0 0 1 MODE2 read/write Mode register 2 0 0 0 1 0 PWM0 read/write brightness control LED0 0 0 0 1 1 PWM1 read/write brightness control LED1 0 0 1 0 0 PWM2 read/write brightness control LED2 0 0 1 0 1 PWM3 read/write brightness control LED3 0 0 1 1 0 PWM4 read/write brightness control LED4 0 0 1 1 1 PWM5 read/write brightness control LED5 0 1 0 0 0 PWM6 read/write brightness control LED6 0 1 0 0 1 PWM7 read/write brightness control LED7 0 1 0 1 0 GRPPWM read/write group duty cycle control 0 1 0 1 1 GRPFREQ read/write group frequency 0 1 1 0 0 LEDOUT0 read/write LED output state 0 0 1 1 0 1 LEDOUT1 read/write LED output state 1 0 1 1 1 0 SUBADR1 read/write I2 C-bus subaddress 1 0 1 1 1 1 SUBADR2 read/write I2 C-bus subaddress 2 1 0 0 0 0 SUBADR3 read/write I2 C-bus subaddress 3 1 0 0 0 1 ALLCALLADR read/write LED All Call I2 C-bus address
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.3.1 Mode register 1, MODE1[1] It takes 500 μs max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings on LEDn outputs are not
guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 μs window.
[2] When the oscillator is off (Sleep mode) the LED outputs cannot be turned on, off or dimmed/blinked.
7.3.2 Mode register 2, MODE2
Table 5. MODE1 - Mode register 1 (address 00h) bit descriptionLegend: * default value. AI2 read only 0 register Auto-Increment disabled register Auto-Increment enabled AI1 read only 0* Auto-Increment bit1=0 Auto-Increment bit1=1 AI0 read only 0* Auto-Increment bit0=0 Auto-Increment bit0=1 SLEEP R/W 0 Normal mode[1] Low power mode; oscillator off[2] SUB1 R/W 0* PCA9634 does not respond to I2 C-bus subaddress 1 PCA9634 responds to I2 C-bus subaddress 1 SUB2 R/W 0* PCA9634 does not respond to I2 C-bus subaddress 2 PCA9634 responds to I2 C-bus subaddress 2 SUB3 R/W 0* PCA9634 does not respond to I2 C-bus subaddress 3 PCA9634 responds to I2 C-bus subaddress 3 ALLCALL R/W 0 PCA9634 does not respond to LED All Call I2 C-bus address PCA9634 responds to LED All Call I2 C-bus address
Table 6. MODE2 - Mode register 2 (address 01h) bit descriptionLegend: * default value. - read only 0* reserved - read only 0* reserved DMBLNK R/W 0* Group control = dimming Group control = blinking INVRT[1] R/W 0* output logic state not inverted; value to use when no external driver used;
applicable when OE=0 output logic state inverted; value to use when external driver used;
applicable when OE=0 OCH R/W 0* outputs change on STOP command[2] outputs change on ACK OUTDRV[1] R/W 0 the 8 LED outputs are configured with an open-drain structure the 8 LED outputs are configured with a totem-pole structure
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver[1] See Section 7.7 “Using the PCA9634 with and without external drivers” for more details. Normal LEDs can be driven directly in either
mode. Some newer LEDs include integrated Zener diodesto limit voltage transients, reduce EMI and protectthe LEDs, and these must
be driven only in the open-drain mode to prevent overheating the IC.
[2] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9634. Applicable to registers from
02h (PWM0) to 0Dh (LEDOUT) only.
[3] See Section 7.4 “Active LOW output enable input” for more details.
7.3.3 PWM0 to PWM7: Individual brightness controlA 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6% duty cycle= LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx= 10 or 11 (LEDOUT0 and LEDOUT1 registers).
(1)to0 OUTNE[1:0][3] R/W 00 when OE = 1 (output drivers not enabled), LEDn = 0
01* when OE = 1 (output drivers not enabled):
LEDn = 1 when OUTDRV=1
LEDn= high-impedance when OUTDRV= 0 (same as OUTNE[1:0]= 10) when OE = 1 (output drivers not enabled), LEDn = high-impedance reserved
Table 6. MODE2 - Mode register 2 (address 01h) bit description …continuedLegend: * default value.
Table 7. PWM0to PWM7 - PWM registers 0to 7 (address 02h to 09h) bit descriptionLegend: * default value.
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
duty cycle IDC 7:0[]
256------------------------=
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.3.4 GRPPWM: Group duty cycle controlWhen DMBLNK bit (MODE2 register) is programmed with 0, a 190 Hz fixed frequency
signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is
then used as a global brightness control allowing the LED outputs to be dimmed with the
same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 8 outputs is controlled through 256 linear steps from 00h% duty cycle= LED output off) to FFh (99.6 % duty cycle= maximum brightness).
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT0 and LEDOUT1
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(2)
7.3.5 GRPFREQ: Group frequencyGRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK=0.
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT0 and LEDOUT1
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73s).
(3)
Table 8. GRPPWM - Group duty cycle control register (address 0Ah) bit descriptionLegend: * default value.
0Ah GRPPWM 7:0 GDC[7:0] R/W 1111 1111 GRPPWM register
duty cycle GDC 7:0[]
256 ---------------------------=
Table 9. GRPFREQ - Group Frequency register (address 0Bh) bit descriptionLegend: * default value.
0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
global blinking period GFRQ 7:0[] 1+ ---------------------------------------- in ondssec ()=
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.3.6 LEDOUT0 and LEDOUT1: LED driver output state
LDRx= 00 — LED driver x is off (default power-up state).
LDRx= 01 — LED driver x is fully on (individual brightness and group dimming/blinking
not controlled).
LDRx= 10 — LED driver x individual brightness can be controlled through its PWMx
register.
LDRx= 11 — LED driver x individual brightness and group dimming/blinking can be
controlled through its PWMx register and the GRPPWM registers.
7.3.7 SUBADR1 to SUBADR3: I2 C-bus subaddress 1to3Subaddresses are programmable through the I2 C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to 1 in order to have the device acknowledging these addresses (MODE1 register).
Only the 7 MSBs representing the I2 C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to 1, the corresponding I2 C-bus subaddress can be used during either
an I2 C-bus read or write sequence.
Table 10. LEDOUT0 and LEDOUT1- LED driver output state registers (address 0Ch and
0Dh) bit descriptionLegend: * default value.
0Ch LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
0Dh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control
5:4 LDR6 R/W 00* LED6 output state control
3:2 LDR5 R/W 00* LED5 output state control
1:0 LDR4 R/W 00* LED4 output state control
Table 11. SUBADR1to SUBADR3 - I2 C-bus subaddress registers 1to 3 (address 0Eh to
10h) bit descriptionLegend: * default value.
0Eh SUBADR1 7:1 A1[7:1] R/W 1110 001* I2 C-bus subaddress 1 A1[0] R only 0* reserved
0Fh SUBADR2 7:1 A2[7:1] R/W 1110 010* I2 C-bus subaddress 2 A2[0] R only 0* reserved
10h SUBADR3 7:1 A3[7:1] R/W 1110 100* I2 C-bus subaddress 3 A3[0] R only 0* reserved
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.3.8 ALLCALLADR: LED All Call I2 C-bus addressThe LED All Call I2 C-bus address allows all the PCA9634s on the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default
state)). This addressis programmable through theI2 C-bus and canbe used during either
an I2 C-bus read or write sequence. The register address can also be programmed as a
Sub Call.
Only the 7 MSBs representing the All Call I2 C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0). ALLCALLbit=0, the device does not acknowledge the address programmedin register
ALLCALLADR.
7.4 Active LOW output enable inputThe active LOW output enable (OE) pin, allowsto enableor disableall the LED outputsat
the same time.
Whena LOW levelis appliedto OE pin,all the LED outputs are enabled and follow the
output state defined in the LEDOUT register with the polarity defined by INVRT bit
(MODE2 register).
When a HIGH level is applied to OE pin, all the LED outputs are programmed to the
value that is defined by OUTNE[1:0] in the MODE2 register.
The OE pin can be used as a synchronization signal to switch on/off several PCA9634
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can alsobe usedasan external dimming control signal. The frequencyof the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global
blinking is selected (DMBLNK= 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OEasan external dimming control signal when internal global
dimming is selected (DMBLNK= 0, MODE2 register) since it will result in an undefined
dimming pattern.
Table 12. ALLCALLADR - LED All Call I2 C-bus address register (address 11h) bit
descriptionLegend: * default value.
11h ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2 C-bus
address register AC[0] R only 0* reserved
Table 13. LED outputs when OE=1000 1 1 if OUTDRV= 1, high-impedance if OUTDRV=0 0 high-impedance 1 reserved
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.5 Power-on resetWhen power is applied to VDD, an internal power-on reset holds the PCA9634 in a reset
condition until VDD has reached VPOR.At this point, the reset conditionis released and the
PCA9634 registers and I2 C-bus state machine are initialized to their default states (all
zeroes) causingall the channelstobe deselected. Thereafter, VDD mustbe lowered below
0.2 V to reset the device.
7.6 Software ResetThe Software Reset Call (SWRST Call) allowsall the devicesin theI2 C-bustobe resetto
the power-up state value througha specific formattedI2 C-bus command.Tobe performed
correctly, it implies that the I2 C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following: A START command is sent by the I2 C-bus master. The reserved SWRSTI2 C-bus address ‘0000 011’ with the R/Wbit setto‘0’ (write)is
sent by the I2 C-bus master. The PCA9634 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only.If the R/Wbitis setto‘1’ (read),no acknowledgeis returnedto
the I2 C-bus master. Once the SWRST Call address has been sent and acknowledged, the master sends bytes with 2 specific values (SWRST data byte 1 and byte 2): Byte 1= A5h: the PCA9634 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9634 does not acknowledge it. Byte 2= 5Ah: the PCA9634 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9634 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9634 does not acknowledge any more. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sendsa STOP commandto end the SWRST Call:
the PCA9634 then resets to the default value (power-up value) and is ready to be
addressed again within the specified bus free time (tBUF).
TheI2 C-bus master must interpreta non-acknowledge from the PCA9634(at any time)as
a ‘SWRST Call Abort’. The PCA9634 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.7 Using the PCA9634 with and without external driversThe PCA9634 LED output drivers are 5.5 V only tolerant and can sink up to 25 mA at 5V.
If the device needs to drive LEDs to a higher voltage and/or higher current, use of an
external driver is required.
INVRT bit (MODE2 register) can be used to keep the LED PWM control firmware the
same (PWMx and GRPPWM values directly calculated from their respective formulas
and the LED output state determinedby LEDOUT register value) independentlyof the
typeof external driver. Thisbit allows LED output polarity inversion/non-inversion only
when OE=0.
OUTDRVbit (MODE2 register) allows minimizing the amountof external components
required to control the external driver (N-type or P-type device).
[1] Correct configuration when LEDs directly connected to the LEDn outputs (connection to VDD through current limiting resistor).
[2] Optimum configuration when external P-type (PNP , PMOS) driver used.
[3] Optimum configuration when external N-type (NPN, NMOS) driver used.
Table 14. Use of INVRT and OUTDRV based on connection to the LEDn outputs when OE=0When OE= 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver[1] External pull-up or LED current limiting resistor connects LEDn to VDD.
Table 15. Output transistors based on LEDOUT registers, INVRT and OUTDRV bits when OE=0When OE= 1, LED output state is controlled only by OUTNE[1:0] bits (MODE2 register).
LED driver off 0 off off high-Z[1] 1 on off VDD 0 off on VSS 1 off on VSS
LED driver on 0 off on VSS 1 off on VSS 0 off off high-Z[1] 1 on off VDD
Individual
brightness
control 0 off Individual PWM
(non-inverted)
VSS or high-Z[1] 1 Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
VSS or VDD = PWMx value 0 off Individual PWM
(inverted)
high-Z[1]− PWMx value 1 Individual PWM
(inverted)
Individual PWM
(inverted)
VDD or VSS = 1− PWMx value
Individual +
Group
dimming/blinking 0 off Individual+ Group
PWM
(non-inverted)
VSS or high-Z[1]
values 1 Individual PWM
(non-inverted)
Individual PWM
(non-inverted)
VSS or VDD = PWMx or GRPPWM values 0 off Individual+ Group
PWM (inverted)
high-Z[1]− PWMx) or− GRPPWM) values 1 Individual PWM
(inverted)
Individual PWM
(inverted)
VDD or VSS =(1− PWMx) or− GRPPWM) values
NXP Semiconductors PCA9634
8-bit Fm+ I2 C-bus LED driver
7.8 Individual brightness control with group dimming/blinkingA 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED. topof this signal, oneof the following signals canbe superimposed (this signal canbe
applied to the 4 LED outputs):
A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
A programmable frequency signal from 24 Hz to1 ⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
