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PCA9624BS-PCA9624PW
8-bit Fm+ I2C-bus 100 mA 40 V LED driver
1. General descriptionThe PCA9624 is an I2 C-bus controlled 8-bit LED driver optimized for voltage switch
dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output
has its own 8-bit resolution (256 steps) fixed frequency individual PWM controller that
operates at 97 kHz with a duty cycle that is adjustable from 0 % to 99.6 % to allow the
LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps)
group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency
between 24 Hz to once every 10.73 seconds with a duty cycle that is adjustable from 0 %
to 99.6 % that is used to either dim or blink all LEDs with the same value.
Each LED output can be off, on (no PWM control), set at its individual PWM controller
value or at both individual and group PWM controller values. The PCA9624 operates with
a supply voltage range of 2.3 V to 5.5 V and the 100 mA open-drain outputs allow
voltages up to 40V.
The PCA9624 is one of the first LED controller devices in a new Fast-mode Plus (Fm+)
family. Fm+ devices offer higher frequency (up to 1 MHz) and more densely populated
bus operation (up to 4000 pF).
The active LOW Output Enable input pin (OE) blinks all the LED outputs and can be used
to externally PWM the outputs, which is useful when multiple devices need to be dimmed
or blinked together without using software control.
Software programmable LED Group and three Sub Call I2 C-bus addresses allow all or
defined groups of PCA9624 devices to respond to a common I2 C-bus address, allowing
for example, all red LEDs to be turned on or off at the same time or marquee chasing
effect, thus minimizing I2 C-bus commands. Seven hardware address pins allow up to
126 devices on the same bus.
The Software Reset (SWRST) Call allows the master to perform a reset of the PCA9624
through the I2 C-bus, identical to the Power-On Reset (POR) that initializes the registers to
their default state causing the outputs to be set HIGH (LED off). This allows an easy and
quick way to reconfigure all device registers to the same condition.
The PCA9624 and PCA9634 software is identical and if the PCA9624 on-chip 100 mA
NAND FET s do not provide enough current or voltage to drive the LEDs, then the
PCA9634 with larger current or higher voltage external drivers can be used.
PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
Rev. 3 — 6 September 2012 Product data sheet
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
2. Features and benefits 8 LED drivers. Each output programmable at: Off On Programmable LED brightness Programmable group dimming/blinking mixed with individual LED brightness1 MHz Fast-mode Plus compatible I2 C-bus interface with 30 mA high drive capability
on SDA output for driving high capacitive buses 256-step (8-bit) linear programmable brightness per LED output varying from fully off
(default) to maximum brightness using a 97 kHz PWM signal 256-step group brightness control allows general dimming (using a 190 Hz PWM
signal) from fully off to maximum brightness (default) 256-step group blinking with frequency programmable from 24 Hz to 10.73 s and duty
cycle from 0 % to 99.6% Eight open-drain outputs can sink between 0 mA to 100 mA and are tolerant to a
maximum off state voltage of 40 V. No input function. Output state change programmable on the Acknowledge or the STOP Command to
update outputs byte-by-byte or all at the same time (default to ‘Change on STOP’). Active LOW Output Enable (OE) input pin allows for hardware blinking and dimming of
the LEDs 7 hardware address pins allow 126 PCA9624 devices to be connected to the same 2 C-bus and to be individually programmed 4 software programmable I2 C-bus addresses (one LED Group Call address and three
LED Sub Call addresses) allow groups of devices to be addressed at the same time in
any combination (for example, one register used for ‘All Call’ so that all the PCA9624s
on the I2 C-bus can be addressed at the same time and the second register used for
three different addresses so that 1 ⁄3 of all devices on the bus can be addressed at the
same time in a group). Software enable and disable for I2 C-bus address. Software Reset feature (SWRST Call) allows the device to be reset through the 2 C-bus 25 MHz internal oscillator requires no external components Internal power-on reset Noise filter on SDA/SCL inputs No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage (VDD) range of 2.3 V to 5.5V 5.5 V tolerant inputs on non-LED pins 40 C to +85 C operation ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP24, HVQFN24
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
3. Applications RGB or RGBA LED drivers LED status information LED displays LCD backlights Keypad backlights for cellular phones or handheld devices
4. Ordering information
5. Block diagram
Table 1. Ordering informationPCA9624BS 9624 HVQFN24 plastic thermal enhanced very thin quad flat package; leads; 24 terminals; body44 0.85 mm
SOT616-3
PCA9624PW PCA9624PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
6. Pinning information
6.1 Pinning
6.2 Pin description
Table 2. Pin descriptionVSS 1, 7, 12, 13, 18 4, 9, 22, 10, 15[1] power supply supply ground 2 23 I address input 0 3 24 I address input 1 4 1 I address input 2 5 2 I address input 3 6 3 I address input 4
LED0 8 5 O LED driver 0
LED1 9 6 O LED driver 1
LED2 10 7 O LED driver 2
LED3 11 8 O LED driver 3
LED4 14 11 O LED driver 6
LED5 15 12 O LED driver 7
LED6 16 13 O LED driver 8
LED7 17 14 O LED driver 9 19 16 I active LOW output enable 20 17 I address input 5 21 18 I address input 6
SCL 22 19 I serial clock line
SDA 23 20 I/O serial data line
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver[1] HVQFN24 package supply ground is connected to both VSS pins and exposed center pad. VSS pins must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9624”.
7.1 Device addressesFollowing a START condition, the bus master must output the address of the slave it is
accessing.
There are a maximum of 128 possible programmable addresses using the 7 hardware
address pins. Two of these addresses, Software Reset and LED All Call, cannot be used
because their default power-up state is ON, leaving a maximum of 126 addresses. Using
other reserved addresses, as well as any other Sub Call address, will reduce the total
number of possible addresses even further.
7.1.1 Regular I2 C-bus slave addressThe I2 C-bus slave address of the PCA9624 is shown in Figure 4. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
Remark: Using reserved I2 C-bus addresses will interfere with other devices, but only if
the devices are on the bus and/or the bus will be open to other I2 C-bus systems at some
later date. In a closed system where the designer controls the address assignment these
addresses can be used since the PCA9624 treats them like any other address. The
LEDAll Call, Software Rest and PCA9564 or PCA9665 slave address (if on the bus) can
never be used for individual device addresses.
PCA9624 LED All Call address (1110 000) and Software Reset (0000 0110) which are
active on start-up
PCA9564 (0000 000) or PCA9665 (1110 000) slave address which is active on
start-up
‘reserved for future use’ I2 C-bus addresses (0000 011, 1111 1XX)
slave devices that use the 10-bit addressing scheme (1111 0XX)
slave devices that are designed to respond to the General Call address (0000 000)
High-speed mode (Hs-mode) master code (0000 1XX)
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driverThe last bit of the address byte defines the operation to be performed. When set to logic1
a read is selected, while a logic 0 selects a write operation.
7.1.2 LED All Call I2 C-bus address Default power-up value (ALLCALLADR register): E0h or 1110 000
Programmable through I2 C-bus (volatile programming)
At power-up, LED All Call I2 C-bus address is enabled. PCA9624 sends an ACK when
E0h (R/W= 0) or E1h (R/W= 1) is sent by the master.
See Section 7.3.8 “ALLCALLADR, LED All Call I2 C-bus address” for more detail.
Remark: The default LED All Call I2 C-bus address (E0h or 1110 000) must not be used as
a regular I2 C-bus slave address since this address is enabled at power-up. All the
PCA9624s on the I2 C-bus will acknowledge the address if sent by the I2 C-bus master.
7.1.3 LED Sub Call I2 C-bus addresses 3 different I2 C-bus addresses can be used
Default power-up values:
SUBADR1 register: E2h or 1110 001
SUBADR2 register: E4h or 1110 010
SUBADR3 register: E8h or 1110 100
Programmable through I2 C-bus (volatile programming)
At power-up, Sub Call I2 C-bus addresses are disabled. PCA9624 does not send an
ACK when E2h (R/W =0) or E3h (R/W= 1), E4h (R/W= 0) or E5h (R/W =1), or
E8h (R/W= 0) or E9h (R/W= 1) is sent by the master.
See Section 7.3.7 “SUBADR1 to SUBADR3, I2 C-bus subaddress 1to 3” for more detail.
Remark: The default LED Sub Call I2 C-bus addresses may be used as regular I2 C-bus
slave addresses as long as they are disabled.
7.1.4 Software Reset I2 C-bus addressThe address shown in Figure 5 is used when a reset of the PCA9624 needs to be
performed by the master. The Software Reset address (SWRST Call) must be used with
R/W= logic 0. If R/W= logic 1, the PCA9624 does not acknowledge the SWRST. See
Section 7.6 “Software reset” for more detail.
Remark: The Software Reset I2 C-bus address is a reserved address and cannot be used
as a regular I2 C-bus slave address or as an LED All Call or LED Sub Call address.
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.2 Control registerFollowing the successful acknowledgement of the slave address, LED All Call address or
LED Sub Call address, the bus master will send a byte to the PCA9624, which will be
stored in the Control register.
The lowest 5 bits are used as a pointer to determine which register will be accessed
(D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options
(AI[2:0]).
When the Auto-Increment flag is set (AI2= logic 1), the five low order bits of the Control
register are automatically incremented after a read or write. This allows the user to
program the registers sequentially. Four different types of Auto-Increment are possible,
depending on AI1 and AI0 values.
Remark: Other combinations not shown in Table 3 (AI[2:0] = 001, 010, and 011) are
reserved and must not be used for proper device operation.
AI[2:0]= 000 is used when the same register must be accessed several times during a
single I2 C-bus communication, for example, changes the brightness of a single LED. Data
is overwritten each time the register is accessed during a write operation.
AI[2:0]= 100 is used when all the registers must be sequentially accessed, for example,
power-up programming.
AI[2:0]= 101 is used when the 16 LED drivers must be individually programmed with
different values during the same I2 C-bus communication, for example, changing color
setting to another color setting.
Table 3. Auto-Increment options 0 0 no Auto-Increment 0 0 Auto-Increment for all registers. D[4:0] roll over to 00h after the last
register (11h) is accessed. 0 1 Auto-Increment for individual brightness registers only. D[4:0] roll over to
02h after the last register (11h) is accessed. 1 0 Auto-Increment for global control registers only. D[4:0] roll over to 0Ah’
after the last register (0Bh) is accessed. 1 1 Auto-Increment for individual and global control registers only. D[4:0] roll
over to 02h after the last register (0Bh) is accessed.
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driverAI[2:0]= 110 is used when the LED drivers must be globally programmed with different
settings during the same I2 C-bus communication, for example, global brightness or
blinking change.
AI[2:0]= 111 is used when individual and global changes must be performed during the
same I2 C-bus communication, for example, changing a color and global brightness at the
same time.
Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.
When the Control register is written, the register entry point determined by D[4:0] is the
first register that will be addressed (read or write operation), and can be anywhere
between 0 0000 and 1 0001 (as defined in Table 4). When AI[2]= 1, the Auto-Increment
flag is set and the rollover value at which the register increment stops and goes to the next
one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control
register = 1110 0100 (E4h), then the register addressing sequence will be (in
hexadecimal): … 0B02… 0B02… 0B02…0B02 … as long
as the master keeps sending or reading data.
7.3 Register definitions[1] Only D[4:0]=0 0000to1 0001 are allowed and will be acknowledged. D[4:0]=1 0010 to 1 1111 are reserved and will not be
acknowledged.
[2] When writing to the Control register, bit 4 must be programmed with logic 0 for proper device operation.
Table 4. Register summary [1][2]00h 0 0 0 0 0 MODE1 read/write Mode register 1
01h 0 0 0 0 1 MODE2 read/write Mode register 2
02h 0 0 0 1 0 PWM0 read/write brightness control LED0
03h 0 0 0 1 1 PWM1 read/write brightness control LED1
04h 0 0 1 0 0 PWM2 read/write brightness control LED2
05h 0 0 1 0 1 PWM3 read/write brightness control LED3
06h 0 0 1 1 0 PWM4 read/write brightness control LED4
07h 0 0 1 1 1 PWM5 read/write brightness control LED5
08h 0 1 0 0 0 PWM6 read/write brightness control LED6
09h 0 1 0 0 1 PWM7 read/write brightness control LED7
0Ah 0 1 0 1 0 GRPPWM read/write group duty cycle control
0Bh 0 1 0 1 1 GRPFREQ read/write group frequency
0Ch 0 1 1 0 0 LEDOUT0 read/write LED output state 0
0Dh 0 1 1 0 1 LEDOUT1 read/write LED output state 1
0Eh 0 11 10SUBADR1 read/write I2 C-bus subaddress 1
0Fh 0 11 11SUBADR2 read/write I2 C-bus subaddress 2
10h 1 00 00SUBADR3 read/write I2 C-bus subaddress 3
11h 1 0 0 0 1 ALLCALLADR read/write LED All Call I2 C-bus address
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.3.1 Mode register 1, MODE1[1] It takes 500 s max. for the oscillator to be up and running once SLEEP bit has been set to logic 0. Timings
on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the
500 s window.
[2] No blinking or dimming is possible when the oscillator is off.
7.3.2 Mode register 2, MODE2[1] Change of the outputs at the STOP command allows synchronizing outputs of more than one PCA9624.
Applicable to registers from 02h (PWM0) to 08h (LEDOUT) only.
[2]
Remark: If you change these bits from their default values, the device will not perform as expected.
Table 5. MODE1 - Mode register 1 (address 00h) bit descriptionLegend: * default value. AI2 read only 0 Register Auto-Increment disabled. Register Auto-Increment enabled. AI1 read only 0* Auto-Increment bit1=0. Auto-Increment bit1=1. AI0 read only 0* Auto-Increment bit0=0. Auto-Increment bit0=1. SLEEP R/W 0 Normal mode[1] Low power mode. Oscillator off[2] SUB1 R/W 0* PCA9624 does not respond to I2 C-bus subaddress 1. PCA9624 responds to I2 C-bus subaddress 1. SUB2 R/W 0* PCA9624 does not respond to I2 C-bus subaddress 2. PCA9624 responds to I2 C-bus subaddress 2. SUB3 R/W 0* PCA9624 does not respond to I2 C-bus subaddress 3. PCA9624 responds to I2 C-bus subaddress 3. ALLCALL R/W 0 PCA9624 does not respond to LED All Call I2 C-bus
address. PCA9624 responds to LED All Call I2 C-bus address.
Table 6. MODE2 - Mode register 2 (address 01h) bit descriptionLegend: * default value. - read only 0* reserved - read only 0* reserved DMBLNK R/W 0* group control = dimming. group control = blinking. INVRT R/W 0* reserved; write must always be a logic0 OCH R/W 0* outputs change on STOP command[1] outputs change on ACK - R/W 1* reserved; write must always be a logic1[2] - R/W 0* reserved; write must always be a logic0[2] - R/W 1* reserved; write must always be a logic1[2]
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.3.3 PWM0 to PWM7, individual brightness controlA 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through
256 linear steps from 00h (0 % duty cycle = LED output off) to FFh
(99.6% duty cycle= LED output at maximum brightness). Applicable to LED outputs
programmed with LDRx= 10 or 11 (LEDOUT0 to LEDOUT3 registers).
(1)
7.3.4 GRPPWM, group duty cycle controlWhen DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h % duty cycle= LED output off) to FFh (99.6 % duty cycle= maximum brightness).
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT0 to LEDOUT3
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
(2)
Table 7. PWM0to PWM7 - PWM registers 0to 7 (address 02h to 09h) bit descriptionLegend: * default value.
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000* PWM0 Individual Duty Cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000* PWM1 Individual Duty Cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000* PWM2 Individual Duty Cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000* PWM3 Individual Duty Cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000* PWM4 Individual Duty Cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000* PWM5 Individual Duty Cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000* PWM6 Individual Duty Cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000* PWM7 Individual Duty Cycle
Table 8. GRPPWM - Group brightness control register (address 0Ah) bit descriptionLegend: * default value
0Ah GRPPWM 7:0 GDC[7:0] R/W 11111111 GRPPWM register
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.3.5 GRPFREQ, group frequencyGRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK=0.
Applicable to LED outputs programmed with LDRx= 11 (LEDOUT0 to LEDOUT3
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73s).
(3)
7.3.6 LEDOUT0 and LEDOUT1, LED driver output state
LDRx= 00 — LED driver x is off (default power-up state).
LDRx= 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled).
LDRx= 10 — LED driver x individual brightness can be controlled through its PWMx register.
LDRx= 11 — LED driver x individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.
Table 9. GRPFREQ - Group Frequency register (address 0Bh) bit descriptionLegend: * default value.
0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000* GRPFREQ register
Table 10. LEDOUT0 to LEDOUT1 - LED driver output state register (address 0Ch to 0Dh)
bit descriptionLegend: * default value.
0Ch LEDOUT0 7:6 LDR3 R/W 00* LED3 output state control
5:4 LDR2 R/W 00* LED2 output state control
3:2 LDR1 R/W 00* LED1 output state control
1:0 LDR0 R/W 00* LED0 output state control
0Dh LEDOUT1 7:6 LDR7 R/W 00* LED7 output state control
5:4 LDR6 R/W 00* LED6 output state control
3:2 LDR5 R/W 00* LED5 output state control
1:0 LDR4 R/W 00* LED4 output state control
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.3.7 SUBADR1 to SUBADR3, I2 C-bus subaddress 1to3Subaddresses are programmable through the I2 C-bus. Default power-up values are E2h,
E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up
(the corresponding SUBx bit in MODE1 register is equal to 0).
Once subaddresses have been programmed to their right values, SUBx bits need to be
set to logic 1 in order to have the device acknowledging these addresses (MODE1
register).
Only the 7 MSBs representing the I2 C-bus subaddress are valid. The LSB in SUBADRx
register is a read-only bit (0).
When SUBx is set to logic 1, the corresponding I2 C-bus subaddress can be used during
either an I2 C-bus read or write sequence.
7.3.8 ALLCALLADR, LED All Call I2 C-bus addressThe LED All Call I2 C-bus address allows all the PCA9624s on the bus to be programmed
at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default
state)). This address is programmable through the I2 C-bus and can be used during either
an I2 C-bus read or write sequence. The register address can also be programmed as a
Sub Call.
Only the 7 MSBs representing the All Call I2 C-bus address are valid. The LSB in
ALLCALLADR register is a read-only bit (0).
If ALLCALL bit= 0, the device does not acknowledge the address programmed in register
ALLCALLADR.
Table 11. SUBADR1to SUBADR3 - I2 C-bus subaddress registers 0to 3 (address 0Eh to
10h) bit descriptionLegend: * default value.
0Eh SUBADR1 7:1 A1[7:1] R/W 1110 001* I2 C-bus subaddress 1 A1[0] R only 0* reserved
0Fh SUBADR2 7:1 A2[7:1] R/W 1110 010* I2 C-bus subaddress 2 A2[0] R only 0* reserved
10h SUBADR3 7:1 A3[7:1] R/W 1110 100* I2 C-bus subaddress 3 A3[0] R only 0* reserved
Table 12. ALLCALLADR - LED All Call I2 C-bus address register (address 11h)
bit descriptionLegend: * default value.
11h ALLCALLADR 7:1 AC[7:1] R/W 1110 000* ALLCALL I2 C-bus
address register AC[0] R only 0* reserved
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
7.4 Active LOW output enable inputThe active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at
the same time.
When a LOW level is applied to OE pin, all the LED outputs are enabled.
When a HIGH level is applied to OE pin, all the LED outputs are high-impedance.
The OE pin can be used as a synchronization signal to switch on/off several PCA9624
devices at the same time. This requires an external clock reference that provides blinking
period and the duty cycle.
The OE pin can also be used as an external dimming control signal. The frequency of the
external clock must be high enough not to be seen by the human eye, and the duty cycle
value determines the brightness of the LEDs.
Remark: Do not use OE as an external blinking control signal when internal global blinking is selected (DMBLNK= 1, MODE2 register) since it will result in an undefined
blinking pattern. Do not use OE as an external dimming control signal when internal global
dimming is selected (DMBLNK= 0, MODE2 register) since it will result in an undefined
dimming pattern.
Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin.
7.5 Power-on resetWhen power is applied to VDD, an internal power-on reset holds the PCA9624 in a reset
condition until VDD has reached VPOR. At this point, the reset condition is released and the
PCA9624 registers and I2 C-bus state machine are initialized to their default states (all
zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below
0.2 V to reset the device.
7.6 Software resetThe Software Reset Call (SWRST Call) allows all the devices in the I2 C-bus to be reset to
the power-up state value through a specific formatted I2 C-bus command. To be performed
correctly, it implies that the I2 C-bus is functional and that there is no device hanging the
bus.
The SWRST Call function is defined as the following: A START command is sent by the I2 C-bus master. The reserved SWRST I2 C-bus address ‘0000 011’ with the R/W bit set to ‘0’ (write) is
sent by the I2 C-bus master. The PCA9624 device(s) acknowledge(s) after seeing the SWRST Call address
‘0000 0110’ (06h) only. If the R/W bit is set to ‘1’ (read), no acknowledge is returned to
the I2 C-bus master. Once the SWRST Call address has been sent and acknowledged, the master sends bytes with 2 specific values (SWRST data byte 1 and byte2): Byte 1= A5h: the PCA9624 acknowledges this value only. If byte 1 is not equal to
A5h, the PCA9624 does not acknowledge it.
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver Byte 2= 5Ah: the PCA9624 acknowledges this value only. If byte 2 is not equal to
5Ah, then the PCA9624 does not acknowledge it.
If more than 2 bytes of data are sent, the PCA9624 does not acknowledge any more. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and
correctly acknowledged, the master sends a STOP command to end the
SWRST Call: the PCA9624 then resets to the default value (power-up value) and is
ready to be addressed again within the specified bus free time (tBUF).
The I2 C-bus master must interpret a non-acknowledge from the PCA9624 (at any time) as
a ‘SWRST Call Abort’. The PCA9624 does not initiate a reset of its registers. This
happens only when the format of the SWRST Call sequence is not correct.
7.7 Individual brightness control with group dimming/blinkingA 97 kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used
to control individually the brightness for each LED.
On top of this signal, one of the following signals can be superimposed (this signal can be
applied to the 4 LED outputs):
A lower 190 Hz fixed frequency signal with programmable duty cycle (8 bits,
256 steps) is used to provide a global brightness control.
A programmable frequency signal from 24 Hz to 1 ⁄10.73 Hz (8 bits, 256 steps) with
programmable duty cycle (8 bits, 256 steps) is used to provide a global blinking
control.
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure9).
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
9. Bus transactionsNXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driverNXP Semiconductors PCA9624
8-bit Fm+ I2 C-bus 100 mA 40 V LED driver
10. Application design-in information
