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PCA9605D
Simple 2-wire bus buffer
1. General descriptionThe PCA9605 is a monolithic CMOS integrated circuit for bus buffering in applications
including I2 C-bus, SMBus, DDC, PMBus, and other systems based on similar principles.
The buffer extends the bus load limit by buffering both the SCL and SDA lines, allowing
the maximum permissible bus capacitance on both sides of the buffer.
The PCA9605 includes a unidirectional buffer for the clock signal, and a bidirectional
buffer for the data signal. Slave devices which employ clock stretching are therefore not
supported.
In its most basic implementation, the buffer will allow an extended number of slave
devices to be attached to one (or more) master devices. In this case, all master devices
would be positioned on the Sxx_IN side of the PCA9605.
The direction pin (DIR) further enhances this function by allowing the unidirectional clock
signal to be reversed, thus allowing master devices on both sides of the buffer.
The enable (EN) function allows sections of the bus to be isolated. Individual parts of the
system can be brought on-line successively. This means a controlled start-up using a
diverse range of components, operating speeds and loads is easily achieved.
2. Features and benefits Simple impedance isolating buffer for 2-wire buses 30 mA maximum static open-drain pull-down capability supports a wide range of bus
standards Works with I2 C-bus (Standard-mode, Fast-mode, Fast-mode Plus), SMBus (standard
and high power mode), and PMBus Fast switching times allow operation in excess of 1 MHz Enable allows bus segments to be disconnected Hysteresis on inputs provides noise immunity Operating voltages from 2.7 V to 5.5V Very low supply current Uncomplicated characteristics suitable for quick implementation in most common
2-wire bus applications
PCA9605
Simple 2-wire bus buffer
Rev. 1 — 28 February 2011 Product data sheet
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
3. Applications Electronic signs and displays Lighting control (including architectural and stage lighting) Game consoles/boxes Gaming machine networks Building automation TV/projector/monitor interconnection (DDC) Power management systems Desktop and portable computers Security systems Interfacing standard 3 mA I2 C-bus parts to a 30 mA Fm+ bus
4. Ordering information
5. Block diagram
Table 1. Ordering informationPCA9605D PCA9605 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
PCA9605DP 9605 TSSOP8 plastic thin shrink small outline package; 8 leads; body width3 mm SOT505-1
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9605”.
7.1 VDD, VSS — supply pinsThe power supply voltage for the PCA9605 may be any voltage in the range 2.7 V to
5.5 V. The IC supply must be common with the supply for the bus. Hysteresis on the ports
is a percentage of the IC’s power supply, hence noise margin considerations should be
taken into account when selecting an operating voltage.
7.2 SCL_IN, SCL_OUT — clock signal inputs/outputsThe clock signal buffer is unidirectional, although the direction may be reversed under
control of the direction pin (DIR). In normal bus operations, for example the I2 C-bus, the
master device generates a unidirectional clock signal to the slave. For lowest cost, the
PCA9605 combines unidirectional buffering of the clock signal with a bidirectional buffer
for the data signal. Clock stretching is therefore not supported and slave devices that may
require clock stretching must be accommodated by the master adopting an appropriate
Table 2. Pin description 1 enable
SCL_OUT 2 clock buffer, slave side
SCL_IN 3 clock buffer, master side
VSS 4 supply ground
DIR 5 clock direction
SDA_IN 6 data buffer, master side
SDA_OUT 7 data buffer, slave side
VDD 8 positive supply
NXP Semiconductors PCA9605
Simple 2-wire bus bufferclocking when communicating with them. The buffer includes hysteresis to ensure clean
switching signals are output, especially with slow rise times on high capacitively loaded
buses. Output ports are open-drain type and require external pull-up resistors.
7.3 SDA_IN, SDA_OUT — data signal inputs/outputsThe data signal buffer is bidirectional. The port (SDA_IN, SDA_OUT) which first falls
below the ‘lock voltage’ Vlock, will take control of the buffer direction and ‘lock out’ signals
coming from the opposite side. As the ‘input’ signal continues to fall, it will then drive the
‘output’ side LOW. Again, hysteresis is applied to the buffer to minimize the effects of
noise.
At some points during the communication, the data direction will reverse, e.g., when the
slave transmits an acknowledge (ACK), or responds with its register contents. During
these times, the controlling ‘input’ side will have to rise back above the ‘unlock voltage’
(Vunlock) before it releases the ‘lock’, which then allows the ‘output’ side to gain control,
and pull (what was) the ‘input’ side LOW again. This will cause a ‘pulse’ on the ‘input’ side,
which can be quite a long duration in high capacitance buses. However, this pulse will not
interfere with the actual data transmission, as it should not occur during times of clock line
transition (during normal I2 C-bus and SMBus protocols), and thus data signal set-up time
requirements are still met. Ports are open-drain type and require external pull-up resistors.
7.4 Enable (EN) — activate buffer operationsThe active HIGH enable input (EN) can be used to disable the buffer, for the purpose of
isolating sections of the bus. The IC should only be disabled when the bus is idle. This
prevents truncation of commands which may confuse other devices on the bus. Enable
(EN) may also be used to progressively activate sections of the bus during system
start-up. Bus sections slow to respond on power-up can be kept isolated from the main
system to avoid interference and collisions. The pin must be externally driven to a valid
state.
7.5 Direction (DIR) — clock buffer direction controlThe direction input (DIR) is used to change the signal direction of the SCL ports. When the
DIR pin is logic LOW, the clock signal input is SCL_IN and the buffered output is
SCL_OUT. When the DIR pin is logic HIGH, the clock signal input is SCL_OUT and the
buffered output is SCL_IN. The pin must be externally driven to a valid state.
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
8. Limiting values[1] Voltages are specified with respect to pin 4 (VSS).
9. Characteristics
Table 3. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage [1] 0.3 +7 V voltage on any other pin [1] VSS 0.5 VDD +0.5V
II/O input/output current any pin - 50 mA
Ptot total power dissipation - 300 mW
Tstg storage temperature 55 +125 C
Tamb ambient temperature operating 40 +85 C
Table 4. CharacteristicsTamb= 40 C to +85 C; voltages are specified with respect to ground (VSS); VDD= 5.5 V unless otherwise specified.
Power supplyVDD supply voltage operating 2.7 - 5.5 V
IDD supply current quiescent; VDD =VI(EN)= 5.5V --1 A
SCL_IN, SDA_IN = 800 kHz;
VDD =5.5V
[1] -170 - A
Buffer ports (SDA_IN, SCL_IN, SDA_OUT, SCL_OUT)VI2C-bus I2 C-bus voltage - - VDD +0.3 V
VIL LOW-level input voltage VDD =2.7V [2] --0.4 V
VDD =5.5V [2] --0.5 V
VIH HIGH-level input voltage VDD =2.7V [2] 1.2 - - V
VDD =5.5V [2] 2.0 - - V
VI(hys) hysteresis of input voltage VDD =2.7V [2] 80 - - mV
VDD =5.5V [2] 200 - - mV
ILI input leakage current VI2C-bus =VDD or GND 1- +1 A
IO(sink) output sink current LOW-level; VI2C-bus
VOL LOW-level output voltage IOL =30 mA - 80 300 mV
IOL= 100 A- 1 - mV
Pins SDA_IN, SDA_OUT
Vlock direction lock voltage VDD =2.7V [2] --1.3 V
VDD =5.5V [2] --3.0 V
Vunlock direction unlock voltage VDD =2.7V [2] 2.0 - - V
VDD =5.5V [2] 4.8 - - V
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
[1] Guaranteed by design, not subject to test.
[2] Supply voltage dependent; refer to graphs (Figure 5 through Figure 8) for typical trend.
Enable (EN)
Vth(en) enable threshold voltage EN active; VDD =2.7V 2.0 - - V
EN active; VDD =5.5V 4.8 - - V
Vth(dis) disable threshold voltage EN standby; VDD= 2.7V --0.9 V
EN standby; VDD= 5.5V --2.1 V
Vhys hysteresis voltage VDD =2.7V 100 - - mV
VDD =5.5V 200 - - mV
ILI input leakage current VI(EN) = VDD -- 0.1 A
Direction (DIR)
VI(dir) direction input voltage direction SCL_OUT to SCL_IN
VDD =2.7V 2.0 - - V
VDD =5.5V 4.8 - - V
direction SCL_IN to SCL_OUT
VDD= 2.7V - - 0.9 V
VDD= 5.5V - - 2.1 V
Vhys hysteresis voltage VDD =2.7V 100 - - mV
VDD =5.5V 200 - - mV
ILI input leakage current VDIR =VDD -- 0.1 A
Timing characteristics (Figure4) delay time RPU = 200 [1] -70 - ns fall time RPU = 200 [1] -16 - ns
Table 4. Characteristics …continued
Tamb= 40 C to +85 C; voltages are specified with respect to ground (VSS); VDD= 5.5 V unless otherwise specified.
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
9.1 Bidirectional data buffer
The bidirectional data buffer will determine which side has first fallen below Vlock and give
that side of the buffer control over the direction of the buffer. For the purpose of this one
LOW-going pulse, that side now becomes the ‘input’ (be it SDA_IN or SDA_OUT).
When the ‘input’ side falls to near VIL, it will begin to drive the ‘output’ side of the buffer
LOW. It will continue to hold the ‘output’ low until the ‘input’ exceeds VIH at which point the
‘output’ is released and will rise as fast as it is permitted by the load and pull-up to which it
is attached. (Assuming, of course, that the ‘output’ is not otherwise held LOW by some
other device on the bus on that side of the buffer.)
When the ‘input’ side again exceeds Vunlock, it will release its control of the buffer direction.
At this point, if the ‘output’ side was being held LOW (< Vunlock) by another device, it will
immediately gain control and now become the ‘input’. What was the ‘input’ will now
become the ‘output’, and the process will repeat as above, but in the opposite direction.
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
This means that as direction control is handed from one side of the buffer to the other, a
voltage ‘spike’ of about Vunlock volts will appear on the side that was the ‘input’ and
became the ‘output’.
Figure 9 shows clock and data being buffered through the PCA9605. Channel 3 shows
the SDA_IN port, with direction ‘hand over’ spike (upper left corner). The level of the
SDA_OUT port (channel 4) can be seen to increase as it goes from being held LOW by
the buffer, to being held LOW by another device on the bus.
Of course, the information on the SDA line is only latched into an I2 C-bus device on a
clock edge. The spike on the data line does not occur at a time when data is being
latched, and thus the set-up and hold conditions are still met for a valid I2 C-bus
transaction.
Figure 9 also shows a glitch occurring on the SDA_OUT port (upper right corner). A more
drastic example is shown in Figure 10. In this case, the side acting as the ‘input’
(SDA_OUT) is more lightly loaded than the side acting as the ‘output’ (SDA_IN). It
therefore rises quickly to Vunlock level, before the SDA_IN has been able to exceed VIL.
Direction control briefly reverses, and SDA_OUT gets pulled back LOW again until
SDA_IN has exceeded VIH.
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
Figure 11 shows that by choosing an appropriate value of pull-up resistance (or adding
additional load capacitance if that is preferred), the rate of rise of both input and output
can be matched, and the glitch on the rising edge eliminated.
9.2 Operating conditions
A full byte transaction is shown in Figure 12. SDA_IN and SDA_OUT are shown at the top
of the image, and SCL_IN and SCL_OUT are shown at the bottom. The START condition,
address bits, read/write bit, acknowledge bit and STOP condition can all be clearly seen.
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
10. Application information
10.1 Design considerations
Figure 13 shows a typical data transfer through the PCA9605. The PCA9605 has
excellent application to extending loads and providing interfaces to connectors on high
speed microprocessor cards. PCA9605 can operate well in excess of the Fast-mode
400 kHz I2 C-bus specification (Ref. 1), and is compatible with the Fast-mode Plus
specification. Rise times are determined simply by the side of the buffer with the slowest
RC time constant.
Figure 14 shows a typical application for the PCA9605. In most applications there will be a
single master on the Sxx_IN side of the buffer. One or more PCA9605s can be connected
to this master, giving multiple isolated bus sections on which the slaves are located. Each
bus section can have the maximum permissible load capacitance, and this capacitance
will not influence any other bus section.
The master can control the enable (EN) signals such that each bus section can be
independently activated. This allows for slaves sharing the same address to be placed on
different bus sections and thus uniquely addressed.
The enable pin (EN) can similarly be used to interface buses of different operating
frequencies. When certain bus sections are enabled, the system frequency may be limited
by a bus section having a slave device specified only to 400 kHz (Fast-mode). When that
bus section is disabled, the slow slave is isolated and the remaining bus can be run at MHz (Fast-mode Plus).
NXP Semiconductors PCA9605
Simple 2-wire bus buffer
Figure 15 shows the PCA9605 used with masters on both sides of the buffer. More than
one master may be used on the Sxx_IN side of the IC. However, to locate a master on the
Sxx_OUT side and have that master be able to communicate with devices on the Sxx_IN
side, it must either have direct control over the direction pin (DIR) of the PCA9605, or it
must request another controlling master to change the direction. In Figure 15, U4 uses an
IRQ to signal to U2 that requests a direction change. Once in control, it could alternatively
use the bus to signal ‘release of control’.
