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PCA9600D-PCA9600DP
Dual bidirectional bus buffer
1. General descriptionThe PCA9600 is designed to isolate I2 C-bus capacitance, allowing long buses to be
driven in point-to-point or multipoint applications of up to 4000 pF. The PCA9600 is a
higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic interface
between a normal I2 C-bus and a range of other higher capacitance or different voltage
bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side
is compatible with the Fast-mode Plus (Fm+) specifications.
The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface
making it suitable for interfacing with buses that have non I2 C-bus-compliant logic levels
such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels.
The separation of the bidirectional I2 C-bus signals into unidirectional TX and RX signals
enables the SDA and SCL signals to be transmitted via balanced transmission lines
(twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX
signals may be connected together to provide a normal bidirectional signal.
2. Features and benefits Bidirectional data transfer of I2 C-bus signals Isolates capacitance allowing 400 pF on SX/SY side and 4000 pF on TX/TY side TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive
buses1 MHz operation on up to 20 meters of wire (see AN10658) Supply voltage range of 2.5 V to 15 V with I2 C-bus logic levels on SX/SY side
independent of supply voltage Splits I2 C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface
with opto-electrical isolators and similar devices that need unidirectional input and
output signal paths Low power supply current ESD protection exceeds 4500 V HBM per JESD22-A114 and 1400 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8 and TSSOP8 (MSOP8)
PCA9600
Dual bidirectional bus buffer
Rev. 5 — 5 May 2011 Product data sheet
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
3. Applications Interface between I2 C-buses operating at different logic levels (for example, 5 V and
3V or 15V) Interface between I2 C-bus and SMBus (350 μA) standard or Fm+ standard Simple conversion of I2 C-bus SDA or SCL signals to multi-drop differential bus
hardware, for example, via compatible PCA82C250 Interfaces with opto-couplers to provide opto-isolation between I2 C-bus nodes up to
1MHz Long distance point-to-point or multipoint architectures
4. Ordering information
4.1 Ordering options
5. Block diagram
Table 1. Ordering informationPCA9600D SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCA9600DP TSSOP8 plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
Table 2. Ordering optionsPCA9600D PCA9600 −40 °C to +85°C
PCA9600DP 9600 −40 °C to +85°C
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9600”.
The PCA9600 has two identical buffers allowing buffering of SDA and SCL I2 C-bus
signals. Each buffer is made up of two logic signal paths, a forward path from the I2 C-bus
interface, pins SX and SY which drive the buffered bus, and a reverse signal path from the
buffered bus input, pins RX and RY to drive the I2 C-bus interface. These paths:
sense the voltage state of I2 C-bus pins SX (and SY) and transmit this state to pin TX
(and TY respectively), and
sense the state of pins RX and RY and pull the I2 C-bus pin LOW whenever pin RX or
pin RY is LOW.
The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is
identical.
The I2 C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based
systems.
Table 3. Pin description 1 I2 C-bus (SDA or SCL) 2 receive signal 3 transmit signal
GND 4 negative supply voltage 5 transmit signal 6 receive signal 7 I2 C-bus (SDA or SCL)
VCC 8 positive supply voltage
NXP Semiconductors PCA9600
Dual bidirectional bus bufferThe logic threshold voltage levels at SX on this I2 C-bus are independent of the IC supply
voltage VCC. The maximum I2 C-bus supply voltage is 15V.
When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal mA with a VOL of 0.74 V maximum. That guarantees compliance with the Fast-mode 2 C-bus specification for all I2 C-bus voltages greater than 3 V, as well as compliance with
SMBus or other systems that use TTL switching levels.
SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of
typically 300 μA (maximum 1 mA at −40 °C). When selecting the pull-up for the bus at SX,
the sink capability of other connected drivers should be taken into account. Most TTL
devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the
requirement to ensure the 0.8 V TTL LOW.
For Fast-mode I2 C-bus operation, the other connected I2 C-bus parts may have the
minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at −40 °C),
which forms part of the external driver loading. When selecting the pull-up it is necessary
to subtract the SX pin pull-up current, so, worst-case at −40 °C, the allowed pull-up can be
limited (by external drivers) to 2 mA.
When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher
specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA
at VOL=1 V maximum. That 1 V complies with the bus LOW requirement (0.25Vbus) of
any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a
drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at
VOL=1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is
(5.5V− 1V)/7mA=643 Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum
can be met with total bus loading up to 200 pF.
The logic level on RX is determined from the power supply voltage VCC of the chip. Logic
LOW is below 40 % of VCC, and logic HIGH is above 55 % of VCC (with a typical switching
threshold just slightly below half VCC).
TX is an open-collector output without ESD protection diodes to VCC. It may be connected
via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V rating is not
exceeded. It has a larger current sinking capability than a normal I2 C-bus device, being
able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down
capability as well.
A logic LOW is transmitted to TX when the voltage at I2 C-bus pin SX is below 0.425 V. A
logic LOW at RX will cause I2 C-bus pin SX to be pulled to a logic LOW level in accordance
with I2 C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be
looped back to the TX output and cause the buffer to latch LOW.
The LOW level this chip can achieve on the I2 C-bus by a LOW at RX is typically 0.64V
when sinking 1 mA.
If the supply voltage VCC fails, then neither the I2 C-bus nor the TX output will be held
LOW. Their open-collector configuration allows them to be pulled up to the rated
maximum of 15 V even without VCC present. The input configuration on SX and RX also
presents no loading of external signals when VCC is not present.
The effective input capacitance of any signal pin, measured by its effect on bus rise times,
is less than 10 pF for all bus voltages and supply voltages including VCC =0V.
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design does not support this configuration. Bidirectional I2 C-bus signals do not allow any
direction control pin so, instead, slightly different logic LOW voltage levels are used at
SX/SY to avoid latching of this buffer. A ‘regular I2 C-bus LOW’ applied at the RX/RY of a
PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage
level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that
second PCA9600 will not recognize it as a ‘regular I2 C-bus LOW’ and will not propagate it
to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers
that rely on special logic thresholds for their operation, for example P82B96, PCA9511A,
PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, and compatible
with, the normal I2 C-bus logic voltage levels of I2 C-bus master and slave chips, or even
TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX and TY/RY I/O
pins use the standard I2 C-bus logic voltage levels of all I2 C-bus parts. There are no
restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s,
for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the
common bus and the SX/SY side connected to the line card slave devices. For more
details see Application Note AN10658, “Sending I2 C-bus signals via long communication
cables”.
The PCA9600 is a direct upgrade of the P82B96 with the significant differences
summarized in Table4.
Table 4. PCA9600 versus P82B96Supply voltage (VCC) range: 2.5 V to 15V 2 V to 15V
Maximum operating bus voltage
(independent of VCC):V 15V
Typical operating supply current: 5 mA 1 mA
Typical LOW-level input voltage on I2 C-bus
(SX/SY side):
0.5 V over −40 °C to +85°C 0.65 V at 25°C
LOW-level output voltage on I2 C-bus
(SX/SY side;3 mA sink):
0.74 V (max.) over −40 °C to +85°C 0.88 V (typ.) at 25°C
LOW-level output voltage on Fm+ I2 C-bus
(SX/SY side; 7 mA sink): V (max.) n/a
Temperature coefficient of VIL /VOL:0 mV/°C −2mV/°C
Logic voltage levels on SX/SY bus
(independent of VCC):
compatible with I2 C-bus and similar
buses using TTL levels (SMBus, etc.)
compatible with I2 C-bus and similar
buses using TTL levels (SMBus, etc.)
Typical propagation delays: < 100ns < 200ns
TX/RX switching specifications (I2 C-bus
compliant):
yes, all classes including 1 MHz Fm+ yes, all classes including Fm+
RX logic levels with tighter control than 2 C-bus limit of 30 % to 70%:
yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal)
Maximum bus speed: >1 MHz > 400 kHz
ESD rating HBM per JESD22-A114: > 4500V > 3500V
Package: SO8, TSSOP8 (MSOP8) DIP8, SO8, TSSOP8 (MSOP8)
NXP Semiconductors PCA9600
Dual bidirectional bus bufferWhen the device driving the PCA9600 is an I2 C-bus compatible device, then the
PCA9600 is an improvement on the P82B96 as shown in Table 4. There will always be
exceptions however, and if the device driving the bus buffer is not I2 C-bus compatible
(e.g., you need to use the micro already in the system and bit-bang using two GPIO pins)
then here are some considerations that would point to using the P82B96 instead:
When the pull-up must be the weakest one possible. The spec is 200 μA for P82B96,
but it typically works even below that. And if designing for a temperature range −40 °C
up to +60 °C, then the driver when sinking 200 μA only needs to drive a guaranteed
low of 0.55 V. For the PCA9600, over that same temperature range and when sinking
1.3 mA (at −40 °C), the device driving the bus buffer must provide the required low of
0.425V.
When the lower operating temperature range is restricted (say 0 °C). The P82B96
larger SX voltage levels then make a better typical match with the driver, even when
the supply is as low as 3.3V.
For an I2 C-bus compliant driver on 3.3 V the P82B96 is required to guarantee a bus
low that is below 0.83 V. P82B96 guarantees that with a 200 μA pull-up.
When the operating temperature range is restricted at both limits. An I2 C driver's
typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even
at +60 °C, so there is a reasonable margin. The PCA9600 requires a typical input low
of 0.5 V so its typical margin is smaller. At 0 °C the driver requires a typical input low
of 1.16 V and P82B96 provides 0.75 V, so again the typical margin is already quite big
and even though PCA9600 is better, providing 0.7 V, that difference is not big.
8. Limiting values[1] See also Section 10.2 “Negative undershoot below absolute minimum value”.
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to pin GND.
VCC supply voltage VCC to GND −0.3 +18 V
VI2C-bus I2 C-bus voltage SX and SY; 2 C-bus SDA or SCL −0.3 +18 V output voltage TX and TY;
buffered output
[1] −0.3 +18 V input voltage RX and RY;
receive input
[1] −0.3 +18 V
II2C-bus I2 C-bus current SX and SY; 2 C-bus SDA or SCL 250 mA
Ptot total power dissipation - 300 mW junction temperature operating range −40 +125 °C
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
9. CharacteristicsTable 6. CharacteristicsTamb= −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15V
unless otherwise specified. Typical values are measured at VCC=5 V and Tamb =25 °C.
Power supplyVCC supply voltage operating 2.5 - 15 V
ICC supply current VCC=5 V; buses HIGH - 5.2 6.75 mA
VCC=15 V; buses HIGH - 5.5 7.3 mA
ΔICC additional supply current per TX/TY output driven LOW;
VCC =5.5V
-1.4 3.0 mA
Bus pull-up (load) voltages and currentsPins SX and SY; I2 C-bus input voltage open-collector; RX and RY HIGH - - 15 V output voltage open-collector; RX and RY HIGH - - 15 V output current static; VSX = VSY = 0.4V [1] 0.3 - 2 mA
IO(sink) output sink current dynamic; VSX = VSY = 1V; and RY LOW
715 - mA leakage current VSX = VSY = 15V; andRY HIGH
--10 μA
Pins TX and TY output voltage open-collector - - 15 V
Iload load current maximum recommended on
buffered bus; VTX =VTY =0.4V;
SX and SY LOW on 2 C-bus= 0.4V
--30 mA output current from buffered bus;
VTX =VTY=1 V; SX and SY LOW
on I2 C-bus= 0.4V 130 - mA leakage current on buffered bus;
VTX =VTY =VCC=15 V; SX and HIGH
--10 μA
Input currents input current from I2 C-bus on SX and SY
RX and RY HIGHor LOW; and SY LOW≤ 1V
[1]- −0.3 −1mA
RX and RY HIGH; SX and HIGH> 1.4V
[1] --10 μA
from buffered bus on RX and RY;
SX and SY HIGHor LOW;
VRX =VRY =0.4V
[2]- −1.5 −10 μA leakage current on buffered bus input on RX and
RY; VRX = VRY =15V
--10 μA
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
Output logic LOW levelPins SX and SY
VOL LOW-level output voltage on Standard-mode or Fast-mode 2 C-bus
ISX =ISY = 3 mA; Figure6 - 0.7 0.74 V
ISX =ISY = 0.3 mA; Figure5 - 0.6 0.65 V
on 5 V Fm+ I2 C-bus
ISX =ISY = 7 mA --1 V
ΔV/ΔT voltage variation with temperature ISX =ISY = 0.3mAto3mA - 0 - %/K
Input logic switching threshold voltagesPins SX and SY
VIL LOW-level input voltage on normal I2 C-bus; Figure7 [3] --425 mV
Vth(IH) HIGH-level input threshold voltage on normal I2 C-bus; Figure8 580 --mV
ΔV/ΔT voltage variation with temperature - 0 - %/K
Pins RX and RY
VIH HIGH-level input voltage fraction of applied VCC 0.55VCC --V
Vth(i) input threshold voltage fraction of applied VCC -0.48VCC -V
VIL LOW-level input voltage fraction of applied VCC --0.4VCC V
Logic level threshold difference voltage difference SX and SY; SX output LOW at
0.3 mAto SX input HIGH
maximum
[4] 50 --mV
Thermal resistanceRth(j-pcb) thermal resistance from junction to
printed-circuit board
SOT96-1 (SO8); average lead
temperature at board interface
-127 -K/W
Bus release on VCC failureVCC supply voltage SX, SY , TX and TY; voltage at
which all buses are to be released
at 25°C
--1 V
ΔV/ΔT voltage variation with temperature Figure9 - −4- %/K
Table 6. Characteristics …continuedTamb= −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15V
unless otherwise specified. Typical values are measured at VCC=5 V and Tamb =25 °C.
NXP Semiconductors PCA9600
Dual bidirectional bus buffer[1] This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink capability
(see VOL under sub-section “Output logic LOW level”). The maximum static sink current for a Standard/Fast-mode I2C-bus is 3 mA and
PCA9600 is guaranteed to sink 3 mA at SX/SY when its pins are holding the bus LOW. However, when an external device pulls the
SX/SY pins below 1.4 V, the PCA9600 may source a current between 0 mA and 1 mA maximum. When that other external device is
driving LOW it will pull the bus connected to SX or SY down to, or below, the 0.4 V level referenced in the I2C-bus specification and in
these test conditions. Then that device must be able to sink up to 1 mA coming from SX/SY plus the usual pull-up current. Therefore the
external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/SY as a function of junction
temperature are shown in Figure 10, and the equivalent circuit at the SX/SY interface is shown in Figure4.
[2] Valid over temperature for VCC≤5 V. At higher VCC, this current may increase to maximum −20 μA at VCC =15V.
[3] The input logic threshold is independent of the supply voltage.
[4] The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for VSX output LOW will always exceed
the maximum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any
IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of
another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked
because the resulting system would be very susceptible to induced noise and would not support all I2C-bus operating modes.
[5] The fall time of VTX from 5 V to 2.5 V in the test is approximately 10ns.
The fall time of VSX from 5 V to 2.5 V in the test is approximately 20ns.
The rise time of VTX from 0 V to 2.5 V in the test is approximately 15ns.
The rise time of VSX from 0.7 V to 2.5 V in the test is approximately 25ns.
Buffer response time[5]VCC = 5 V; pin TX pull-up resistor= 160 Ω; pin SX pull-up resistor= 2.2 kΩ; no capacitive load delay time VSX to VTX, VSY to VTY; on falling
input between VSX= input
switching threshold, and VTX
output falling to 50 % VCC
-50 - ns
VSX to VTX, VSY to VTY; on rising
input between VSX= input
switching threshold, and VTX
output reaching 50 % VCC
-60 - ns
VRX to VSX, VRY to VSY; on falling
input between VRX= input
switching threshold, and VSX
output falling to 50 % VCC
-100 -ns
VRX to VSX, VRY to VSY; on rising
input between VRX= input
switching threshold, and VSX
output reaching 50 % VCC
-95 - ns
Input capacitance input capacitance effective input capacitance of any
signal pin measured by
incremental bus rise times;
guaranteed by design, not
production tested
--10 pF
Table 6. Characteristics …continuedTamb= −40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC= 2.5 V to 15V
unless otherwise specified. Typical values are measured at VCC=5 V and Tamb =25 °C.
NXP Semiconductors PCA9600
Dual bidirectional bus bufferNXP Semiconductors PCA9600
Dual bidirectional bus buffer
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
10. Application informationRefer to PCA9600 data sheet and application notes AN10658 and AN255 for more
detailed application information.
NXP Semiconductors PCA9600
Dual bidirectional bus bufferFor more examples of faster alternatives for driving over longer cables such as Cat5
communication cable, see AN10658. Communication at 1 MHz is possible over short
cables and > 400 kHz is possible over 50 m of cable.
Table 7. Examples of bus capabilityRefer to Figure 14. 12 5 750 2.2 400 250 n/a
(delay based)
1.25μs 600 3850 125 normal
specification
400 kHz parts 12 5 750 2.2 220 100 n/a
(delay based)
500ns 600 2450 195 normal
specification
400 kHz parts
3.3 5 3.3 330 1 220 25 1nF 125ns 260 770 620 meets Fm+
specification
3.3 5 3.3 330 1 100 3 120pF 15ns 260 720 690 meets Fm+
specification
NXP Semiconductors PCA9600
Dual bidirectional bus buffer
10.1 Calculating system delays and bus clock frequencyNXP Semiconductors PCA9600
Dual bidirectional bus bufferFigure 15, Figure 16, and Figure 17 show the PCA9600 used to drive extended bus wiring
with relatively large capacitances linking two I2 C-bus nodes. It includes simplified
expressions for making the relevant timing calculations for 3.3 V or 5 V operation.
Because the buffers and the wiring introduce timing delays, it may be necessary to
decrease the nominal SCL frequency. In most cases the actual bus frequency will be
lower than the nominal Master timing due to bit-wise stretching of the clock periods.
The delay factors involved in calculation of the allowed bus speed are:
A — The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is that of the falling edge of SCL because this edge ‘requests’
the data or acknowledge from a slave. See Figure 15.
B — The effective stretching of the nominal LOW period of SCL at the master caused by the buffer and bus rise times. See Figure 16.
C — The propagation delay of the slave's response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising
edges are always slower and are therefore delayed by a longer time than falling edges.
(The rising edges are limited by the passive pull-up while falling edges are actively
driven); see Figure 17.
The timing requirement in any I2 C-bus system is that a slave's data response (which is
provided in response to a falling edge of SCL) must be received at the master before the
end of the corresponding LOW period of SCL as appears on the bus wiring at the master.
Since all slaves will, as a minimum, satisfy the worst case timing requirements of their
speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the
set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm+
parts. In systems that introduce additional delays it may be necessary to extend the
minimum clock LOW period to accommodate the ‘effective’ delay of the slave's response.
The effective delay of the slave’s response equals the total delays in SCL falling edge
NXP Semiconductors PCA9600
Dual bidirectional bus bufferfrom the master reaching the slave (Figure 15) minus the effective delay (stretch) of the
SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on
SDA, reaching the master (Figure 17).
The master microcontroller should be programmed to produce a nominal SCL LOW
period as follows:
(1)
The actual LOW period will become (the programmed value+ the stretching time B).
When this actual LOW period is then less than the specified minimum, the specified
minimum should be used.
Example 1:It is required to connect an Fm+ slave, with Rs× Cs product of 100 ns, to a 5V
Fast-mode system also having 100 ns Rm× Cm using two PCA9600’s to buffer a 5V
bus with 4 nF loading and 160 Ω pull-up.
Calculate the allowed bus speed:
Delay A = 120 + 85 + (2.5 + [4× 4]) × 5 + 50= 347.5ns
Delay B = 115 + 100 + 70= 285ns
Delay C = 115 + 20 + 0.7(100 + 100)= 275ns
The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW
period is calculated as:
LOW≥ 450 + 347.5 − 285 + 275 + 100= 887.5ns
The actual LOW period will be 887.5 + 285= 1173 ns, which is below the Fast-mode
minimum, so the programmed LOW period must be increased to
(1300− 285)= 1015 ns, so the actual LOW equals the 1300 ns requirement and this
shows that this Fast-mode system may be safely run to its limit of 400 kHz.
Example 2:It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability,
to an Fm+ bus. All the system operates at 3.3 V. The Master Rm× Cm product is 50 ns.
Only one PCA9600 is used. The Fm+ bus becomes the buffered bus. The Fm+ bus has
200 pF loading and 150 Ω pull-up, so its Rb× Cb product is 30 ns. The Fm+ slave has a
specified data valid time tVD;DAT maximum of 300 ns.
Calculate the allowed maximum system bus speed. (Note that the fixed values in the
delay equations represent the internal propagation delays of the PCA9600. Only one
PCA9600 is used here, so those fixed values used below are taken from the
characteristics.)
The delays are:
Delay A = 40 + 56 + (2.5 + [4× 0.2]) × 3.3 = 107ns
Delay B = 115 + 50 + 21 = 186ns
Delay C = 70 + 0.7(50 + 30) = 126ns
The programmed LOW period is calculated as:
SCL LOW ≥ 300 + 117 − 186 + 126 + 50 = 407ns
SCL LOW slave response delay to valid data on its SDA AB C data set-up time++–+( )≥ ns
