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PCA9575HF-PCA9575PW1-PCA9575PW2
16-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt
General descriptionThe PCA9575 is a CMOS device that provides 16 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2 C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, separate supply rails to allow voltage level translation anywhere between
1.1V and 3.6V, 400 kHz clock frequency, and smaller packaging. Anyof the16 I/O ports
canbe configuredasan inputor output independentof each other and defaulton start-up
to inputs.
I/O expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum; for example in battery powered mobile applications and
clamshell devices for interfacing to sensors, push buttons, keypad, etc. In addition to
providing a flexible set of GPIOs, it simplifies interconnection of a processor running at
one voltage level to I/O devices operating at a different (usually higher) voltage level.
PCA9575 has built-in level shifting feature that makes these devices extremely flexible in
mixed signal environments where communication between incompatible I/Os is required.
The core of PCA9575 can operate at a voltage as low as 1.1 V while each I/O bank can
operate in the range 1.1 V to 3.6 V. Bus hold with programmable on-chip pull-up or
pull-down feature for I/Os is also provided.
The output stage consists of two banks each of 8-bit configuration registers, input
registers, interrupt mask registers, output registers, bus-hold and pull-up/pull-down
registers and polarity inversion registers. These registers allow the system master to
program and configure 16 GPIOs through the I2 C-bus.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Inputor Output register. The polarityof the read registers canbe inverted with the Polarity
Inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is
asserted each time a change occurs on an input port unless that port is masked
(default= masked). A ‘GPIO All Call’ command allows programming multiple PCA9575s
at the same time even if they have different individual I2 C-bus addresses. This allows
optimal code programming when more than one device needstobe programmed with the
same instructionorifall outputs needtobe turnedonoroffat the same time. The internal
PCA9575
16-bitI2 C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 03 — 9 November 2009 Product data sheet
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIOPower-On Reset (POR)or hardware reset pin (RESET) initializes the two banksof8 I/Os inputs, sets the registersto their default values and initializes the device state machine.
The I/O banks are held in its default state when the logic supply (VDD) is off.
The PCA9575 is available in 24-pin TSSOP , 28-pin TSSOP and HWQFN24 packages,
and is specified over the −40 °C to +85 °C industrial temperature range.
The 28-pin package provides four address select pins, allowing up to 16 PCA9575
devices to be connected with 16 different addresses on the same I2 C-bus.
Features Separate supply rails for core logic and each of the two I/O banks provides voltage
level shifting 1.1 V to 3.6 V operation with level shifting feature Very low standby current: <2 μA 16 configurable I/O pins organized as 2 banks that default to inputs at power-up Outputs: Totem pole: 1 mA source and 3 mA sink Independently programmable 100 kΩ pull-up or pull-down for each I/O pin Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs Inputs: Programmable bus hold provides valid logic level when inputs are not actively
driven Programmable Interrupt Mask Controlfor input pins thatdo not requirean interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up Polarity Inversion register allows inversion of the polarity of the I/O pins when read 400 kHz I2 C-bus serial interface Compliant with I2 C-bus Standard-mode (100 kHz) Active LOW reset (RESET) input pin resets device to power-up default state GPIO All Call address allows programming of more than one device at the same time
with the same parameters 16 programmable slave addresses using 4 address pins (28-pin TSSOP only) −40 °C to +85 °C operation ESD protection exceeds 6000 V HBM per JESD22-A114, 500 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP28, TSSOP24, HWQFN24
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO Applications Cell phones Media players Multi-voltage environments Battery operated mobile gadgets Motherboards Servers RAID systems Industrial control Medical equipment PLCs Gaming machines Instrumentation and test measurement
Ordering information
Table 1. Ordering informationPCA9575PW2 PCA9575PW2 TSSOP28 plastic thin shrink small outline package; 28 leads;
body width 4.4 mm
SOT361-1
PCA9575PW1 PA9575PW1 TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9575HF 575F HWQFN24 plastic thermal enhanced very very thin quad flat package; leads; 24 terminals; body4×4× 0.75 mm
SOT994-1
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO Block diagram
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO Pinning information
6.1 Pinning
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
6.2 Pin description[1] HWQFN24 packagedie supply groundis connectedto both VSSpin and exposed center pad. VSSpin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal padthe board andfor proper heat conduction throughthe board, thermal vias needtobe incorporatedinthe
PCB in the thermal pad region.
Table 2. Pin description 1 - - I address input 0
VDD 2 1 22 power supply supply voltage
RESET 3 2 23 I active LOW reset input
P0_0 4 3 24 I/O port 0 input/output 0
P0_1 5 4 1 I/O port 0 input/output 1
P0_2 6 5 2 I/O port 0 input/output 2
P0_3 7 6 3 I/O port 0 input/output 3 8 - - I address input 1
VDD(IO)0 9 7 4 power supply I/O supply voltage for bank0
P0_4 10 8 5 I/O port 0 input/output 0
P0_5 11 9 6 I/O port 0 input/output 1
P0_6 12 10 7 I/O port 0 input/output 2
P0_7 13 11 8 I/O port 0 input/output 3
INT 14 12 9 O interrupt output (open-drain;
active LOW) 15 - - I address input 2
VSS 16 13 10[1] ground supply ground
P1_7 17 14 11 I/O port 1 input/output 4
P1_6 18 15 12 I/O port 1 input/output 5
P1_5 19 16 13 I/O port 1 input/output 6
P1_4 20 17 14 I/O port 1 input/output 7
VDD(IO)1 21 18 15 power supply I/O supply voltage for bank1 22 - - I address input 3
P1_3 23 19 16 I/O port 1 input/output 3
P1_2 24 20 17 I/O port 1 input/output 2
P1_1 25 21 18 I/O port 1 input/output 1
P1_0 26 22 19 I/O port 1 input/output 0
SDA 27 23 20 I/O serial data line
SCL 28 24 21 I serial clock line
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO Functional description
7.1 I/O portsThe 16 I/O ports are organized as two banks of 8 ports each. The system master can
enable the I/Os as either inputs or outputs by writing to the I/O configuration register bits.
The datafor each inputor outputis keptin the corresponding Inputor Output register. The
polarity of the read register can be inverted with the Polarity Inversion register. Either a
bus-hold function or pull-up/pull-down feature can be selected by programming
corresponding registers. A bus-hold provides a valid logic level when the I/O bus is not
actively driven. It consists of a pair of buffers, one being weak (low drive-strength), that
latch the inputat the last driven value. This prevents the input from floating whileitis being
driven by a 3-state output. Latching the last valid logic state of input prevents it from
settlingata midpoint between VDD and ground thatin turn consumes power. An active bus
driver can easily override the logic level set by the bus-keeper.
When bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
7.2 Device addressFollowing a START condition, the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). Address configuration for
the device depends on the package type chosen. The device offered in a 24-pin package
will have a fixed slave address for the PCA9575 as shown in Figure6.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while logic 0 selects a write operation.
The slave address for the 28-pin version of the PCA9575 is shown in Figure7.
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.3 Command registerFollowing the successful acknowledgementof the slave address+ R/W bit, the bus master
will send a byte to the PCA9575, which will be stored in the Command register.
The lowest4 bits are usedasa pointerto determine which register willbe accessed. Only Command register code with the4 least significant bits equalto the16 allowable values
as defined in Table 3 “Register summary” will be acknowledged. Reserved or undefined
command codes will notbe acknowledged.At power-up, this register defaultsto 00h, with
the AI bit set to logic 0, and the lowest 4 bits set to logic0.
If the Auto-Increment flag is set (AI= 1), the 4 least significant bits of the Command
register are automatically incremented after a read or write. This allows the user to
program and/or read the 16 command registers (listed in Table 3) sequentially. It will then
roll overto register 00h after the last registeris accessed and the selected registers willbe
overwritten or re-read.
If the Auto-Increment flag is cleared (AI= 0), the 4 least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.4 Register definitions
Table 3. Register summary00h 0 0 0 0 IN0 read only Input port 0 register
01h 0 0 0 1 IN1 read only Input port 1 register
02h 0 0 1 0 INVRT0 read/write Polarity inversion port 0 register
03h 0 0 1 1 INVRT1 read/write Polarity inversion port 1 register
04h 0 1 0 0 BKEN0 read/write Bus-hold enable 0 register
05h 0 1 0 1 BKEN1 read/write Bus-hold enable 1 register
06h 0 1 1 0 PUPD0 read/write Pull-up/pull-down selector port 0 register
07h 0 1 1 1 PUPD1 read/write Pull-up/pull-down selector port 1 register
08h 1 0 0 0 CFG0 read/write Configuration port 0 register
09h 1 0 0 1 CFG1 read/write Configuration port 1 register
0Ah 1 0 1 0 OUT0 read/write Output port 0 register
0Bh 1 0 1 1 OUT1 read/write Output port 1 register
0Ch 1 1 0 0 MSK0 read/write Interrupt mask port 0 register
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.5 Writing to port registersData is transmitted to the PCA9575 by sending the device address and setting the least
significant bit to logic 0 (see Figure 6 or Figure 7 for device address). The command byte
is sent after the address and determines which register will receive the data following the
command byte. Each 8-bit register may be updated independently of the other registers.
7.6 Reading the port registersIn order to read data from the PCA9575, the bus master must first send the PCA9575
address with the least significant bit set to a logic 0 (see Figure 6 or Figure 7 for device
address). The command byteis sent after the address and determines which register will
be accessed. After a restart, the device address is sent again but this time, the least
significant bit is set to logic 1. Data from the register defined by the command byte will
then be sent by the PCA9575. Data is clocked into the register on the falling edge of the
acknowledge clock pulse. After the first byte is read, additional bytes may be read using
the auto-increment feature.
7.6.1 Register 0 - Input port 0 registerThis register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pinis definedasan inputoran outputby the Configuration register. Writesto
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
0Dh 1 1 0 1 MSK1 read/write Interrupt mask port 1 register
0Eh 1 1 1 0 INTS0 read only Interrupt status port 0 register
0Fh 1 1 1 1 INTS1 read only Interrupt status port 1 register
Table 3. Register summary …continued
Table 4. Register 0 - Input port 0 register (address 00h) bit description IO0.7 read only X determined by externally applied logic level IO0.6 read only X IO0.5 read only X IO0.4 read only X IO0.3 read only X IO0.2 read only X IO0.1 read only X IO0.0 read only X
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.2 Register 1 - Input port 1 registerThis register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pinis definedasan inputoran outputby the Configuration register. Writesto
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
7.6.3 Register 2 - Polarity inversion port 0 registerThis register allows the user to invert the polarity of the Input port register data. If a bit in
this registeris set (written with ‘1’), the corresponding Input port datais inverted.Ifabitin
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Register 1 - Input port 1 register (address 01h) bit description IO1.7 read only X determined by externally applied logic level IO1.6 read only X IO1.5 read only X IO1.4 read only X IO1.3 read only X IO1.2 read only X IO1.1 read only X IO1.0 read only X
Table 6. Register 2 - Polarity Inversion port 0 register (address 02h) bit descriptionLegend: * default value. N0.7 R/W 0* inverts polarity of Input port 0 register data
0 = Input port 0 register data retained (default value)
1 = Input port 0 register data inverted N0.6 R/W 0* N0.5 R/W 0* N0.4 R/W 0* N0.3 R/W 0* N0.2 R/W 0* N0.1 R/W 0* N0.0 R/W 0*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.4 Register 3 - Polarity inversion port 1 registerThis register allows the user to invert the polarity of the Input port register data. If a bit in
this registeris set (written with ‘1’), the corresponding Input port datais inverted.Ifabitin
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
7.6.5 Register 4 - Bus-hold/pull-up/pull-down enable 0 registerBit0of this register allows the userto enable/disable the bus-hold featurefor the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 0. In this mode, the
pull-up/pull-downs will be disabled for I/O bank 0. Setting the bit 0 to logic 0 disables
bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting thebit1to logic1 enables selectionof pull-up/pull-down using Register6. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 0 pins and contents of
Register 6 will have no effect on the I/O.
Table 7. Register 3 - Polarity Inversion port 1 register (address 03h) bit descriptionLegend: * default value. N1.7 R/W 0* inverts polarity of Input port 1 register data
0 = Input port 1 register data retained (default value)
1 = Input port 1 register data inverted N1.6 R/W 0* N1.5 R/W 0* N1.4 R/W 0* N1.3 R/W 0* N1.2 R/W 0* N1.1 R/W 0* N1.0 R/W 0*
Table 8. Register 4 - Bus-hold/pull-up/pull-down enable 0 register (address 04h)
bit descriptionLegend: * default value. E0.7 R/W X not used E0.6 R/W X E0.5 R/W X E0.4 R/W X E0.3 R/W X E0.2 R/W X E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O bank 0 pins
0 = disables pull-up/pull-downs on the I/O bank 0 pins and
contents of Register 6 will have no effect on the I/O bank0
(default value)
1 = enables selection of pull-up/pull-down using Register6 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the
I/O bank 0 pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.6 Register 5 - Bus-hold/pull-up/pull-down enable 1 registerBit0of this register allows the userto enable/disable the bus-hold featurefor the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank 1. In this mode, the
pull-up/pull-downs will be disabled for I/O bank 1. Setting the bit 0 to logic 0 disables
bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting thebit1to logic1 enables selectionof pull-up/pull-down using Register7. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O bank 1 pins and contents of
Register 7 will have no effect on the I/O.
Table 9. Register 5 - Bus-hold/pull-up/pull-down enable 1 register (address 05h)
bit descriptionLegend: * default value. E1.7 R/W X not used E1.6 R/W X E1.5 R/W X E1.4 R/W X E1.3 R/W X E1.2 R/W X E1.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O bank 1 pins
0 = disables pull-up/pull-downs on the I/O bank 1 pins and
contents of Register 7 will have no effect on the I/O bank0
(default value)
1 = enables selection of pull-up/pull-down using Register7 E1.0 R/W 0* allows user to enable/disable the bus-hold feature for the
I/O bank 1 pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.7 Register 6 - Pull-up/pull-down select port 0 registerWhen bus-hold feature is not selected and bit 1 of Register 4 is set to logic 1, the I/O
port 0 can be configured to have pull-up or pull-down by programming the
pull-up/pull-down register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for
that I/O pin. Settingabitto logic0 will selecta 100 kΩ pull-down resistorfor that I/O pin.If
the bus-hold feature is enabled, writing to this register will have no effect on
pull-up/pull-down selection.
7.6.8 Register 7 - Pull-up/pull-down select port 1 registerWhen bus-hold feature is not selected and bit 1 of Register 5 is set to logic 1, the I/O
port 1 can be configured to have pull-up or pull-down by programming the
pull-up/pull-down register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for
that I/O pin. Settingabitto logic0 will selecta 100 kΩ pull-down resistorfor that I/O pin.If
the bus-hold feature is enabled, writing to this register will have no effect on
pull-up/pull-down selection.
Table 10. Register 6 - Pull-up/pull-down select port 0 register (address 06h) bit descriptionLegend: * default value. P0.7 R/W 1* configures I/O port 0 pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 4 is logic1
0 = selects a 100 kΩ pull-down resistor for that I/O pin= selectsa 100kΩ pull-up resistorfor thatI/Opin (default
value) P0.6 R/W 1* P0.5 R/W 1* P0.4 R/W 1* P0.3 R/W 1* P0.2 R/W 1* P0.1 R/W 1* P0.0 R/W 1*
Table 11. Register 7 - Pull-up/pull-down select port 1 register (address 07h) bit descriptionLegend: * default value. P1.7 R/W 1* configures I/O port 1 pin to have pull-up or pull-down when
bus-hold feature not selected andbit1of Register5is logic1
0 = selects a 100 kΩ pull-down resistor for that I/O pin= selectsa 100kΩ pull-up resistorfor that I/Opin (default
value) P1.6 R/W 1* P1.5 R/W 1* P1.4 R/W 1* P1.3 R/W 1* P1.2 R/W 1* P1.1 R/W 1* P1.0 R/W 1*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.9 Register 8 - Configuration port 0 registerThis register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port 0 pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding
port 0 pin is enabled as an output. At reset, the device’s ports are inputs.
7.6.10 Register 9 - Configuration port 1 registerThis register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port 1 pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding
port 1 pin is enabled as an output. At reset, the device’s ports are inputs.
Table 12. Register 8 - Configuration port 0 register (address 08h) bit descriptionLegend: * default value. C0.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value) C0.6 R/W 1* C0.5 R/W 1* C0.4 R/W 1* C0.3 R/W 1* C0.2 R/W 1* C0.1 R/W 1* C0.0 R/W 1*
Table 13. Register 9 - Configuration port 1 register (address 09h) bit descriptionLegend: * default value. C1.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value) C1.6 R/W 1* C1.5 R/W 1* C1.4 R/W 1* C1.3 R/W 1* C1.2 R/W 1* C1.1 R/W 1* C1.0 R/W 1*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.11 Register 10 - Output port 0 registerThis register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 8. Bit values in this register have no effect on pins defined as
inputs.In turn, reads from this register reflect the value thatisin the flip-flop controlling the
output selection,
not the actual pin value.
7.6.12 Register 11 - Output port 1 registerThis register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 9. Bit values in this register have no effect on pins defined as
inputs.In turn, reads from this register reflect the value thatisin the flip-flop controlling the
output selection,
not the actual pin value.
Table 14. Register 10 - Output port 0 register (address 0Ah) bit descriptionLegend: * default value. O0.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 86 O0.6 R/W 0* O0.5 R/W 0* O0.4 R/W 0* O0.3 R/W 0* O0.2 R/W 0* O0.1 R/W 0* O0.0 R/W 0*
Table 15. Register 11 - Output port 1 register (address 0Bh) bit descriptionLegend: * default value. O1.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 96 O1.6 R/W 0* O1.5 R/W 0* O1.4 R/W 0* O1.3 R/W 0* O1.2 R/W 0* O1.1 R/W 0* O1.0 R/W 0*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.13 Register 12 - Interrupt mask port 0 registerAll the bits of Interrupt mask port 0 register are set to logic 1 upon power-on or software
reset, thus disabling interrupts. Interrupts maybe enabledby setting corresponding mask
bits to logic0.
7.6.14 Register 13 - Interrupt mask port 1 registerAll the bits of Interrupt mask port 1 register are set to logic 1 upon power-on or software
reset, thus disabling interrupts. Interrupts maybe enabledby setting corresponding mask
bits to logic0.
Table 16. Register 12 - Interrupt mask port 0 register (address 0Ch) bit descriptionLegend: * default value. M0.7 R/W 1* enable or disable interrupts
0 = enable interrupt
1 = disable interrupt (default value) M0.6 R/W 1* M0.5 R/W 1* M0.4 R/W 1* M0.3 R/W 1* M0.2 R/W 1* M0.1 R/W 1* M0.0 R/W 1*
Table 17. Register 13 - Interrupt mask port 1 register (address 0Dh) bit descriptionLegend: * default value. M1.7 R/W 1* enable or disable interrupts
0 = enable interrupt
1 = disable interrupt (default value) M1.6 R/W 1* M1.5 R/W 1* M1.4 R/W 1* M1.3 R/W 1* M1.2 R/W 1* M1.1 R/W 1* M1.0 R/W 1*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.6.15 Register 14 - Interrupt status port 0 registerThis register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register will return all zeros.
7.6.16 Register 15 - Interrupt status port 1 registerThis register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register will return all zeros.
7.7 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9575 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9575 registers and state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supplyis above VPOR. However, whenitis requiredto reset the partby lowering the power
supply, it is necessary to lower it below 0.2V.
7.8 RESET input reset canbe accomplishedby holding the RESET pin LOWfora minimumof tw(rst). The
PCA9575 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
Table 18. Register 14 - Interrupt status port 0 register (address 0Eh) bit descriptionLegend: * default value. S0.7 read only 0* identifies source of interrupt S0.6 read only 0* S0.5 read only 0* S0.4 read only 0* S0.3 read only 0* S0.2 read only 0* S0.1 read only 0* S0.0 read only 0*
Table 19. Register 15 - Interrupt status port 1 register (address 0Fh) bit descriptionLegend: * default value. S1.7 read only 0* identifies source of interrupt S1.6 read only 0* S1.5 read only 0* S1.4 read only 0* S1.3 read only 0* S1.2 read only 0* S1.1 read only 0* S1.0 read only 0*
NXP Semiconductors PCA9575
16-bit I2 C-bus and SMBus, level translating, low voltage GPIO
7.9 Software resetThe Software Reset Call allows all the devices in the I2 C-bus to be reset to the power-up
state value through a specific formatted I2 C-bus command. To be performed correctly, it
implies that the I2 C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following: A START command is sent by the I2 C-bus master. The reserved General CallI2 C-bus address ‘0000 000’ with the R/Wbit setto0 (write)
is sent by the I2 C-bus master. The PCA9575 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is
returned to the I2 C-bus master. Once the General Call address has been sent and acknowledged, the master sends byte. The value of the byte must be equal to 06h (1000 0011).The PCA9575
acknowledges this value only. If the byte is not equal to 06h, the PCA9575 does not
acknowledge it. If more than 1 byte of data is sent, the PCA9575 does not
acknowledge anymore. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9575 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed. TheI2 C-bus master must interpreta non-acknowledge from the PCA9575
(at any time) as a ‘Software Reset Abort’. The PCA9575 does not initiate a software
reset.
7.10 Interrupt output (INT)The open-drain active LOW interruptis activated when oneof the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port registeris read.Itis highly recommendedto program the MSK register, and the CFG
registers during the initialization sequence after power-up, since any change to them
during Normal mode operation may cause undesirable interrupt events to happen.
Remark: Changingan I/O froman outputtoan input may causea false interruptto occur the stateof the pin does not match the contentsof the Input Port register. Onlya Readof
the Input Port register that contains the bit(s) image of the input(s) that generated the
interrupt clears the interrupt condition.
7.11 StandbyThe PCA9575 goes into standby when theI2 C-busis idle. Standby supply currentis lower
than 2.0 μA (typical).
