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PCA9574BS
8-bit I虏C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt
1. General descriptionThe PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel
Input/Output (GPIO) expansion in low voltage processor and handheld battery powered
mobile applications and was developed to enhance the NXP family of I2 C-bus I/O
expanders. The improvements include lower supply current, lower operating voltage of
1.1 V to 3.6 V, dual and separate supply rails to allow voltage level translation anywhere
between 1.1 V and 3.6 V, 400 kHz clock frequency, and smaller packaging. Any of the
eight I/O ports can be configured as an input or output independent of each other and
default on start-up to inputs. I/O expanders provide a simple solution when additional I/Os
are needed while keeping interconnections to a minimum; for example in battery powered
mobile applications and clamshell devices for interfacing to sensors, push buttons,
keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of
a processor running at one voltage level to I/O devices operating at a different (usually
higher) voltage level. PCA9574 has built-in level shifting feature that makes these devices
extremely flexible in mixed signal environments where communication between
incompatible I/Os is required. The core of PCA9574 can operate at a voltage as low as
1.1 V while the I/O bank can operate in the range 1.1 V to 3.6 V. Bus-hold with
programmable on-chip pull-up or pull-down feature for I/Os is also provided.
The system master can enable the I/Os as either inputs or outputs by writing to the I/O
configuration register bits. The data for each input or output is kept in the corresponding
Input or Output register. The polarity of the read register can be inverted with the Polarity
inversion register (active HIGH or active LOW operation). Either a bus-hold function or
pull-up/pull-down feature can be selected by programming corresponding registers. The
bus-hold provides a valid logic level when the I/O bus is not actively driven. When
bus-hold feature is not selected, the I/O ports can be configured to have pull-up or
pull-down by programming the pull-up/pull-down configuration register.
An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted
each time a change occurs on an input port unless that port is masked
(default= masked). A ‘GPIO All Call’ command allows programming multiple PCA9574s
at the same time even if they have different individual I2 C-bus addresses. This allows
optimal code programming when more than one device needs to be programmed with the
same instruction or if all outputs need to be turned on or off at the same time. The internal
Power-On Reset (POR) or hardware reset pin (RESET) initializes the eight I/Os as inputs,
sets the registers to their default values and initializes the device state machine. The I/O
bank is held in its default state when the logic supply (VDD) is off.
One address select pin allows up to two PCA9574 devices to be connected with two
different addresses on the same I2 C-bus.
PCA9574
8-bit I2 C-bus and SMBus, level translating, low voltage GPIO
with reset and interrupt
Rev. 4 — 25 April 2012 Product data sheet
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIOThe PCA9574 is available in TSSOP16, HVQFN16 and XQFN16 packages and is
specified over the −40 °C to +85 °C industrial temperature range.
2. Features and benefits 400 kHz I2 C-bus serial interface Compliant with I2 C-bus Standard-mode (100 kHz) Separate supply rails for core logic and I/O bank provides voltage level shifting 1.1 V to 3.6 V operation with level shifting feature Very low standby current: <1 μA 8 configurable I/O pins that default to inputs at power-up Outputs:T otem pole: 1 mA source and 3 mA sink Independently programmable 100 kΩ pull-up or pull-down for each I/O pin Open-drain active LOW interrupt (INT) output pin allows monitoring of logic level
change of pins programmed as inputs Inputs: Programmable bus hold provides valid logic level when inputs are not actively
driven Programmable Interrupt Mask Control for input pins that do not require an interrupt
when their states change or to prevent spurious interrupts default to mask at
power-up Polarity inversion register allows inversion of the polarity of the I/O pins when read Active LOW reset (RESET) input pin resets device to power-up default state GPIO All Call address allows programming of more than one device at the same time
with the same parameters 2 programmable slave addresses using 1 address pin −40 °C to +85 °C operation ESD protection exceeds 7000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: TSSOP16, HVQFN16 and XQFN16
3. Applications Cell phones Media players Multi voltage environments Battery operated mobile gadgets Motherboards Servers RAID systems Industrial control Medical equipment PLCs
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO Gaming machines Instrumentation and test measurement
4. Ordering information
4.1 Ordering options
5. Block diagram
Table 1. Ordering informationPCA9574PW TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9574BS HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body3×3× 0.85 mm
SOT758-1
PCA9574HK XQFN16 plastic, extremely thin quad flat package; no leads; terminals; body 1.80× 2.60× 0.50 mm
SOT1161-1
Table 2. Ordering optionsPCA9574PW PCA9574 Tamb = −40 °C to +85°C
PCA9574BS P74 Tamb = −40 °C to +85°C
PCA9574HK 74 Tamb = −40 °C to +85°C
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
6. Pinning information
6.1 PinningNXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
6.2 Pin description[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
7. Functional description
7.1 Device addressFollowing a START condition the bus master must send the address of the slave it is
accessing and the operation it wants to perform (read or write). The address of the
PCA9574 is shown in Figure 6. Slave address pin A0 chooses 1 of 2 slave addresses:
40h or 42h.
The last bit of the first byte defines the operation to be performed. When set to logic 1 a
read is selected, while logic 0 selects a write operation.
Table 3. Pin descriptionINT 1 15 15 O active LOW interrupt output;
active LOW SMBus alert output 2 16 16 I address input
RESET 311I active LOW reset input 422I/O input/output 0 533I/O input/output 1 644I/O input/output 2 755I/O input/output 3
VSS 86[1] 6 ground supply ground
VDD(IO) 9 7 7 power supply I/O bank supply voltage 10 8 8 I/O input/output 4 11 9 9 I/O input/output 5 12 10 10 I/O input/output 6 13 11 11 I/O input/output 7
SCL 14 12 12 I serial clock line
SDA 15 13 13 I/O serial data line
VDD 16 14 14 power supply supply voltage
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.2 Command registerFollowing the successful acknowledgement of the slave address + R/W bit, the bus
master will send a byte to the PCA9574, which will be stored in the Command register.
The lowest three bits are used as a pointer to determine which register will be accessed.
Only a command register code with the three least significant bits equal to the eight
allowable values as defined in Table 4 “Register summary” will be acknowledged.
Reserved or undefined command codes will not be acknowledged. At power-up, this
register defaults to 00h, with the AI bit set to ‘0’, and the lowest 3 bits set to ‘0’.
If the Auto-Increment flag is set (AI= 1), the three least significant bits of the Command
register are automatically incremented after a read or write. This allows the user to
program and/or read the eight command registers (listed in Table 4) sequentially. It will
then roll over to register 00h after the last register is accessed and the selected registers
will be overwritten or re-read.
If the Auto-Increment flag is cleared (AI= 0), the three least significant bits are not
incremented after data is read or written, only one register will be repeatedly read or
written.
7.3 Register definitions
7.4 Writing to port registersData is transmitted to the PCA9574 by sending the device address and setting the least
significant bit to logic 0 (see Figure 6 for device address). The command byte is sent after
the address and determines which register will receive the data following the command
byte. Each 8-bit register may be updated independently of the other registers.
Table 4. Register summary00h 000IN read only Input port register
01h 001INVRT read/write Polarity inversion register
02h 0 1 0 BKEN read/write Bus-hold enable register
03h 011PUPD read/write Pull-up/pull-down selector register
04h 100CFG read/write Port configuration register
05h 101OUT read/write Output port register
06h 110MSK read/write Interrupt mask register
07h 111INTS read only Interrupt status register
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.5 Reading the port registersIn order to read data from the PCA9574, the bus master must first send the PCA9574
address with the least significant bit set to a logic 0 (see Figure 6 for device address). The
command byte is sent after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the least significant bit is set
to logic 1. Data from the register defined by the command byte will then be sent by the
PCA9574. Data is clocked into the register on the falling edge of the acknowledge clock
pulse. After the first byte is read, additional bytes may be read using the auto-increment
feature.
7.5.1 Register 0 - Input port registerThis register is read-only. It reflects the incoming logic levels of the pins, regardless of
whether the pin is defined as an input or an output by the Configuration register. Writes to
this register will be acknowledged but will have no effect.
The default ‘X’ is determined by the externally applied logic level.
7.5.2 Register 1 - Polarity inversion registerThis register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Register 0 - Input port register (address 00h) bit description I0.7 read only X determined by externally applied logic level I0.6 read only X I0.5 read only X I0.4 read only X I0.3 read only X I0.2 read only X I0.1 read only X I0.0 read only X
Table 6. Register 1 - Polarity inversion register (address 01h) bit descriptionLegend: * default value. N0.7 R/W 0* inverts polarity of Input port register data
0 = Input port register data retained (default value)
1 = Input port register data inverted
6N0.6 R/W 0*
5N0.5 R/W 0*
4N0.4 R/W 0*
3N0.3 R/W 0*
2N0.2 R/W 0*
1N0.1 R/W 0*
0N0.0 R/W 0*
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable registerBit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins.
Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the
pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature.
Bit 1 of this register allows the user to enable/disable pull-up/pull-downs on the I/O pins.
Setting the bit 1 to logic 1 enables selection of pull-up/pull-down using Register 3. Setting
the bit 1 to logic 0 disables pull-up/pull-downs on the I/O pins and contents of Register3
will have no effect on the I/O.
Table 7. Register 2 - Bus-hold/pull-up/pull-down enable register (address 02h) bit
descriptionLegend: * default value. E0.7 R/W X not used
6E0.6 R/W X
5E0.5 R/W X
4E0.4 R/W X
3E0.3 R/W X
2E0.2 R/W X E0.1 R/W 0* allows the user to enable/disable pull-up/pull-downs on the
I/O pins
0 = disables pull-up/pull-downs on the I/O pins and
contents of Register 3 will have no effect on the I/O
(default value)
1 = enables selection of pull-up/pull-down using
Register3 E0.0 R/W 0* allows user to enable/disable the bus-hold feature for the I/O
pins
0 = disables bus-hold feature (default value)
1 = enables bus-hold feature
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.5.4 Register 3 - Pull-up/pull-down selector registerWhen bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port
can be configured to have pull-up or pull-down by programming the pull-up/pull-down
register. Setting a bit to logic 1 will select a 100 kΩ pull-up resistor for that I/O pin. Setting
a bit to logic 0 will select a 100 kΩ pull-down resistor for that I/O pin. If the bus-hold
feature is enabled, writing to this register will have no effect on pull-up/pull-down
selection.
7.5.5 Register 4 - Configuration registerThis register configures the direction of the I/O pins. If a bit in this register is set (written
with logic 1), the corresponding port pin is enabled as an input with high-impedance
output driver. If a bit in this register is cleared (written with logic 0), the corresponding port
pin is enabled as an output. At reset, the device’s ports are inputs.
Table 8. Register 3 - Pull-up/pull-down selector register (address 03h) bit descriptionLegend: * default value. P0.7 R/W 1* configures I/O port pin to have pull-up or pull-down when
bus-hold feature not selected and bit 1 of Register 2 is
logic1
0 = selects a 100 kΩ pull-down resistor for that I/O pin
1 = selects a 100 kΩ pull-up resistor for that I/O pin
(default value)
6P0.6 R/W 1*
5P0.5 R/W 1*
4P0.4 R/W 1*
3P0.3 R/W 1*
2P0.2 R/W 1*
1P0.1 R/W 1*
0P0.0 R/W 1*
Table 9. Register 4 - Configuration register (address 04h) bit descriptionLegend: * default value. C0.7 R/W 1* configures the direction of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value) C0.6 R/W 1* C0.5 R/W 1* C0.4 R/W 1* C0.3 R/W 1* C0.2 R/W 1* C0.1 R/W 1* C0.0 R/W 1*
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.5.6 Register 5 - Output port registerThis register is an output-only port. It reflects the outgoing logic levels of the pins defined
as outputs by Register 4. Bit values in this register have no effect on pins defined as
inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the
output selection, not the actual pin value.
7.5.7 Register 6 - Interrupt mask registerAll the bits of Interrupt mask register are set to logic 1 upon power-on or software reset,
thus disabling interrupts. Interrupts may be enabled by setting corresponding mask bits to
logic0.
Table 10. Register 5 - Output port register (address 05h) bit descriptionLegend: * default value. O0.7 R/W 0* reflects outgoing logic levels of pins defined as
outputs by Register 46O0.6 R/W 0*
5O0.5 R/W 0*
4O0.4 R/W 0*
3O0.3 R/W 0*
2O0.2 R/W 0*
1O0.1 R/W 0*
0O0.0 R/W 0*
Table 11. Register 6 - Interrupt mask register (address 06h) bit descriptionLegend: * default value. M0.7 R/W 1* enable or disable interrupts
0 = enable interrupt
1 = disable interrupt (default value)
6M0.6 R/W 1*
5M0.5 R/W 1*
4M0.4 R/W 1*
3M0.3 R/W 1*
2M0.2 R/W 1*
1M0.1 R/W 1*
0M0.0 R/W 1*
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
7.5.8 Register 7 - Interrupt status registerThis register is read-only. It is used to identify the source of interrupt.
Remark: If the interrupts are masked, this register will return all zeros.
7.6 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9574 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9574 registers and state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supply is above VPOR. However, when it is required to reset the part by lowering the power
supply, it is necessary to lower it below 0.2V.
7.7 RESET inputA reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9574 registers and I2 C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
7.8 Software resetThe Software Reset Call allows all the devices in the I2 C-bus to be reset to the power-up
state value through a specific formatted I2 C-bus command. To be performed correctly, it
implies that the I2 C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following: A START command is sent by the I2 C-bus master. The reserved General Call I2 C-bus address ‘0000 000’ with the R/W bit set to 0 (write)
is sent by the I2 C-bus master. The PCA9574 device(s) acknowledge(s) after seeing the General Call address
‘0000 0000’ (00h) only. If the R/W bit is set to logic 1 (read), no acknowledge is
returned to the I2 C-bus master. Once the General Call address has been sent and acknowledged, the master sends byte. The value of the byte must be equal to 06h.The PCA9574 acknowledges this
value only. If the byte is not equal to 06h, the PCA9574 does not acknowledge it. If
more than 1 byte of data is sent, the PCA9574 does not acknowledge anymore.
Table 12. Register 7 - Interrupt status register (address 07h) bit descriptionLegend: * default value. S0.7 read only 0* identifies source of interrupt S0.6 read only 0* S0.5 read only 0* S0.4 read only 0* S0.3 read only 0* S0.2 read only 0* S0.1 read only 0* S0.0 read only 0*
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the PCA9574 then resets to
the default value (power-up value) and is ready to be addressed again within the
specified bus free time. If the master sends a Repeated START instead, no reset is
performed. The I2 C-bus master must interpret a non-acknowledge from the PCA9574
(at any time) as a ‘Software Reset Abort’. The PCA9574 does not initiate a software
reset.
7.9 Interrupt output (INT)The open-drain active LOW interrupt is activated when one of the port pins changes state
and the port pin is configured as an input and the interrupt on it is not masked. The
interrupt is deactivated when the port pin input returns to its previous state or the Input
Port register is read. It is highly recommended to program the MSK register, and the CFG
registers during the initialization sequence after power-up, since any change to them
during Normal mode operation may cause undesirable interrupt events to happen.
Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input port register. Only a read of
the Input port register that contains the bit(s) image of the input(s) that generated the
interrupt clears the interrupt condition.
7.10 StandbyThe PCA9574 goes into standby when the I2 C-bus is idle. Standby supply current is lower
than 1.0 μA (typical).
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure9).
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
9. Bus transactionsData is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see Figure 12
and Figure 13).
Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure 14 and
Figure 15).
NXP Semiconductors PCA9574
8-bit I2 C-bus and SMBus, level translating, low volage GPIO
