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PCA9564D-PCA9564PW
Parallel bus to I2C-bus controller
Product data sheet
Supersedes data of 2004 Jun 25
2006 Sep 01
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
FEATURES• Parallel-bus to I2C-bus protocol converter and interface Both master and slave functions Multi-master capability Internal oscillator reduces external components Operating supply voltage 2.3 V to 3.6 V 5 V tolerant I/Os Standard and fast mode I2C capable and compatible with SMBus ESD protection exceeds 2000 V HEM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which
exceed 100 mA. Packages offered: DIP20, SO20, TSSOP20, HVQFN20
APPLICATIONS• Add I2 C-bus port to controllers/processors that do not have one Add additional I2 C-bus ports to controllers/processors that need
multiple I2C-bus ports Higher frequency, lower voltage migration path for the PCF8584 Converts 8 bits of parallel data to serial data stream to prevent
having to run a large number of traces across the entire PC board
DESCRIPTIONThe PCA9564 is an integrated circuit designed in CMOS technology
that serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I2 C-bus and allows
the parallel bus system to communicate bi-directionally with the
I2C-bus. The PCA9564 can operate as a master or a slave and can
be a transmitter or receiver. Communication with the I2C-bus is
carried out on a byte-wise basis using interrupt or polled handshake.
The PCA9564 controls all the I2C-bus specific sequences, protocol,
arbitration and timing with no external timing element required.
The PCA9564 is similar to the PCF8584 but operates at lower
voltages and higher I�C frequencies. Other enhancements
requested by design engineers have also been incorporated.
While the PCF8584 supported most parallel-bus microcontrollers/
microprocessors including the Intel 8049/8051, Motorola
6800/68000 and the Zilog Z80, the PCA9564 has been designed to
be very similar to the Philips standard 80C51 microcontroller I2C
hardware so the devices are not code compatible. Additionally, the
PCA9564 does not support the bus monitor “Snoop” mode nor the
long distance mode and is not footprint compatible with the
PCF8584.
ORDERING INFORMATIONStandard packing quantities and other packaging data are available at www.standardics.philips.com/packaging.
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
PIN CONFIGURATION — DIP , SO, TSSOP
PIN CONFIGURATION — HVQFN
PIN DESCRIPTION
NOTES: HVQFN package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for
proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board
using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in
the PCB in the thermal pad region.
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Figure 1. Block diagram
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
FUNCTIONAL DESCRIPTION
GeneralThe PCA9564 acts as an interface device between standard
high-speed parallel buses and the serial I2 C-bus. On the I2 C-bus, it
can act either as master or slave. Bidirectional data transfer between
the I2C-bus and the parallel-bus microcontroller is carried out on a
byte-wise basis, using either an interrupt or polled handshake.
Internal OscillatorThe PCA9564 contains an internal 9 MHz oscillator which is used
for all I2C timing. The oscillator requires up to 500 μs to start-up
after ENSIO bit is set to “1”.
RegistersThe PCA9564 contains four registers which are used to configure
the operation of the device as well as to send and receive serial data.
The registers are selected by setting pins A0 and A1 to the
appropriate logic levels before a read or write operation is executed.
CAUTION: Do not write to I2C registers while the I2C-bus is busy
and the SIO is in master or addressed slave mode.
The Time-out Register, I2CTO: The time-out register is used todetermine the maximum time that SCL is allowed to be LOW before
the I2C state machine is reset.
When the I2 C interface is operating, I2CTO is loaded in the time-out
counter at every SCL transition.
I2CTO 5 4 3 2 1 0
The most significant bit of I2CTO (TE) is used as a time-out
enable/disable. A “1” will enable the time-out function. The time-out
period = (I2CTO[6:0] + 1) × 113.7 μs. The time-out value may vary
some and is an approximate value.
The time-out register can be used in the following cases: When the SIO, in the master mode, wants to send a START
condition and the SCL line is held LOW by some other device.
The SIO waits a time period equivalent to the time-out value for
the SCL to be released. In case it is not released, the SIO
concludes that there is a bus error, loads 90H in the I2CSTA
register, generates an interrupt signal and releases the SCL and
SDA lines. After the microcontroller reads the status register, it
needs to send an external reset in order to reset the SIO. In the master mode, the time-out feature starts every time the SCL
goes LOW. If SCL stays LOW for a time period equal to or greater
than the time-out value, the SIO concludes there is a bus error
and behaves in the manner described above.
The Address Register, I2CADR: I2CADR is not affected by theSIO hardware. The contents of this register are irrelevant when SIO
is in a master mode. In the slave modes, the seven most significant
bits must be loaded with the microcontroller’s own slave address.
I2CADR 65 4 3 2 1 0
The most significant bit corresponds to the first bit received from the
I2C-bus after a start condition. A logic 1 in I2CADR corresponds to a
HIGH level on the I2C-bus, and a logic 0 corresponds to a LOW
level on the bus. The least significant bit is not used but should be
programmed with a ‘0’.
The Data Register, I2CDAT: I2CDAT contains a byte of serial datato be transmitted or a byte which has just been received. In master
mode, this includes the slave address that the master wants to send
out on the I2C-bus, with the most significant bit of the slave address
in the SD7 bit position and the Read/Write bit in the SD0 bit position.
The CPU can read from and write to this 8-bit register while it is not
in the process of shifting a byte. This occurs when SIO is in a
defined state and the serial interrupt flag is set. Data in I2CDAT
remains stable as long as SI is set. Whenever the SIO generates an
interrupt, the I2CDAT registers contain the data byte that was just
transferred on the I2C-bus.
NOTE: The I2CDAT register will capture the serial address as datawhen addressed via the serial bus. Also, the data register will
continue to capture data from the serial bus during 38H so the
I2CDAT register will need to be reloaded when the bus becomes
free.
I2CDAT 65 4 3 2 1 0 SD7 - SD0:
Eight bits to be transmitted or just received. A logic 1 in I2CDAT
corresponds to a HIGH level on the I2C-bus, and a logic 0
corresponds to a LOW level on the bus.
The Control Register, I2CCON: The microcontroller can read fromand write to this 8-bit register. Two bits are affected by the SIO
hardware: the SI bit is set when a serial interrupt is requested, and
the STO bit is cleared when a STOP condition is present on the2 C-bus. A write to the I2CCON register clears the SI bit and causes
the Serial Interrupt line to be de–asserted and the next clock pulse
on the SCL line to be generated. Since none of the registers should
be written to via the parallel interface once the Serial Interrupt line
has been de-asserted, all the other registers that need to be
modified should be written to before the content of the I2CCON
register is modified.
I2CCON 65 4 3 2 1 0 ENSIO, THE SIO ENABLE BIT
ENSIO = “0”: When ENSIO is “0”, the SDA and SCL outputs are in a
high impedance state. SDA and SCL input signals are ignored, SIO
is in the “not addressed” slave state.
ENSIO = “1”: When ENSIO is “1”, SIO is enabled.
After the ENSIO bit is set, it takes 500 μs for the internal oscillator to
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
release the PCA9564 from the I2 C-bus since, when ENSIO is reset,
the I2 C-bus status is lost. The AA flag should be used instead (see
description of the AA flag in the following text).
In the following text, it is assumed that ENSIO = “1”. STA, THE START FLAG
STA = “1”: When the STA bit is set to enter a master mode, the SIO
hardware checks the status of the I2C-bus and generates a START
condition if the bus is free. If the bus is not free, then SIO waits for a
STOP condition (which will free the bus) and generates a START
condition after the minimum buffer time (tBUF) has elapsed.
If STA is set while SIO is already in a master mode and one or more
bytes are transmitted or received, SIO transmits a repeated START
condition. STA may be set at any time. STA may also be set when
SIO is an addressed slave.
STA = “0”: When the STA bit is reset, no START condition or
repeated START condition will be generated. STO, THE STOP FLAG
STO = “1”: When the STO bit is set while SIO is in a master mode, a
STOP condition is transmitted to the I2C-bus. When the STOP
condition is detected on the bus, the SIO hardware clears the STO
flag.
If the STA and STO bits are both set, then a STOP condition is
transmitted to the I2 C-bus if SIO is in a master mode. SIO then
transmits a START condition.
STO = “0”: When the STO bit is reset, no STOP condition will be
generated. SI, THE SERIAL INTERRUPT FLAG
SI = “1”: When the SI flag is set, then, if the ENSIO bit is also set, a
serial interrupt is requested. SI is set by hardware when one of 24 of
the 25 possible SIO states is entered. The only state that does not
cause SI to be set is state F8H, which indicates that no relevant
state information is available.
While SI is set, the LOW period of the serial clock on the SCL line is
stretched, and the serial transfer is suspended. A HIGH level on the
SCL line is unaffected by the serial interrupt flag. SI must be reset
by writing “0” to the SI bit. The SI bit cannot be set by the user.
SI = “0”: When the SI flag is reset, no serial interrupt is requested,
and there is no stretching of the serial clock on the SCL line. AA, THE ASSERT ACKNOWLEDGE FLAG
AA = “1”: If the AA flag is set, an acknowledge (LOW level to SDA)
will be returned during the acknowledge clock pulse on the SCL line
when: The “own slave address” has been received A data byte has been received while SIO is in the master receiver
mode A data byte has been received while SIO is in the addressed
slave receiver mode
AA = “0”: if the AA flag is reset, a not acknowledge (HIGH level to
SDA) will be returned during the acknowledge clock pulse on SCL
when: A data byte has been received while SIO is in the master receiver
mode A data byte has been received while SIO is in the addressed
slave receiver mode “Own slave address” has been received
When SIO is in the addressed slave transmitter mode, state C8H
will be entered after the last serial is transmitted (see Figure 5).
When SI is cleared, enters the not addressed slave receiver mode,
and the SDA line remains at a HIGH level. In state C8H, the AA flag
can be set again for future address recognition.
When SIO is in the not addressed slave mode, its own slave
address is ignored. Consequently, no acknowledge is returned, and
a serial interrupt is not requested. Thus, SIO can be temporarily
released from the I2C-bus while the bus status is monitored. While
SIO is released from the bus, START and STOP conditions are
detected, and serial data is shifted in. Address recognition can be
resumed at any time by setting the AA flag. THE CLOCK RATE BITS, CR2, CR1, AND CR0
Three bits determine the serial clock frequency when SIO is in
master mode. The various serial rates are shown in Table 1.
The clock frequencies only take the HIGH and LOW times into
consideration. The rise and fall time will cause the actual measured
frequency to be lower than expected.
The frequencies shown in Table 1 are unimportant when SIO is in a
slave mode. In the slave modes, SIO will automatically synchronize
with any clock frequency up to 400 kHz.
Table 1. Serial Clock Rates
NOTE: The clock frequency values are approximate and may vary
with temperature, supply voltage, process, and SCL output
loading. If normal mode I2 C parameters must be strictly followed
(SCL < 100kHz), it is recommended not to use
CR[2:0] = 100 (SCL = 88kHz) since the clock frequency might be
slightly higher than 100 kHz under certain temperature, voltage,
and process conditions and use CR[2:0] = 101 (SCL = 59 kHz)
instead.
The Status Register, I2CSTA: I2CSTA is an 8-bit read-only register.The three least significant bits are always zero. The five most
significant bits contain the status code. There are 25 possible status
codes. When I2CSTA contains F8H, no relevant state information is
available and no serial interrupt is requested. All other I2CSTA
values correspond to defined SIO states. When each of these states
is entered, a serial interrupt is requested (SI = “1”).
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
More Information on SIO Operating ModesThe four operating modes are: Master Transmitter Master Receiver Slave Receiver Slave Transmitter
Data transfers in each mode of operation are shown in Figures 2–5.
These figures contain the following abbreviations:
Abbreviation Explanation Start condition
SLA 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) Acknowledge bit (LOW level at SDA) Not acknowledge bit (HIGH level at SDA)
Data 8-bit data byte Stop condition
In Figures 2-5, circles are used to indicate when the serial interrupt
flag is set. A serial interrupt is not generated when I2CSTA = F8H.
This happens on a stop condition. The numbers in the circles show
the status code held in the I2CSTA register. At these points, a service
routine must be executed to continue or complete the serial transfer.
These service routines are not critical since the serial transfer is
suspended until the serial interrupt flag is cleared by software.
When a serial interrupt routine is entered, the status code in I2CSTA
is used to branch to the appropriate service routine. For each status
code, the required software action and details of the following serial
transfer are given in Tables 2-6.
Master Transmitter Mode: In the master transmitter mode, anumber of data bytes are transmitted to a slave receiver (see
Figure 2). Before the master transmitter mode can be entered,
I2CCON must be initialized as follows:
I2CCON 65 4 3 2 1 0
ENSIO must be set to logic 1 to enable SIO. If the AA bit is reset,
SIO will not acknowledge its own slave address in the event of
another device becoming master of the bus. In other words, if AA is
reset, SIO cannot enter a slave mode. STA, STO, and SI must be
reset.
The master transmitter mode may now be entered by setting the
STA bit. The SIO logic will now test the I2 C-bus and generate a start
condition as soon as the bus becomes free. When a START
condition is transmitted, the serial interrupt flag (SI) is set, and the
status code in the status register (I2CSTA) will be 08H. This status
code must be used to vector to an interrupt service routine that
loads I2CDAT with the slave address and the data direction bit
(SLA+W). The SI bit in I2CCON must then be reset before the serial
transfer can continue.
When the slave address and the direction bit have been transmitted
and an acknowledgment bit has been received, the serial interrupt
flag (SI) is set again, and a number of status codes in I2CSTA are
possible. There are 18H, 20H, or 38H for the master mode and also
68H, or B0H if the slave mode was enabled (AA = logic 1). The
appropriate action to be taken for each of these status codes is
detailed in Table 2. After a repeated start condition (state 10H). SIO
Master Receiver Mode: In the master receiver mode, a number ofdata bytes are received from a slave transmitter (see Figure 3). The
transfer is initialized as in the master transmitter mode. When the
start condition has been transmitted, the interrupt service routine
must load I2CDAT with the 7-bit slave address and the data
direction bit (SLA+R). The SI bit in I2CCON must then be cleared
before the serial transfer can continue.
When the slave address and the data direction bit have been
transmitted and an acknowledgment bit has been received, the
serial interrupt flag (SI) is set again, and a number of status codes in
I2CSTA are possible. These are 40H, 48H, or 38H for the master
mode and also 68H, or B0H if the slave mode was enabled (AA =
logic 1). The appropriate action to be taken for each of these status
codes is detailed in Table 3. ENSIO is not affected by the serial
transfer and are not referred to in Table 3. After a repeated start
condition (state 10H), SIO may switch to the master transmitter
mode by loading I2CDAT with SLA+W.
Note that a master should not transmit its own slave address.
Slave Receiver Mode: In the slave receiver mode, a number ofdata bytes are received from a master transmitter (see Figure 4). To
initiate the slave receiver mode, I2CADR and I2CCON must be
loaded as follows:
I2CADR 65 43 2 1 0
The upper 7 bits are the address to which SIO will respond when
addressed by a master.
I2CCON 65 4 3 2 1 0 0 0 0 X X X
ENSIO must be set to logic 1 to enable SIO. The AA bit must be set
to enable SIO to acknowledge its own slave address, STA, STO,
and SI must be reset.
When I2CADR and I2CCON have been initialized, SIO waits until it
is addressed by its own slave address followed by the data direction
bit which must be “0” (W) for SIO to operate in the slave receiver
mode. After its own slave address and the W bit have been
received, the serial interrupt flag (I) is set and a valid status code
can be read from I2CSTA. This status code is used to vector to an
interrupt service routine, and the appropriate action to be taken for
each of these status codes is detailed in Table 4. The slave receiver
mode may also be entered if arbitration is lost while SIO is in the
master mode (see status 68H).
If the AA bit is reset during a transfer, SIO will return a not
acknowledge (logic 1) to SDA after the next received data byte.
While AA is reset, SIO does not respond to its own slave address.
However, the I2C-bus is still monitored and address recognition may
be resumed at any time by setting AA. This means that the AA bit
may be used to temporarily isolate SIO from the I2C-bus.
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Figure 2. Format and states in the master transmitter mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
ÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
Figure 3. Format and states in the master receiver mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
ÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇÇÇÇ
ÇÇÇ
Figure 4. Format and states in the slave receiver mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Table 2. Master Transmitter Mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Table 3. Master Receiver Mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Table 4. Slave Receiver Mode
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Table 5. Slave Transmitter Mode
Table 6. Miscellaneous States
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Slave Transmitter Mode: In the slave transmitter mode, a numberof data bytes are transmitted to a master receiver (see Figure 5).
Data transfer is initialized as in the slave receiver mode. When
I2CADR and I2CCON have been initialized, SIO waits until it is
addressed by its own slave address followed by the data direction
bit which must be “1” (R) for SIO to operate in the slave transmitter
mode. After its own slave address and the R bit have been received,
the serial interrupt flag (SI) is set and a valid status code can be
read from I2CSTA. This status code is used to vector to an interrupt
service routine, and the appropriate action to be taken for each of
these status codes is detailed in Table 5. The slave transmitter mode
may also be entered if arbitration is lost while SIO is in the master
mode (see state B0H).
If the AA bit is reset during a transfer, SIO will transmit the last byte
of the transfer and enter state C8H. SIO is switched to the not
addressed slave mode and will ignore the master receiver if it
continues the transfer. Thus the master receiver receives all 1s as
serial data. While AA is reset, SIO does not respond to its own slave
address. However, the I2C-bus is still monitored, and address
recognition may be resumed at any time by setting AA. This means
that the AA bit may be used to temporarily isolate SIO from the2 C-bus.
Miscellaneous States: There are four I2CSTA codes that do notcorrespond to a defined SIO hardware state (see Table 6). These
are discussed below.
I2CSTA = F8H:This status code indicates that no relevant information is available
because the serial interrupt flag, SI, is not yet set. This occurs on a
STOP condition and when SIO is not involved in a serial transfer.
I2CSTA = 00H:This status code indicates that a bus error has occurred during an
SIO serial transfer. A bus error is caused when a START or STOP
condition occurs at an illegal position in the format frame. Examples
of such illegal positions are during the serial transfer of an address
byte, a data byte, or an acknowledge bit. A bus error may also be
caused when external interference disturbs the internal SIO signals.
When a bus error occurs, SI is set. To recover from a bus error, the
microcontroller must send an external reset signal to reset the SIO.
I2CSTA = 70H:This status code indicates that the SDA line is stuck LOW when the
SIO, in master mode, is trying to send a START condition.
I2CSTA = 90H:This status code indicates that the SCL line is stuck LOW.
Some Special Cases: The SIO hardware has facilities to handle thefollowing special cases that may occur during a serial transfer: SIMULTANEOUS REPEATED START CONDITIONS FROM TWO MASTERS
A repeated START condition may be generated in the master
transmitter or master receiver modes. A special case occurs if
another master simultaneously generates a repeated START
condition (see Figure 6). Until this occurs, arbitration is not lost by
either master since they were both transmitting the same data.
If the SIO hardware detects a repeated START condition on the2 C-bus before generating a repeated START condition itself, it will
use the repeated START as its own and continue with the sending of
the slave address. DATA TRANSFER AFTER LOSS OF ARBITRATION
Arbitration may be lost in the master transmitter and master receiver
modes. Loss of arbitration is indicated by the following states in
I2CSTA; 38H, 68H, and B0H (see Figures 2 and 3).
NOTE: In order to exit state 38H, a Timeout, Reset, or externalStop are required.
If the STA flag in I2CCON is set by the routines which service these
states, then, if the bus is free again, a START condition (state 08H)
is transmitted without intervention by the CPU, and a retry of the
total serial transfer can commence. FORCED ACCESS TO THE I2 C BUS
In some applications, it may be possible for an uncontrolled source
to cause a bus hang-up. In such situations, the problem may be
caused by interference, temporary interruption of the bus or a
temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks
a STOP condition, then the I2 C-bus stays busy indefinitely. If the
STA flag is set and bus access is not obtained within a reasonable
amount of time, then a forced access to the I2 C-bus is possible. If
the I2 C-bus stays idle for a time period equal to the time out period,
then the ’64 concludes that no other master is using the bus and
sends a START condition.
Figure 6. Simultaneous repeated START conditions from 2 masters
Philips Semiconductors Product data sheet
PCA9564Parallel bus to I2 C-bus controller
Figure 7. Forced access to a busy I2 C-busI2 C BUS OBSTRUCTED BY A LOW LEVEL ON SCL OR SDA
An I2 C-bus hang-up occurs if SDA or SCL is pulled LOW by an
uncontrolled source. If the SCL line is obstructed (pulled LOW) by a
device on the bus, no further serial transfer is possible, and the SIO
hardware cannot resolve this type of problem. When this occurs, the
problem must be resolved by the device that is pulling the SCL bus
line LOW.
When the SCL line stays LOW for a period equal to the time-out
value, the ’64 concludes that this is a bus error and behaves in a
manner described on page 5 under “Time-out Register”.
If the SDA line is obstructed by another device on the bus (e.g., a
slave device out of bit synchronization), the problem can be solved
by transmitting additional clock pulses on the SCL line (see
Figure 8). The SIO hardware sends out nine clock pulses followed
by the STOP condition. If the SDA line is released by the slave
pulling it LOW, a normal START condition is transmitted by the SIO,
state 08H is entered and the serial transfer continues. If the SDA
line is not released by the slave pulling it LOW, then the SIO
concludes that there is a bus error, loads 70H in I2CSTA, generates
an interrupt signal, and releases the SCL and SDA lines. After the
microcontroller reads the status register, it needs to send an
external reset signal in order to reset the SIO.
If a forced bus access occurs or a repeated START condition is
transmitted while SDA is obstructed (pulled LOW), the SIO
hardware performs the same action as described above. In each
case, state 08H is entered after a successful START condition is
transmitted and normal serial transfer continues. Note that the CPU
is not involved in solving these bus hang-up problems. BUS ERROR
A bus error occurs when a START or STOP condition is present at
an illegal position in the format frame. Examples of illegal positions
are during the serial transfer of an address byte, a data or an
acknowledge bit.
The SIO hardware only reacts to a bus error when it is involved in a
serial transfer either as a master or an addressed slave. When a
bus error is detected, SIO releases the SDA and SCL lines, sets the
interrupt flag, and loads the status register with 00H. This status
code may be used to vector to a service routine which either
attempts the aborted serial transfer again or simply recovers from
the error condition as shown in Table 6. The microcontroller must
send an external reset signal to reset the SIO.
Figure 8. Recovering from a bus obstruction caused by a LOW level on SDA
