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PCA9559PW
PCA9559; 5-bit multiplexed/1-bit latched 6-bit I²C EEPROM DIP switch
Product data
Supersedes data of 2002 May 24
2003 Jun 27
Philips Semiconductors Product data
PCA95595-bit multiplexed/1-bit latched 6-bit 2 C EEPROM DIP switch
FEATURES 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch 6-bit internal non-volatile register Internal non-volatile register programmable and readable via2 C-bus Override input forces all outputs to logic 0 5 open drain multiplexed outputs 1 open drain non-multiplexed (latched) output 5 V and 2.5 V tolerant inputs Useful for ‘jumperless’ configuration of PC motherboards 2 address pins, allowing up to 4 devices on the I2 C-bus ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
DESCRIPTIONThe PCA9559 is a 20-pin CMOS device consisting of one 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 2 preset values (1 set of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance or deep
sleep modes. The PCA9559 is also useful in server and
telecom/networking applications when used to replace DIP switches
or jumpers, since the settings can be easily changed via I2C/SMBus
without having to power down the equipment to open the cabinet.
The non-volatile memory retains the most current setting selected
before the power is turned off.
The PCA9559 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption.
The PCA9559 has 2 address pins allowing up to 4 devices to be
placed on the same I2C-bus or SMBus.
PIN CONFIGURATION
Figure 1. Pin configuration
PIN DESCRIPTION
ORDERING INFORMATION
Philips Semiconductors Product data
PCA95595-bit multiplexed/1-bit latched 6-bit 2 C EEPROM DIP switch
FUNCTIONAL DESCRIPTIONWhen the MUX_SELECT signal is logic 0, the multiplexer will select
the data from the non-volatile register to drive on the MUX_OUT
pins. When the MUX_SELECT signal is logic 1, the multiplexer will
select the MUX_IN lines to drive on the MUX_OUT pins. The
MUX_SELECT signal is also used to latch the NON_MUXED_OUT
signal which outputs data from the non-volatile register. The
NON_MUXED_OUT signal latch is transparent when MUX_SELECT
is in a logic 0 state, and will latch data when MUX_SELECT is in a
logic 1 state. When the active-LOW OVERRIDE_N signal is set to
logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will
be driven to logic 0. This information is summarized in Table 1.
The Write Protect (WP) input is used to control the ability to write the
contents of the 6-bit non-volatile register. If the WP signal is logic 0,
the I2C-bus will be able to write the contents of the non-volatile
register. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile register.
The factory default for the contents of the non-volatile register are all
logic 0. These stored values can be read or written using the
I2C-bus (described in the next section).
The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have
internal pull-up resistors. See the DC and AC Characteristics for
hysteresis and signal spike suppression figures.
FUNCTION TABLE
NOTE: NON_MUXED_OUT state will be the value present on the output
at the time of the MUX_SELECT input transitioned from a logic 0
to a logic 1 state.
2 C INTERFACECommunicating with this device is initiated by sending a valid
address on the I2 C-bus. The address format (see FIgure 1) has 5
fixed bits and two user-programmable bits followed by a 1-bit
read/write value which determines the direction of the data transfer.
Figure 2. I2C Address ByteFollowing the address and acknowledge bit are 8 data bits which,
depending on the read/write bit in the address, will read data from or
write data to the non-volatile register. Data will be written to the
register if the read/write bit is logic 0 and the WP input is logic 0.
Data will be read from the register if the bit is logic 1. The four
high-order bits are latched outputs, while the four low order bits are
multiplexed outputs (Figure 3).
NOTE: To ensure data integrity, the non-volatile register must be
internally write protected when VCC to the I2 C-bus is powered
down or VCC to the component is dropped below normal
operating levels.
Figure 3. I2 C Data Byte
POWER-ON RESET (POR)When power is applied to VCC, an internal power-on reset holds the
PCA9559 in a reset state until VCC has reached VPOR. At that point,
the reset condition is released and the PCA9559 volatile registers
and I2 C/SMBus state machine will initialize to their default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
the OVERRIDE # and MUX_SELECT logic levels
the previously stored values in the EEPROM register/current
MUX_IN pin values as shown in the Function Table.
Philips Semiconductors Product data
PCA95595-bit multiplexed/1-bit latched 6-bit 2 C EEPROM DIP switch
BLOCK DIAGRAM
Figure 4. Block diagram
Philips Semiconductors Product data
PCA95595-bit multiplexed/1-bit latched 6-bit 2 C EEPROM DIP switch
ABSOLUTE MAXIMUM RATINGS1, 2In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0 V)
NOTES: Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Philips Semiconductors Product data
PCA95595-bit multiplexed/1-bit latched 6-bit 2 C EEPROM DIP switch
DC CHARACTERISTICS
NOTES: VHYS is the hysteresis of Schmitt-Trigger inputs
NON-VOLATILE STORAGE SPECIFICATIONS
