PCA9557D ,8-bit I2C-bus and SMBus I/O port with resetBlock diagram PCA9557A0IO0A1IO1A28-bit IO2SCLINPUTIO3INPUT/2I C-BUS/SMBusFILTERSDAOUTPUT IO4CONTROL ..
PCA9557DB ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander with Reset and Configuration Registers 16-SSOP -40 to 856 Specifications(1)6.1 Absolute
PCA9557DBR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander with Reset and Configuration Registers 16-SSOP -40 to 85Features 2 DescriptionThis 8-bit I/O expander for the two-line bidirectional1• Low Standby Current ..
PCA9557DGVR ,Remote 8-Bit I2C and SMBus Low-Power I/O Expander with Reset and Configuration Registers 16-TVSOP -40 to 85Features 2 DescriptionThis 8-bit I/O expander for the two-line bidirectional1• Low Standby Current ..
PCA9557DGVRG4G4 , REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS
PCA9557DGVRG4G4 , REMOTE 8-BIT I2C AND SMBus LOW-POWER I/O EXPANDER WITH RESET AND CONFIGURATION REGISTERS
PEX8619-BA50BCG , Flexible & Versatile 16-lane 16-port PCI Express Switch
PEX8649-AA50BCF , PCI Express Gen 2 Switch, 48 Lanes, 12 Ports
PF0140 , MOSFET POWER AMPLIFIER MODULE FOR GSM HANDY PHONE
PF0560.104NLT , SMT POWER INDUCTORS
PF0560.152NL , SMT POWER INDUCTORS Shielded Drum Core - PF0560NL Series
PF0560.382NL , SMT POWER INDUCTORS Shielded Drum Core - PF0560NL Series
PCA9557D
8-bit I2C-bus and SMBus I/O port with reset
1. General descriptionThe PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2 C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2 C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the 2 C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
2. Features and benefits Lower voltage, higher performance migration path for the PCA9556 8 general purpose input/output expander/collector Input/output configuration register Active HIGH polarity inversion registerI2 C-bus and SMBus interface logic Internal power-on reset Noise filter on SCL/SDA inputs Active LOW reset input 3 address pins allowing up to 8 devices on the I2 C-bus/SMBus High-impedance open-drain on IO0 No glitch on power-up Power-up with all channels configured as inputs Low standby current Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant inputs/outputs0 kHz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Three packages offered: SO16, TSSOP16, HVQFN16
PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
Rev. 7 — 10 December 2013 Product data sheet
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
3. Ordering information
3.1 Ordering options
4. Block diagram
Table 1. Ordering informationPCA9557BS 9557 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; terminals; body44 0.85 mm
SOT629-1
PCA9557D PCA9557D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
PCA9557PW PCA9557 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Table 2. Ordering optionsPCA9557BS PCA9557BS,118 HVQFN16 Reel 13” Q1/T1
*Standard mark SMD
6000 Tamb= 40 C to +85C
PCA9557D PCA9557D,112 SO16 Standard marking
* IC’s tube - DSC bulk pack
1000 Tamb= 40 C to +85C
PCA9557D,118 SO16 Reel 13” Q1/T1
*Standard mark SMD
2500 Tamb= 40 C to +85C
PCA9557PW PCA9557PW,112 TSSOP16 Standard marking
* IC’s tube - DSC bulk pack
2400 Tamb= 40 C to +85C
PCA9557PW,118 TSSOP16 Reel 13” Q1/T1
*Standard mark SMD
2500 Tamb= 40 C to +85C
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with resetNXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with resetNXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
5. Pinning information
5.1 Pinning
5.2 Pin description
Table 3. Pin descriptionSCL 1 15 serial clock line
SDA 2 16 serial data line 3 1 address input 0 4 2 address input 1 5 3 address input 2 6 4 input/output 0 (open-drain)
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. System diagramVSS 86[1] supply ground
IO2 9 7 input/output 2
IO3 10 8 input/output 3
IO4 11 9 input/output 4
IO5 12 10 input/output 5
IO6 13 11 input/output 6
IO7 14 12 input/output 7
RESET 15 13 active LOW reset input
VDD 16 14 supply voltage
Table 3. Pin description …continued
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
7. Functional descriptionRefer to Figure 1 “Block diagram of PCA9557”.
7.1 Device addressFollowing a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
7.2 Control registerFollowing the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9557, which will be stored in the control register. This register can be
written and read via the I2 C-bus.
Table 4. Register definition 0 Register0 read-only Input port register 1 Register1 read/write Output port register 0 Register2 read/write Polarity inversion register 1 Register3 read/write Configuration register
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
7.3 Register descriptions
7.3.1 Register 0 - Input port registerThis register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. Writes
to this register have no effect.
7.3.2 Register 1 - Output port registerThis register reflects the outgoing logic levels of the pins defined as outputs by the
Configuration register. Bit values in this register have no effect on pins defined as inputs.
In turn, reads from this register reflect the value that is in the flip-flop controlling the output
selection, not the actual pin value.
7.3.3 Register 2 - Polarity inversion registerThis register enables polarity inversion of pins defined as inputs by the Configuration
register. If a bit in this register is set (written with logic 1), the corresponding port pin’s
polarity is inverted. If a bit in this register is cleared (written with logic 0), the
corresponding port pin’s original polarity is retained.
7.3.4 Register 3 - Configuration registerThis register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output.
Table 5. Register 0 - Input port register bit allocation
Table 6. Register 1 - Output port register bit allocation
Table 7. Register 2 - Polarity inversion register bit allocation
Table 8. Register 3 - Configuration register bit allocation
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
7.4 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in
a reset condition until VDD has reached VPOR. At that point, the reset condition is released
and the PCA9557 registers and I2 C-bus/SMBus state machine will initialize to their default
states. Thereafter, VDD must be lowered below 0.2 V to reset the device.
7.5 RESET inputA reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The
PCA9557 registers and SMBus/I2 C-bus state machine will be held in their default state
until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if
no active connection is used.
8. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 10).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 11).
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12).
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
8.4 Bus transactionsData is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14
and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte
transfers (see Figure 16 and Figure 17).
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with resetNXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
9. Application design-in information
9.1 Minimizing IDD when the I/Os are used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the
I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes
lower than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/OVI
at or above VDD and prevents additional supply current consumption when the LED is off.
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
10. Limiting values
Table 9. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +6 V input voltage VSS 0.5 5.5 V input current - 20 mA
IIHL(max) maximum allowed input current
through protection diode (IO1to IO7) VDD or VI VSS - 400 A
VI/O voltage on an input/output pin I/O as an input, except IO0 VSS 0.5 5.5 V
IO0 as an input VSS 0.5 5.5 V
II/O input/output current IO0 as an input - +400 A 20 mA
IO(IOn) output current on pin IOn - 50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 C
Tamb ambient temperature operating 40 +85 C
NXP Semiconductors PCA9557
8-bit I2 C-bus and SMBus I/O port with reset
11. Static characteristics[1] VDD must be lowered to 0.2 V in order to reset part.
[2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit.
[3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit.
Table 10. Static characteristicsVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.
SuppliesVDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD =5.5V; load; fSCL= 100 kHz
-19 25 A
IstbL LOW-level standby current standby mode; VDD =5.5V; load; VI =VSS; fSCL=0 kHz;
I/O= inputs
-0.25 1 A
IstbH HIGH-level standby current standby mode; VDD =5.5V; load; VI =VDD; fSCL=0 kHz;
I/O= inputs
-0.25 1 A
Istb additional standby current standby mode; VDD =5.5V;
every LED I/O at VI =4.3V;
fSCL=0 kHz
-0.8 1 mA
VPOR power-on reset voltage no load; VI =VDD or VSS [1] -1.65 2.1 V
Input SCL; input/output SDAVIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5 V
IOL LOW-level output current VOL =0.4 V; VDD= 2.3V 3 --mA leakage current VI =VDD or VSS 1- +1 A input capacitance VI =VSS -6 10 pF
I/OsVIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL =5.5 V; VDD =2.3V [2] 810 - mA
IOH HIGH-level output current except pin IO0; VOH =2.4V [3]4 --mA
pin IO0; VOH= 4.6V --1 A
pin IO0; VOH= 3.3V --1 A
ILI input leakage current VDD =5.5 V; VI =VSS -- 100 A input capacitance - 3.7 5 pF output capacitance - 3.7 5 pF
Select inputs A0, A1, A2 and RESETVIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- +1 A
