PCA9555D-PCA9555PW- Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9555D ,16-bit I2C and SMBus I/O port with interruptFEATURESActive-LOW operation) registers. The system master can enable theI/Os as either inputs or o ..
PCA9555D ,16-bit I2C and SMBus I/O port with interruptPIN CONFIGURATION — HVQFN1 24 VINT DD2 23A1 SDAI/O0.0 18 A013 22A2 SCLI/O1.7I/O0.1 2 174 21I/O0.0 A ..
PCA9555D ,16-bit I2C and SMBus I/O port with interruptBlock diagramPCA9555IO1_0IO1_18-bitIO1_2A0INPUT/IO1_3A1OUTPUTIO1_4A2PORTSwrite pulseIO1_5IO1_6read ..
PCA9555DB ,16-bit I2C-bus and SMBus I/O port with interruptPIN CONFIGURATION — DIP, SO, SSOP, TSSOP
PCA9555DBR ,Remote 16-Bit I2C And SMBus I/O Expander With Interrupt Output And Configuration Registers 24-SSOP -40 to 85Maximum Ratings. 4• Changed the Handling Ratings table to the ESD Ratings table... 4• Added the The ..
PCA9555DWRG4 ,Remote 16-Bit I2C And SMBus I/O Expander With Interrupt Output And Configuration Registers 24-SOIC -40 to 85Maximum Ratings . 410.1 Power-On Reset Errata..... 246.2 ESD Ratings........ 411 Layout.... 256.3 R ..
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PCA9555D-PCA9555PW-
16-bit I2C-bus and SMBus I/O port with interrupt
General descriptionThe PCA9555isa 24-pin CMOS device that provides16 bitsof General Purpose parallel
Input/Output (GPIO) expansion for I2 C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2 C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
conﬁguration, and smaller packaging. I/O expanders provide a simple solution when
additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
The PCA9555 consistsof two 8-bit Conﬁguration (Inputor Output selection); Input, Output
and Polarity Inversion (active HIGH or active LOW operation) registers. The system
master can enable the I/Os as either inputs or outputs by writing to the I/O conﬁguration
bits. The data for each Input or Output is kept in the corresponding Input or Output
register. The polarity of the read register can be inverted with the Polarity Inversion
register. All registers can be read by the system master. Although pin-to-pin and I2 C-bus
address compatible with the PCF8575, software changes are required due to the
enhancements, and are discussed in Application Note AN469.
The PCA9555 open-drain interrupt outputis activated when any input state differs fromits
corresponding input port register state and is used to indicate to the system master that
an input state has changed. The power-on reset sets the registers to their default values
and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the ﬁxed I2 C-bus address and allow up to eight
devices to share the same I2 C-bus/SMBus. The ﬁxed I2 C-bus address of the PCA9555 is
the same as the PCA9554, allowing up to eight of these devices in any combination to
share the same I2 C-bus/SMBus. Features Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise ﬁlter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
Rev. 08 — 22 October 2009 Product data sheet
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24 Ordering information
3.1 Ordering options
Table 1. Ordering information
PCA9555N DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1
PCA9555D SO24 plastic small outline package; 24 leads;
body width 7.5 mm
SOT137-1
PCA9555DB SSOP24 plastic shrink small outline package; 24 leads;
body width 5.3 mm
SOT340-1
PCA9555PW TSSOP24 plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9555BS HVQFN24 plastic thermal enhanced very thin quad ﬂat package; leads; 24 terminals; body4×4× 0.85 mm
SOT616-1
PCA9555HF HWQFN24 plastic thermal enhanced very very thin quad ﬂat
package; no leads; 24 terminals; body4×4× 0.75 mm
SOT994-1
Table 2. Ordering options
PCA9555N PCA9555 −40 °C to +85°C
PCA9555D PCA9555D −40 °C to +85°C
PCA9555DB PCA9555 −40 °C to +85°C
PCA9555PW PCA9555 −40 °C to +85°C
PCA9555BS 9555 −40 °C to +85°C
PCA9555HF P55H −40 °C to +85°C
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt Block diagram Pinning information
5.1 Pinning
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
5.2 Pin description
[1] HVQFN and HWQFN packagedie supply groundis connectedto boththe VSSpin andthe exposed center
pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 3. Pin description
INT 1 22 interrupt output (open-drain) 2 23 address input 1 3 24 address input 2
IO0_0 4 1 port 0 input/output
IO0_1 5 2
IO0_2 6 3
IO0_3 7 4
IO0_4 8 5
IO0_5 9 6
IO0_6 10 7
IO0_7 11 8
VSS 12 9[1] supply ground
IO1_0 13 10 port 1 input/output
IO1_1 14 11
IO1_2 15 12
IO1_3 16 13
IO1_4 17 14
IO1_5 18 15
IO1_6 19 16
IO1_7 20 17 21 18 address input 0
SCL 22 19 serial clock line
SDA 23 20 serial data line
VDD 24 21 supply voltage
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt Functional description
Refer to Figure 1 “Block diagram of PCA9555”.
6.1 Device address
6.2 Registers
6.2.1 Command byte
The command byteis the ﬁrst byteto follow the address byte duringa write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command byte Input port0 Input port1 Output port0 Output port1 Polarity Inversion port0 Polarity Inversion port1 Conﬁguration port0 Conﬁguration port1
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reﬂects the incoming logic levels of the pins,
regardless of whether the pin is deﬁned as an input or an output by Register 3. Writes to
this register have no effect.
The default value ‘X’ is determined by the externally applied logic level.
6.2.3 Registers 2 and 3: Output port registers
This register is an output-only port. It reﬂects the outgoing logic levels of the pins deﬁned
as outputs by Registers 6 and 7. Bit values in this register have no effect on pins deﬁned inputs.In turn, reads from this register reﬂect the value thatisin the ﬂip-ﬂop controlling
the output selection, not the actual pin value.
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in
this register is set (written with ‘1’), the Input port data polarity is inverted. If a bit in this
register is cleared (written with a ‘0’), the Input port data polarity is retained.
Table 5. Input port 0 Register
Table 6. Input port 1 register
Table 7. Output port 0 register
Table 8. Output port 1 register
Table 9. Polarity Inversion port 0 register
Table 10. Polarity Inversion port 1 register
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
6.2.5 Registers 6 and 7: Conﬁguration registers
This register conﬁgures the directions of the I/O pins. If a bit in this register is set (written
with ‘1’), the corresponding port pin is enabled as an input with high-impedance output
driver. If a bit in this register is cleared (written with ‘0’), the corresponding port pin is
enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At
reset, the device's ports are inputs with a pull-up to VDD.
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset
condition until VDD has reached VPOR.At that point, the reset conditionis released and the
PCA9555 registers and SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by the time the power
supplyis above VPOR. However, whenitis requiredto reset the partby lowering the power
supply, it is necessary to lower it below 0.2V.
6.4 I/O port
When an I/O is conﬁgured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up to VDD. The input voltage may be raised above
VDD to a maximum of 5.5V. the I/Ois conﬁguredasan output, then either Q1or Q2is on, dependingon the stateof
the Output Port register. Care should be exercised if an external voltage is applied to an
I/O conﬁgured as an output because of the low-impedance path that exists between the
pin and either VDD or VSS.
Table 11. Conﬁguration port 0 register
Table 12. Conﬁguration port 1 register
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least
signiﬁcantbittoa logic0 (see Figure8 “PCA9555 device address”). The command byteis
sent after the address and determines which register will receive the data following the
command byte.
The eight registers within the PCA9555 are conﬁgured to operate as four register pairs.
The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Conﬁguration
Ports. After sending data to one register, the next data byte will be sent to the other
register in the pair (see Figure 10 and Figure 11). For example, if the ﬁrst byte is sent to
Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, each 8-bit register may be updated independently of the other registers.
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NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must ﬁrst send the PCA9555
address with the least signiﬁcant bit set to a logic 0 (see Figure 8 “PCA9555 device
address”). The command byteis sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
signiﬁcant bit is set to a logic 1. Data from the register deﬁned by the command byte will
then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked
into the register on the falling edge of the acknowledge clock pulse. After the ﬁrst byte is
read, additional bytes maybe read but the data will now reﬂect the informationin the other
registerin the pair. For example,if you read Input Port1, then the next byte read wouldbe
Input Port 0. There is no limitation on the number of data bytes received in one read
transmission but the ﬁnal byte received, the bus master must not acknowledge the data.
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NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
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NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
6.5.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and
the pinis conﬁguredasan input. The interruptis deactivated when the input returnstoits
previous state or the Input Port register is read (see Figure 13). A pin conﬁgured as an
output cannot causean interrupt. Since each 8-bit portis read independently, the interrupt
caused by Port 0 will not be cleared by a read of Port 1 or the other way around.
Remark: Changingan I/O froman outputtoan input may causea false interruptto occur
if the state of the pin does not match the contents of the Input Port register. Characteristics of the I2 C-bus
TheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 15).
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis deﬁnedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOP
condition (P) (see Figure 16).
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt
7.2 System conﬁguration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 17).
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH periodof the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt Application design-in information
NXP Semiconductors PCA9555
16-bit I2 C-bus and SMBus I/O port with interrupt Limiting values
Table 13. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V
VI/O voltage on an input/output pin VSS− 0.5 6 V output current on an I/O pin - ±50 mA input current - ±20 mA
IDD supply current - 160 mA
ISS ground supply current - 200 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C

Partno	Mfg	Dc	Qty	Available	Descript
PCA9555D	Pb-free	N/a	1729	avai	16-bit I2C and SMBus I/O port with interrupt
PCA9555D	NXP ?	N/a	1490	avai	16-bit I2C and SMBus I/O port with interrupt
PCA9555PW- \|PCA9555PW	NXP	N/a	1	avai	16-bit I2C-bus and SMBus I/O port with interrupt