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PCA9555BS-PCA9555D-PCA9555DB-PCA9555PW
16-bit I2C and SMBus I/O port with interrupt
Product data sheet
Supersedes data of 2004 Jul 27
2004 Sep 30
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
FEATURES Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity inversion register Active-LOW interrupt output Low stand-by current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs 0 kHz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA Five packages offered: DIP24, SO24, SSOP24, TSSOP24, and
HVQFN24
DESCRIPTIONThe PCA9555 is a 24-pin CMOS device that provide 16 bits of
General Purpose parallel Input/Output (GPIO) expansion for2 C/SMBus applications and was developed to enhance the Philips
family of I�C I/O expanders. The improvements include higher drive
capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power
switches, sensors, pushbuttons, LEDs, fans, etc.
The PCA9555 consist of two 8-bit Configuration (Input or Output
selection); Input, Output and Polarity inversion (Active-HIGH or
Active-LOW operation) registers. The system master can enable the
I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each Input or Output is kept in the corresponding
Input or Output register. The polarity of the read register can be
inverted with the Polarity Inversion Register. All registers can be
read by the system master. Although pin-to-pin and I2C address
compatible with the PCF8575, software changes are required due to
the enhancements and are discussed in Application Note AN469.
The PCA9555 open-drain interrupt output is activated when any
input state differs from its corresponding input port register state and
is used to indicate to the system master that an input state has
changed. The power-on reset sets the registers to their default
values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2 C address and
allow up to eight devices to share the same I2 C/SMBus. The fixed2 C address of the PCA9555 is the same as the PCA9554 allowing
up to eight of these devices in any combination to share the same2 C/SMBus.
ORDERING INFORMATIONStandard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.
I2C is a trademark of Philips Semiconductors Corporation.
SMBus as specified by the Smart Battery System Implementers Forum is a derivative of the Philips I2C patent.
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
PIN CONFIGURATION — DIP , SO, SSOP , TSSOP
Figure 1. Pin configuration — DIP, SO, SSOP, TSSOP
PIN CONFIGURATION — HVQFN
Figure 2. Pin configuration — HVQFN
PIN DESCRIPTION
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
BLOCK DIAGRAM
Figure 3. Block diagram
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
SIMPLIFIED SCHEMATIC OF I/Os
NOTE: At Power-on Reset, all registers return to default values.
Figure 4. Simplified schematic of I/Os
I/O portWhen an I/O is configured as an input, FETs Q1 and Q2 are off,
creating a high impedance input with a weak pull-up to VDD. The
input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, then either Q1 or Q2 is on,
depending on the state of the Output Port register. Care should be
exercised if an external voltage is applied to an I/O configured as an
output because of the low impedance path that exists between the
pin and either VDD or VSS.
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
REGISTERS
Command ByteThe command byte is the first byte to follow the address byte during
a write transmission. It is used as a pointer to determine which of the
following registers will be written or read.
Registers 0 and 1 — Input Port RegistersThis register is an input-only port. It reflects the incoming logic levels
of the pins, regardless of whether the pin is defined as an input or an
output by Register 3. Writes to this register have no effect.
The default value ‘X’ is determined by the externally applied logic
level.
Registers 2 and 3 — Output Port RegistersThis register is an output-only port. It reflects the outgoing logic
levels of the pins defined as outputs by Register 6 and 7. Bit values
in this register have no effect on pins defined as inputs. In turn,
reads from this register reflect the value that is in the flip-flop
controlling the output selection, NOT the actual pin value.
Registers 4 and 5 — Polarity Inversion RegistersThis register allows the user to invert the polarity of the Input Port
register data. If a bit in this register is set (written with ‘1’), the Input
Port data polarity is inverted. If a bit in this register is cleared (written
with a ‘0’), the Input Port data polarity is retained.
Registers 6 and 7 — Configuration RegistersThis register configures the directions of the I/O pins. If a bit in this
register is set (written with ‘1’), the corresponding port pin is enabled
as an input with high impedance output driver. If a bit in this register
is cleared (written with ‘0’), the corresponding port pin is enabled as
an output. Note that there is a high value resistor tied to VDD at each
pin. At reset the device’s ports are inputs with a pull-up to VDD.
POWER-ON RESETWhen power is applied to VDD, an internal power-on reset holds the
PCA9555 in a reset condition until VDD has reached VPOR. At that
point, the reset condition is released and the PCA9555 registers and
SMBus state machine will initialize to their default states. The
power-on reset typically completes the reset and enables the part by
the time the power supply is above VPOR. However, when it is
required to reset the part by lowering the power supply, it is
necessary to lower it below 0.2 V.
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
DEVICE ADDRESS
Figure 5. PCA9555 address
BUS TRANSACTIONS
Writing to the port registersData is transmitted to the PCA9555 by sending the device address
and setting the least significant bit to a logic 0 (see Figure 5 for device
address). The command byte is sent after the address and determines
which register will receive the data following the command byte.
The eight registers within the PCA9555 are configured to operate
as four register pairs. The four pairs are Input Ports, Output Ports,
Polarity Inversion Ports, and Configuration Ports. After sending data
to one register, the next data byte will be sent to the other register in
the pair (see Figures and ). For example, if the first byte is sent to
Output Port (register 3), then the next byte will be stored in Output
Port 0 (register 2). There is no limitation on the number of data bytes
sent in one write transmission. In this way, each 8-bit register may
be updated independently of the other registers.
Reading the port registersIn order to read data from the PCA9555, the bus master must first
send the PCA9555 address with the least significant bit set to a
logic 0 (see Figure 5 for device address). The command byte is sent
after the address and determines which register will be accessed.
After a restart, the device address is sent again but this time, the
least significant bit is set to a logic 1. Data from the register defined
by the command byte will then be sent by the PCA9555 (see
Figures 8 and 9). Data is clocked into the register on the falling edge
of the acknowledge clock pulse. After the first byte is read, additional
bytes may be read but the data will now reflect the information in the
other register in the pair. For example, if you read Input Port 1, then
the next byte read would be Input Port 0. There is no limitation on
the number of data bytes received in one read transmission but the
final byte received, the bus master must not acknowledge the data.
Interrupt OutputThe open-drain interrupt output is activated when one of the port
pins change state and the pin is configured as an input. The interrupt
is deactivated when the input returns to its previous state or the
input port register is read (see Figure 9). A pin configured as an
output cannot cause an interrupt. Since each 8-bit port is read
independently, the interrupt caused by Port 0 will not be cleared by a
read of Port 1 or the other way around.
Note that changing an I/O from an output to an input may cause a
false interrupt to occur if the state of the pin does not match the
contents of the Input Port register.
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
Figure
6.
WRITE to output port registers
Figure
WRITE to configuration registers
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
OP
condition.
Figure
READ from registerOP condition. When this occurs, data present at the latest acknowledge pha
se is valid (output mode).
Figure
READ input port register — scenario 1
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
OP condition. When this occurs, data present at the latest acknowledge pha
se is valid (output mode).
Figure
READ input port register — scenario 2
Philips Semiconductors Product data sheet
PCA955516-bit I2 C and SMBus I/O port with interrupt
TYPICAL APPLICATION
Figure 11. Typical application.
