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PCA9555APW
Low-voltage 16-bit I虏C-bus I/O port with interrupt and weak pull-up
1. General descriptionThe PCA9555A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and weak pull-up resistors for I2 C-bus/SMBus applications. NXP I/O
expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum, for example, in ACPI power switches, sensors, push
buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5V
allows the PCA9555A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9555A contains the PCA9555 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers.
The PCA9555A is a pin-to-pin replacement to the PCA9555 and other industry-standard
devices. A more fully featured device, the PCAL9555A, is available with Agile I/O
features. See the respective data sheet for more details.
The PCA9555A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2 C-bus. Thus, the PCA9555A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
All input/output pins have weak pull-up resistors connected to them to eliminate external
components.
Three hardware pins (A0, A1, A2) select the fixed I2 C-bus address and allow up to eight
devices to share the same I2 C-bus/SMBus.
PCA9555A
Low-voltage 16-bit I2 C-bus I/O port with interrupt and
weak pull-up
Rev. 1 — 11 September 2012 Product data sheet
NXP Semiconductors PCA9555A
Low-voltage 16-bit I2 C-bus I/O port with interrupt and weak pull-up
2. Features and benefitsI2 C-bus to parallel port expander Operating power supply voltage range of 1.65 V to 5.5V Low standby current consumption: 1.5 A (typical at 5 V VDD) 1.0 A (typical at 3.3 V VDD) Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs Vhys = 0.10 VDD (typical)5 V tolerant I/Os Open-drain active LOW interrupt output (INT) 400 kHz Fast-mode I2 C-bus Internal power-on reset Power-up with all channels configured as inputs with weak pull-up resistors No glitch on power-up Latched outputs with 25 mA drive maximum capability for directly driving LEDs Latch-up performance exceeds 100 mA per JESD78, ClassII ESD protection exceeds JESD22 2000 V Human Body Model (A114-A) 1000 V Charged-Device Model (C101) Packages offered: TSSOP24, HWQFN24
3. Ordering information
3.1 Ordering options
Table 1. Ordering informationPCA9555APW TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1
PCA9555AHF HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; terminals; body44 0.75 mm
SOT994-1
Table 2. Ordering optionsPCA9555APW PCA9555A 40 C to +85C
PCA9555AHF 555A 40 C to +85C
NXP Semiconductors PCA9555A
Low-voltage 16-bit I2 C-bus I/O port with interrupt and weak pull-up
4. Block diagram
5. Pinning information
5.1 PinningNXP Semiconductors PCA9555A
Low-voltage 16-bit I2 C-bus I/O port with interrupt and weak pull-up
5.2 Pin description[1] HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2] Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3] Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
Table 3. Pin descriptionINT 1 22 O Interrupt output. Connect to VDD through a
pull-up resistor. 2 23 I Address input 1. Connect directly to VDD or VSS. 3 24 I Address input 2. Connect directly to VDD or VSS.
P0_0[2] 4 1 I/O Port 0 input/output 0.
P0_1[2] 5 2 I/O Port 0 input/output 1.
P0_2[2] 6 3 I/O Port 0 input/output 2.
P0_3[2] 7 4 I/O Port 0 input/output 3.
P0_4[2] 8 5 I/O Port 0 input/output 4.
P0_5[2] 9 6 I/O Port 0 input/output 5.
P0_6[2] 10 7 I/O Port 0 input/output 6.
P0_7[2] 11 8 I/O Port 0 input/output 7.
VSS 12 9[1] power Ground.
P1_0[3] 13 10 I/O Port 1 input/output 0.
P1_1[3] 14 11 I/O Port 1 input/output 1.
P1_2[3] 15 12 I/O Port 1 input/output 2.
P1_3[3] 16 13 I/O Port 1 input/output 3.
P1_4[3] 17 14 I/O Port 1 input/output 4.
P1_5[3] 18 15 I/O Port 1 input/output 5.
P1_6[3] 19 16 I/O Port 1 input/output 6.
P1_7[3] 20 17 I/O Port 1 input/output 7. 21 18 I Address input 0. Connect directly to VDD or VSS.
SCL 22 19 I Serial clock bus. Connect to VDD through a
pull-up resistor.
SDA 23 20 I/O Serial data bus. Connect to VDD through a
pull-up resistor.
VDD 24 21 power Supply voltage.
NXP Semiconductors PCA9555A
Low-voltage 16-bit I2 C-bus I/O port with interrupt and weak pull-up
6. Functional descriptionRefer to Figure 1 “Block diagram of PCA9555A”.
6.1 Device addressA2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byteFollowing the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9555A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
[1] Undefined.
Table 4. Command byte 0 0 0 0 0 0 0 00h Input port 0 read byte xxxx xxxx[1] 0 0 0 0 0 0 1 01h Input port 1 read byte xxxx xxxx 0 0 0 0 0 1 0 02h Output port 0 read/write byte 11111111 0 0 0 0 0 1 1 03h Output port 1 read/write byte 11111111 0 0 0 0 1 0 0 04h Polarity Inversion port0 read/write byte 0000 0000 0 0 0 0 1 0 1 05h Polarity Inversion port1 read/write byte 0000 0000 0 0 0 0 1 1 0 06h Configuration port0 read/write byte 11111111 0 0 0 0 1 1 1 07h Configuration port1 read/write byte 11111111
