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PCA9554ABS
8-bit I虏C-bus and SMBus I/O port with interrupt
1. General descriptionThe PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I2 C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I2 C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, and so on.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I2 C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in Application Note AN469.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I2 C-bus address and allow up to eight
devices to share the same I2 C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I2 C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I2 C-bus/SMBus.
2. Features and benefits Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 8 I/O pins which default to 8 inputs0 Hz to 400 kHz clock frequency
PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
Rev. 9 — 19 March 2013 Product data sheet
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA AEC-Q100 compliance available Packages offered: SO16, SSOP16, SSOP20, TSSOP16, HVQFN16(2versions: 4 0.85 mm and 33 0.85 mm), and bare die
3. Ordering information[1] PCA9554PW/Q900 is AEC-Q100 compliant. Contact i2c.support for PPAP.
3.1 Ordering options
Table 1. Ordering informationPCA9554D PCA9554D SO16 plastic small outline package; 16 leads;
body width 7.5 mm
SOT162-1
PCA9554AD PCA9554AD
PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
PCA9554ADB 9554A
PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads;
body width 4.4 mm
SOT266-1
PCA9554ATS PA9554A
PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9554PW/Q900[1] 9554DH
PCA9554APW 9554ADH
PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body44 0.85 mm
SOT629-1
PCA9554ABS 554A
PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad flat package; leads; 16 terminals; body33 0.85 mm
SOT758-1
PCA9554ABS3 54A
PCA9554U - bare die - -
Table 2. Ordering optionsPCA9554D PCA9554D,112 SO16 Standard marking *
IC’s tube - DSC bulk pack
1920 Tamb= 40 Cto+85C
PCA9554D,118 SO16 Reel 13” Q1/T1
*standard mark SMD
1000 Tamb= 40 Cto+85C
PCA9554AD PCA9554AD,112 SO16 Standard marking *
IC’s tube - DSC bulk pack
1920 Tamb= 40 Cto+85C
PCA9554AD,118 SO16 Reel 13” Q1/T1
*standard mark SMD
1000 Tamb= 40 Cto+85C
PCA9554DB PCA9554DB,112 SSOP16 Standard marking *
IC’s tube - DSC bulk pack
1092 Tamb= 40 Cto+85C
PCA9554DB,118 SSOP16 Reel 13” Q1/T1
*standard mark SMD
2000 Tamb= 40 Cto+85C
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interruptPCA9554ADB PCA9554ADB,112 SSOP16 Standard marking *
IC’s tube - DSC bulk pack
1092 Tamb= 40 Cto+85C
PCA9554ADB,118 SSOP16 Reel 13” Q1/T1
*standard mark SMD
2000 Tamb= 40 Cto+85C
PCA9554TS PCA9554TS,112 SSOP20 Standard marking *
IC’s tube - DSC bulk pack
1350 Tamb= 40 Cto+85C
PCA9554TS,118 SSOP20 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9554ATS PCA9554ATS,112 SSOP20 Standard marking *
IC’s tube - DSC bulk pack
1350 Tamb= 40 Cto+85C
PCA9554ATS,118 SSOP20 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9554PW PCA9554PW,112 TSSOP16 Standard marking *
IC’s tube - DSC bulk pack
2400 Tamb= 40 Cto+85C
PCA9554PW,118 TSSOP16 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9554PW/Q900 PCA9554PW/Q900,118 TSSOP16 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9554APW PCA9554APW,112 TSSOP16 Standard marking *
IC’s tube - DSC bulk pack
2400 Tamb= 40 Cto+85C
PCA9554APW,118 TSSOP16 Reel 13” Q1/T1
*standard mark SMD
2500 Tamb= 40 Cto+85C
PCA9554BS PCA9554BS,118 HVQFN16 Reel 13” Q1/T1
*standard mark SMD
6000 Tamb= 40 Cto+85C
PCA9554ABS PCA9554ABS,118 HVQFN16 Reel 13” Q1/T1
*standard mark SMD
6000 Tamb= 40 Cto+85C
PCA9554BS3 PCA9554BS3,118 HVQFN16 Reel 13” Q1/T1
*standard mark SMD
6000 Tamb= 40 Cto+85C
PCA9554ABS3 PCA9554ABS3,118 HVQFN16 Reel 13” Q1/T1
*standard mark SMD
6000 Tamb= 40 Cto+85C
PCA9554U PCA9554U,029 bare die Reel 7” Q1/T1 *no mark
die mounted on punched
tape
7000 Tamb= 40 Cto+85C
Table 2. Ordering options …continued
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
4. Block diagramNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
5. Pinning information
5.1 PinningNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
5.2 Pin description[1] HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
6. Functional descriptionRefer to Figure 1 “Block diagram of PCA9554/PCA9554A”.
6.1 Registers
6.1.1 Command byteThe command byte is the first byte to follow the address byte during a write transmission.
It is used as a pointer to determine which of the following registers will be written or read.
Table 3. Pin description 1 15 6 address input 0 2 16 7 address input 1 3 1 9 address input 2
IO0 4 2 10 input/output 0
IO1 5 3 11 input/output 1
IO2 6 4 12 input/output 2
IO3 7 5 14 input/output 3
VSS 86[1] 15 supply ground
IO4 9 7 16 input/output 4
IO5 10 8 17 input/output 5
IO6 11 9 19 input/output 6
IO7 12 10 20 input/output 7
INT 13 11 1 interrupt output (open-drain)
SCL 14 12 2 serial clock line
SDA 15 13 4 serial data line
VDD 16 14 5 supply voltage
n.c. - - 3, 8, 13, 18 not connected
Table 4. Command byte read byte Input Port register read/write byte Output Port register read/write byte Polarity Inversion register read/write byte Configuration register
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
6.1.2 Register 0 - Input Port registerThis register is a read-only port. It reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by Register 3. Writes to this register
have no effect.
The default ‘X’ is determined by the externally applied logic level, normally ‘1’ when no
external signal externally applied because of the internal pull-up resistors.
6.1.3 Register 1 - Output Port registerThis register reflects the outgoing logic levels of the pins defined as outputs by Register 3.
Bit values in this register have no effect on pins defined as inputs. Reads from this register
return the value that is in the flip-flop controlling the output selection, not the actual pin
value.
Table 5. Register 0 - Input Port register bit description I7 read only X determined by externally applied logic level I6 read only X I5 read only X I4 read only X I3 read only X I2 read only X I1 read only X I0 read only X
Table 6. Register 1 - Output Port register bit descriptionLegend: * default value. O7 R 1* reflects outgoing logic levels of pins defined as outputs by Register 36O6 R 1*
5O5 R 1*
4O4 R 1*
3O3 R 1*
2O2 R 1*
1O1 R 1*
0O0 R 1*
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
6.1.4 Register 2 - Polarity Inversion registerThis register allows the user to invert the polarity of the Input Port register data. If a bit in
this register is set (written with ‘1’), the corresponding Input Port data is inverted. If a bit in
this register is cleared (written with a ‘0’), the Input Port data polarity is retained.
6.1.5 Register 3 - Configuration registerThis register configures the directions of the I/O pins. If a bit in this register is set, the
corresponding port pin is enabled as an input with high-impedance output driver. If a bit in
this register is cleared, the corresponding port pin is enabled as an output. At reset, the
I/Os are configured as inputs with a weak pull-up to VDD.
6.2 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the
PCA9554/PCA9554A in a reset condition until VDD has reached VPOR. At that point, the
reset condition is released and the PCA9554/PCA9554A registers and state machine will
initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the
device.
For a power reset cycle, VDD must be lowered below 0.2 V and then restored to the
operating voltage.
Table 7. Register 2 - Polarity Inversion register bit descriptionLegend: * default value. N7 R/W 0* inverts polarity of Input Port register data
0 = Input Port register data retained (default value)
1 = Input Port register data inverted
6N6 R/W 0*
5N5 R/W 0*
4N4 R/W 0*
3N3 R/W 0*
2N2 R/W 0*
1N1 R/W 0*
0N0 R/W 0*
Table 8. Register 3 - Configuration register bit descriptionLegend: * default value. C7 R/W 1* configures the directions of the I/O pins
0 = corresponding port pin enabled as an output
1 = corresponding port pin configured as input
(default value)
6C6 R/W 1*
5C5 R/W 1*
4C4 R/W 1*
3C3 R/W 1*
2C2 R/W 1*
1C1 R/W 1*
0C0 R/W 1*
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
6.3 Interrupt outputThe open-drain interrupt output is activated when one of the port pins change state and
the pin is configured as an input. The interrupt is deactivated when the input returns to its
previous state or the Input Port register is read.
Note that changing an I/O from and output to an input may cause a false interrupt to occur
if the state of the pin does not match the contents of the Input Port register.
6.4 I/O portWhen an I/O is configured as an input, FETs Q1 and Q2 are off, creating a
high-impedance input with a weak pull-up (100 k typ.) to VDD. The input voltage may be
raised above VDD to a maximum of 5.5V.
If the I/O is configured as an output, then either Q1 or Q2 is enabled, depending on the
state of the Output Port register. Care should be exercised if an external voltage is applied
to an I/O configured as an output because of the low-impedance paths that exist between
the pin and either VDD or VSS.
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
6.5 Device address
6.6 Bus transactionsData is transmitted to the PCA9554/PCA9554A registers using the Write mode as shown
in Figure 11 and Figure 12. Data is read from the PCA9554/PCA9554A registers using the
Read mode as shown in Figure 13 and Figure 14. These devices do not implement an
auto-increment function, so once a command byte has been sent, the register which was
addressed will continue to be accessed by reads until a new command byte has been
sent.
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interruptNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
7. Application design-in information
8. Limiting values
Table 9. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +6.0 V input current - 20 mA
VI/O voltage on an input/output pin VSS 0.5 5.5 V
IO(IOn) output current on pin IOn - 50 mA
IDD supply current - 85 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 200 mW
Tstg storage temperature 65 +150 C ambient temperature operating 40 +85 C
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
9. Static characteristicsTable 10. Static characteristicsVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.
SuppliesVDD supply voltage 2.3 - 5.5 V
IDD supply current operating mode; VDD =5.5V; load; fSCL= 100 kHz 104 175 A
Istb standby current Standby mode; VDD= 5.5 V; no load; =VSS; fSCL=0 kHz; I/O= inputs 550 700 A
Standby mode; VDD= 5.5 V; no load; =VDD; fSCL=0 kHz; I/O= inputs
-0.25 1 A
VPOR power-on reset voltage no load; VI =VDD or VSS [1]- 1.5 1.65 V
Input SCL; input/output SDAVIL LOW-level input voltage 0.5 - +0.3VDD V
VIH HIGH-level input voltage 0.7VDD -5.5 V
IOL LOW-level output current VOL =0.4V 3 6 - mA leakage current VI =VDD =VSS 1- +1 A input capacitance VI =VSS - 6 10 pF
I/OsVIL LOW-level input voltage 0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IOL LOW-level output current VOL =0.5 V; VDD =2.3V [2] 810 - mA
VOL =0.7 V; VDD =2.3V [2] 10 13 - mA
VOL =0.5 V; VDD =3.0V [2] 814 - mA
VOL =0.7 V; VDD =3.0V [2] 10 19 - mA
VOL =0.5 V; VDD =4.5V [2] 817 - mA
VOL =0.7 V; VDD =4.5V [2] 10 24 - mA
VOH HIGH-level output voltage IOH= 8mA; VDD =2.3V [3] 1.8 - - V
IOH= 10 mA; VDD =2.3V [3] 1.7 - - V
IOH= 8mA; VDD =3.0V [3] 2.6 - - V
IOH= 10 mA; VDD =3.0V [3] 2.5 - - V
IOH= 8mA; VDD =4.75V [3] 4.1 - - V
IOH= 10 mA; VDD =4.75V [3] 4.0 - - V
ILI input leakage current VDD =3.6 V; VI =VDD 1- +1 A leakage current VDD =5.5 V; VI =VSS -- 100 A input capacitance - 3.7 5 pF output capacitance - 3.7 5 pF
Interrupt INTIOL LOW-level output current VOL =0.4V 3 - - mA
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt[1] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
[2] Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 100 mA.
[3] The total current sourced by all I/Os must be limited to 85 mA.
10. Dynamic characteristics[1] tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
[2] tVD;DAT = minimum time for SDA data output to be valid following SCL LOW.
[3] Cb= total capacitance of one bus line in pF.
Select inputs A0, A1, A2VIL LOW-level input voltage 0.5 - 0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
ILI input leakage current 1- 1 A
Table 10. Static characteristics …continuedVDD= 2.3 V to 5.5 V; VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified.
Table 11. Dynamic characteristicsfSCL SCL clock frequency 0 100 0 400 kHz
tBUF bus free time between a STOP and
START condition
4.7 - 1.3 - s
tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s
tSU;STA set-up time for a repeated START
condition
4.7 - 0.6 - s
tSU;STO set-up time for STOP condition 4.0 - 0.6 - s
tHD;DAT data hold time 0 - 0 - s
tVD;ACK data valid acknowledge time [1] 0.3 3.45 0.1 0.9 s
tVD;DAT data valid time [2] 300 - 50 - ns
tSU;DAT data set-up time 250 - 100 - ns
tLOW LOW period of the SCL clock 4.7 - 1.3 - s
tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s rise time of both SDA and SCL signals - 1000 20+ 0.1Cb[3] 300 ns fall time of both SDA and SCL signals - 300 20+ 0.1Cb[3] 300 ns
tSP pulse width of spikes that must be
suppressed by the input filter 50 - 50 ns
Port timingtv(Q) data output valid time - 200 - 200 ns
tsu(D) data input set-up time 100 - 100 - ns
th(D) data input hold time 1 - 1 - s
Interrupt timingtv(INT_N) valid time on pin INT -4 - 4 s
trst(INT_N) reset time on pin INT -4 - 4 s
NXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interruptNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
11. Package outlineNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interruptNXP Semiconductors PCA9554; PCA9554A
8-bit I2 C-bus and SMBus I/O port with interrupt
