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PCA9553TK
4-bit I2C-bus LED driver with programmable blink rates
General descriptionThe PCA9553 LED blinker blinks LEDs in I2 C-bus and SMBus applications where it is
necessary to limit bus traffic or free up the I2 C-bus master's (MCU, MPU, DSP , chip set,
etc.) timer. The uniqueness of this device is the internal oscillator with two programmable
blink rates.To blink LEDs using normal I/O expanders like the PCF8574or PCA9554, the
bus master must send repeated commands to turn the LED on and off. This greatly
increases the amountof trafficon theI2 C-bus and usesup oneof the master's timers. The
PCA9553 LED blinker instead requires only the initial set-up command to program
BLINK RATE1 and BLINK RATE2 (i.e., the frequency and duty cycle). From then on, only
one command from the bus master is required to turn each individual open-drain output
ON, OFF,orto cycleat BLINK RATE1or BLINK RATE2. Maximum output sink currentis mA per bit and 100 mA per package.
Any bits not used for controlling the LEDs can be used for General Purpose Parallel
Input/Output (GPIO) expansion.
Power-On Reset (POR) initializes the registers to their default state, all zeroes, causing
the bits to be set HIGH (LED off).
Due to pin limitations, the PCA9553 is not featured with hardware address pins. The
PCA9553/01 and the PCA9553/02 have different fixed I2 C-bus addresses allowing
operation of both on the same bus.
Features 4 LED drivers (on, off, flashing at a programmable rate) 2 selectable, fully programmable blink rates (frequency and duty cycle) between
0.172 Hz and 44 Hz (5.82 seconds and 0.023 seconds) Input/outputs not used as LED drivers can be used as regular GPIOs Internal oscillator requires no external componentsI2 C-bus interface logic compatible with SMBus Internal power-on reset Noise filter on SCL/SDA inputs 4 open-drain outputs directly drive LEDs to 25 mA Controlled edge rates to minimize ground bounce No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V0 Hz to 400 kHz clock frequency
PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
Rev. 06 — 29 December 2008 Product data sheet
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 (MSOP8), HVSON8
Ordering information[1] Also known as MSOP8.
[2] PCA9553TK uses version /01 address.
Marking
Table 1. Ordering informationPCA9553D/01 SO8 plastic small outline package; 8 leads;
body width 3.9 mm
SOT96-1
PCA9553D/02
PCA9553DP/01 TSSOP8[1] plastic thin shrink small outline package; 8 leads;
body width3 mm
SOT505-1
PCA9553DP/02
PCA9553TK[2] HVSON8 plastic thermal enhanced very thin small outline
package;no leads;8 terminals; body3×3× 0.85 mm
SOT908-1
PCA9553TK/02
Table 2. Marking codesPCA9553D/01 9553/1
PCA9553D/02 9553/2
PCA9553DP/01 P53/1
PCA9553DP/02 P53/2
PCA9553TK P53/1
PCA9553TK/02 P53/2
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates Block diagram
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates Pinning information
6.1 Pinning
6.2 Pin description[1] HVSON8 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal padthe board andfor proper heat conduction throughthe board, thermal vias needtobe incorporatedinthe
PCB in the thermal pad region.
Table 3. Pin descriptionLED0 1 LED driver 0
LED1 2 LED driver 1
LED2 3 LED driver 2
VSS 4[1] supply ground
LED3 5 LED driver 3
SCL 6 serial clock line
SDA 7 serial data line
VDD 8 supply voltage
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates Functional descriptionRefer to Figure 1 “Block diagram”.
7.1 Device addressFollowing a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9553/01 is shown in Figure 5 and PCA9553/02 in
Figure6.
PCA9553TK uses the version /01 address.
The lastbitof the address byte defines the operationtobe performed. When setto logic1
a read is selected, while a logic 0 selects a write operation.
7.2 Control registerFollowing the successful acknowledgementof the slave address, the bus master will send
a byte to the PCA9553 which will be stored in the Control register.
The lowest 3 bits are used as a pointer to determine which register will be accessed.
If the Auto-Increment flag is set, the three low order bits of the Control register are
automatically incremented after a read or write. This allows the user to program the
registers sequentially. The contentsof these bits will rolloverto ‘000’ after the last register
is accessed.
When the Auto-Increment flag is set (AI= 1) and a read sequence is initiated, the
sequence must start by reading a register different from ‘0’ (B2 B1 B0≠00 0).
Only the 3 least significant bits are affected by the AI flag.
Unused bits must be programmed with zeroes.
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
7.3 Register descriptions
7.3.1 INPUT - Input registerThe INPUT register reflects the state of the device pins. Writes to this register will be
acknowledged but will have no effect.
Remark: The default value‘X’is determinedby the externally applied logic level (normally
logic 1) when used for directly driving LED with pull-up to VDD.
7.3.2 PSC0 - Frequency Prescaler0PSC0 is used to program the period of the PWM output.
The period of BLINK0= (PSC0+1)/ 44.
7.3.3 PWM0 - Pulse Width Modulation0The PWM0 register determines the duty cycleof BLINK0. The outputs are LOW (LED off)
when the count is less than the value in PWM0 and HIGH when it is greater. If PWM0 is
programmed with 00h, then the PWM0 output is always LOW.
The duty cycle of BLINK0= (256− PWM0)/ 256.
Table 4. Control register definition 0 0 INPUT read input register 0 1 PSC0 read/write frequency prescaler 0 1 0 PWM0 read/write PWM register 0 1 1 PSC1 read/write frequency prescaler 1 0 0 PWM1 read/write PWM register 1 0 1 LS0 read/write LED selector
Table 5. INPUT - Input register description
Table 6. PSC0 - Frequency Prescaler 0 register description
Table 7. PWM0 - Pulse Width Modulation 0 register description
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
7.3.4 PSC1 - Frequency Prescaler1PSC1 is used to program the period of the PWM output.
The period of BLINK1= (PSC1+1)/ 44.
7.3.5 PWM1 - Pulse Width Modulation1The PWM1 register determines the duty cycleof BLINK1. The outputs are LOW (LED off)
when the count is less than the value in PWM1 and HIGH when it is greater. If PWM1 is
programmed with 00h, then the PWM1 output is always LOW.
The duty cycle of BLINK1= (256− PWM1)/ 256.
7.3.6 LS0 - LED selector registerThe LS0 LED select register determines the source of the LED data.= output is set LOW (LED on)= output is set high-impedance (LED off; default)= output blinks at PWM0 rate= output blinks at PWM1 rate
Table 8. PSC1 - Frequency Prescaler 1 register description
Table 9. PWM1 - Pulse Width Modulation 1 register description
Table 10. LS0 - LED selector register bit descriptionLegend: * default value.
LS0 - LED0 to LED3 selectorLS0 7:6 01* LED3 selected
5:4 01* LED2 selected
3:2 01* LED1 selected
1:0 01* LED0 selected
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
7.4 Pins used as general purpose I/OsLED pins not used to control LEDs can be used as general purpose I/Os.
For use as input: Set LEDn to high-impedance (01) and then read the pin state via the
Input register.
For useas output: Connect external pull-up resistorto the pin and sizeit accordingto the
DC recommended operating characteristics. LED output pin is HIGH when the output is
programmedas high-impedance, and LOW when the outputis programmed LOW through
the ‘LED selector’ register. The output can be pulse-width controlled when PWM0 or
PWM1 are used.
7.5 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9553 in reset condition until VDD has reached VPOR.At that point, the reset conditionis released
and the PCA9553 registers are initializedto their default states, withall outputsin the OFF
state. Thereafter, VDD must be lowered below 0.2 V to reset the device.
Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure8).
8.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transitionof the data line while the clockis HIGHis definedas the START condition (S).A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure 9).
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
8.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
8.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH periodof the acknowledge related clock pulse; set-up time and hold
time must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
8.4 Bus transactions
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates Application design-in information
9.1 Minimizing IDD when the I/Os are used to control LEDsWhen the I/Os are used to control LEDs, they are normally connected to VDD through a
resistoras shownin Figure 15. Since the LED actsasa diode, when the LEDisoff the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD and is specified as ΔIDD in Table 13 “Static characteristics”.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater thanor equalto VDD when the LEDis off.
Figure 16 shows a high value resistor in parallel with the LED. Figure 17 shows VDD less
than the LED supply voltagebyat least 1.2V. Bothof these methods maintain the I/OVIat
or above VDD and prevents additional supply current consumption when the LED is off.
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
9.2 Programming exampleThe following example shows howto set LED0 and LED1 off.It will then set LED2to blink
at 1 Hz, 50 % duty cycle. LED3 will be set to blink at 4 Hz, 25 % duty cycle. PCA9553/01
is used in this example.
Table 11. Programming PCA9553START S
PCA9553 address C4h
PSC0 subaddress + Auto-Increment 11h
Set prescaler PSC0 to achieve a period of 1 second:
PSC0=43
2Bh
Set PWM0 duty cycle to 50%:
PWM0= 128
80h
Set prescaler PSC1 to achieve a period of 0.25 seconds:
PSC1=10
0Ah
Set PWM1 output duty cycle to 25%:
PWM1= 192
C0h
Set LED0 on, LED1 off, LED2 set to blink at PSC0, PWM0, LED3 set to blink at
PSC1, PWM1
E4h
STOP P
Blink period 1 PSC0 1+------------------------==
256 PWM0–
256 -------------------------------- 0.5=
Blink period 0.25 PSC11+------------------------==
256 PWM1–
256 -------------------------------- 0.25=
NXP Semiconductors PCA9553
4-bit I2 C-bus LED driver with programmable blink rates
10. Limiting values
Table 12. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage −0.5 +6.0 V
VI/O voltage on an input/output pin VSS− 0.5 5.5 V
IO(LEDn) output current on pin LEDn - ±25 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature −65 +150 °C
Tamb ambient temperature operating −40 +85 °C
