PCA9547PW ,8-channel I2C-bus multiplexer with resetGeneral description2The PCA9547 is an octal bidirectional translating multiplexer controlled by the ..
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PCA9547PW
8-channel I2C-bus multiplexer with reset
1. General descriptionThe PCA9547 is an octal bidirectional translating multiplexer controlled by the I2 C-bus.
The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one
SCx/SDx channel can be selected at a time, determined by the contents of the
programmable control register. The device powers up with Channel 0 connected, allowing
immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of
the downstream I2 C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2 C-bus state machine causing all the channels to be deselected, except Channel 0 so
that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the VDD pin can be used to
limit the maximum high voltage which will be passed by the PCA9547. This allows the use
of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits 1-of-8 bidirectional translating multiplexerI2 C-bus interface logic; compatible with SMBus standards Active LOW RESET input 3 address pins allowing up to 8 devices on the I2 C-bus Channel selection via I2 C-bus, one channel at a time Power-up with all channels deselected except Channel 0 which is connected Low Ron multiplexers Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO24, TSSOP24, HVQFN24
PCA9547
8-channel I2 C-bus multiplexer with reset
Rev. 4 — 1 April 2014 Product data sheet
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Table 2. Ordering options
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
4. Block diagramNXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
5. Pinning information
5.1 PinningNXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
5.2 Pin description[1] HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Table 3. Pin description
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
6. Functional description
6.1 Device addressingFollowing a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9547 is shown in Figure 5. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control registerFollowing the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9547, which will be stored in the Control register. If multiple bytes are
received by the PCA9547, it will save the last byte received. This register can be written
and read via the I2 C-bus.
6.2.1 Control register definitionA SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9547 has been addressed. The 4 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, the channel will become active after a STOP condition has been placed on the 2 C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is
made active, so that no false conditions are generated at the time of connection.
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
6.3 RESET inputThe RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9547 will reset its
register and I2 C-bus state machine and will deselect all channels except channel 0. The
RESET input must be connected to VDD through a pull-up resistor.
6.4 Power-on resetWhen power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9547 in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9547 register and I2 C-bus state machine are initialized to their default states,
causing all the channels to be deselected except channel 0. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
Table 4. Control registerWrite = channel selection; Read = channel status
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
6.5 Voltage translationThe pass gate transistors of the PCA9547 are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2 C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the
PCA9547 is only tested at the points specified in Section 11 “Static characteristics” of this
data sheet). In order for the PCA9547 to act as a voltage translator, the Vo(mux) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(mux) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(mux)(max) will be at 2.7 V when the PCA9547 supply voltage is
3.5 V or lower so the PCA9547 supply voltage could be set to 3.3 V. Pull-up resistors can
then be used to bring the bus voltages to their appropriate levels (see Figure 14).
More information can be found in Application Note AN262, PCA954X family of I2 C/SMBus
multiplexers and switches.
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
7. Characteristics of the I2 C-busThe I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transferOne data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
7.1.1 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (seeFigure 9.)
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
7.2 System configurationA device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
7.3 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
7.4 Bus transactionsData is transmitted to the PCA9547 control register using the Write mode as shown in
Figure 12.
Data is read from PCA9547 using the Read mode as shown in Figure 13.
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
8. Application design-in informationNXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
9. Limiting values[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125C.
10. Thermal characteristics
Table 5. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Table 6. Thermal characteristics
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset
11. Static characteristics[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 7. Static characteristics at VDD =2.3 V to 3.6VVSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 4.5 V to 5.5V.[1]
NXP Semiconductors PCA9547
8-channel I2 C-bus multiplexer with reset[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
Table 8. Static characteristics at VDD =4.5 V to 5.5VVSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 7 on page 14 for VDD = 2.3 V to 3.6V.[1]
