PCA9546ABS-PCA9546AD Fast Delivery |IC PHOENIX CO.,LIMITED

PCA9546ABS ,4-channel I2C-bus switch with resetGeneral description2The PCA9546A is a quad bidirectional translating switch controlled via the I C- ..
PCA9546AD ,4-channel I2C-bus switch with reset
PCA9546AD ,4-channel I2C-bus switch with resetFeatures and benefits 1-of-4 bidirectional translating switches2 I C-bus interface logic; compati ..
PCA9546AD ,4-channel I2C-bus switch with resetBlock diagram PCA9546ASC0SC1SC2SC3SD0SD1SD2SD3V SWITCH CONTROL LOGICSSVDDPOWER-ONRESETRESETSCL A0IN ..
PCA9546ADG4 ,4-Channel I2C And SMBus Switch With Reset Functions 16-SOIC -40 to 85Electrical Characteristics....... 52 11.1 Layout Guidelines.... 196.5 I C Interface Timing Requirem ..
PCA9546ADGVR ,4-Channel I2C And SMBus Switch With Reset Functions 16-TVSOP -40 to 85Features... 18.4 Device Functional Modes.... 112 Applications..... 18.5 Programming..... 113 Descri ..
PESD3V3L1BA ,PESDxL1BA series; Low capacitance bidirectional ESD protection diodes in SOD323Applicationsn Computers and peripherals n Data linesn Communication systems n CAN bus protectionn A ..
PESD3V3L1BA ,PESDxL1BA series; Low capacitance bidirectional ESD protection diodes in SOD323PESDxL1BA seriesLow capacitance bidirectional ESD protection diodes inSOD323Rev. 02 — 20 August 200 ..
PESD3V3L1UA ,Low capacitance unidirectional ESD protection diodesApplicationsn Computers and peripherals n Subscriber Identity Module (SIM) cardprotectionn Audio an ..
PESD3V3L1UB ,Low capacitance unidirectional ESD protection diodesLimiting valuesTable 6.
PESD3V3L1UL ,Low capacitance unidirectional ESD protection diodesPESD3V3L1UA; PESD3V3L1UB;PESD3V3L1ULLow capacitance unidirectional ESD protection diodesRev. 01 — 1 ..
PESD3V3L2BT ,Low capacitance double bidirectional ESD protection diodes in SOT23Limiting valuesTable 5.

PCA9546ABS-PCA9546AD
4-channel I2C-bus switch with reset
1. General description
The PCA9546A is a quad bidirectional translating switch controlled via the I2 C-bus. The
SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contents of the programmable control register.
An active LOW reset input allows the PCA9546A to recover from a situation where one of
the downstream I2 C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2 C-bus state machine and causes all the channels to be deselected as does the
internal Power-On Reset (POR) function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit
the maximum high voltage which is passed by the PCA9546A. This allows the use of
different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits 1-of-4 bidirectional translating switchesI2 C-bus interface logic; compatible with SMBus standards Active LOW reset input 3 address pins allowing up to 8 devices on the I2 C-bus Channel selection via I2 C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant Inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Three packages offered: SO16, TSSOP16, and HVQFN16
PCA9546A
4-channel I2 C-bus switch with reset
Rev. 6 — 30 April 2014 Product data sheet
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Table 2. Ordering options
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
4. Block diagram
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
5. Pinning information
5.1 Pinning
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
5.2 Pin description
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad must be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias must be
incorporated in the PCB in the thermal pad region.
6. Functional description
Refer to Figure 1 “Block diagram of PCA9546A”.
6.1 Device address
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9546A is shown in Figure 5. T o conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Table 3. Pin description
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9546A, which is stored in the control register. If the PCA9546A receives
multiple bytes, it saves the last byte received. This register can be written and read via the 2 C-bus.
6.2.1 Control register definition
One or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9546A has been addressed. The LSBs of the control byte are used to determine which channel is to be selected. When a
channel is selected, the channel will become active after a STOP condition has been
placed on the I2 C-bus. This ensures that all SCx/SDx lines are in a HIGH state when the
channel is made active, so that no false conditions are generated at the time of
connection.
Remark: Several channels can be enabled at the same time. Example: B3= 0, B2=1, = 1, B0= 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus
capacitance.
Table 4. Control register: Write—channel selection; Read—channel status
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
6.3 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9546A resets its
registers and I2 C-bus state machine and deselects all channels. The RESET input must
be connected to VDD through a pull-up resistor.
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9546A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9546A registers and I2 C-bus state machine are initialized to their default
states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9546A are constructed such that the VDD voltage can
be used to limit the maximum voltage that is passed from one I2 C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be V to effectively clamp the downstream bus voltages. Looking at 7, we see that Vo(sw)(max) is at 2.7 V when the PCA9546A supply voltage is 3.5 V or V. Pull-up resistors can then 14).
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
More Information can be found in Application Note AN262: PCA954X family of I2 C/SMBus
multiplexers and switches.
7. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as control signals (see Figure8).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure9).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
7.5 Bus transactions
Data is transmitted to the PCA9546A control register using the Write mode as shown in
Figure 12.
Data is read from PCA9546A using the Read mode as shown in Figure 13.
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
8. Application design-in information
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
9. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125C.
10. Thermal characteristics
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VSS (ground=0V)[1]
Table 6. Thermal characteristics
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
11. Static characteristics
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] In order to reset part, VDD must be lowered to 0.2 V for at least 5s.
Table 7. Static characteristics at VDD =2.3 V to 3.6V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 8 on page 14 for VDD = 4.5 V to 5.5V.[1]
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] In order to reset part, VDD must be lowered to 0.2 V for at least 5s.
Table 8. Static characteristics at VDD =4.5 V to 5.5V
VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 7 on page 13 for VDD = 2.3 V to 3.6V.[1]
NXP Semiconductors PCA9546A
4-channel I2 C-bus switch with reset
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb= total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 9. Dynamic characteristics

Partno	Mfg	Dc	Qty	Available	Descript
PCA9546ABS	NXP	N/a	11930	avai	4-channel I2C-bus switch with reset
PCA9546AD	NXP ?	N/a	1465	avai	4-channel I2C-bus switch with reset
PCA9546AD	NXP	N/a	1640	avai	4-channel I2C-bus switch with reset