PCA9545APW ,4-channel I虏C-bus switch with interrupt logic and resetPCA9545A24-channel I C switch with interrupt logic and resetRev. 03 — 3 March 2005 Product data she ..
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PCA9545APW
PCA9545A; 4-channel I²C switch with interrupt logic and reset
General descriptionThe PCA9545A is a quad bi-directional translating switch controlled via the I2 C-bus. The
SCL/SDA upstream pair fans out to four downstream pairs, or channels. Any individual
SCx/SDx channel or combination of channels can be selected, determined by the
contentsof the programmable control register. Four interrupt inputs, INT0to INT3, onefor
eachof the downstream pairs, are provided. One interrupt output, INT, actsasan ANDof
the four interrupt inputs. active LOW reset input allows the PCA9545Ato recover froma situation where oneof
the downstreamI2 C-busesis stuckina LOW state. Pulling the RESET pin LOW resets the2 C-bus state machine and causes all the channels to be deselected as does the internal
Power-on reset function.
The pass gatesof the switches are constructed such that the VDD pin canbe usedto limit
the maximum high voltage which willbe passedby the PCA9545A. This allows the useof
different bus voltageson each pair,so that 1.8Vor 2.5Vor 3.3V parts can communicate
with 5 V parts without any additional protection. External pull-up resistors pull the bus up
to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
Features 1-of-4 bi-directional translating switchesI2 C-bus interface logic; compatible with SMBus standards 4 active LOW interrupt inputs Active LOW interrupt output Active LOW reset input 2 address pins allowing up to 4 devices on the I2 C-bus Channel selection via I2 C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low stand-by current Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant Inputs0 kHz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up protection exceeds 100 mA per JESD78
PCA9545A
4-channel I2 C switch with interrupt logic and reset
Philips Semiconductors PCA9545A Three packages offered: SO20, TSSOP20, and HVQFN20
Ordering informationStandard packing quantities and other packaging data are available at
www.standardproducts.philips.com/packaging.
Marking
Table 1: Ordering informationTamb= –40 °Cto+85°C
PCA9545ABS HVQFN20 plastic thermal enhanced very thin quad flat package;
no leads; 20 terminals; body 5×5× 0.85 mm
SOT662-1
PCA9545AD SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
PCA9545APW TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
Table 2: Marking codesPCA9545ABS 9545A
PCA9545AD PCA9545AD
PCA9545APW PA9545A
Philips Semiconductors PCA9545A Block diagram
Philips Semiconductors PCA9545A Pinning information
6.1 Pinning
6.2 Pin description
Table 3: Pin description 1 19 address input 0 2 20 address input 1
RESET 3 1 active LOW reset input
INT0 4 2 active LOW interrupt input 0
SD0 5 3 serial data 0
SC0 6 4 serial clock 0
INT1 7 5 active LOW interrupt input 1
SD1 8 6 serial data 1
Philips Semiconductors PCA9545A[1] HVQFN packagedie supply groundis connectedto boththe VSSpin andthe exposed center pad. The VSS
pin mustbe connectedto supply groundfor proper device operation.For enhanced thermal, electrical, and
board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the PCB in the thermal pad region.
Functional descriptionRefer to Figure 1 “Block diagram of PCA9545A” on page 3.
7.1 Device addressFollowing a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9545A is shown in Figure 5. T o conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1, a read is selected while a logic 0 selects a write operation.
SC1 9 7 serial clock 1
VSS 10 8[1] supply ground
INT2 11 9 active LOW interrupt input 2
SD2 12 10 serial data 2
SC2 13 11 serial clock 2
INT3 14 12 active LOW interrupt input 3
SD3 15 13 serial data 3
SC3 16 14 serial clock 3
INT 17 15 active LOW interrupt output
SCL 18 16 serial clock line
SDA 19 17 serial data line
VDD 20 18 supply voltage
Table 3: Pin description …continued
Philips Semiconductors PCA9545A
7.2 Control registerFollowing the successful acknowledgementof the slave address, the bus master will send
a byte to the PCA9545A, which will be stored in the control register. If multiple bytes are
receivedby the PCA9545A,it will save the last byte received. This register canbe written
and read via the I2 C-bus.
7.2.1 Control register definitionOne or several SCx/SDx downstream pair, or channel, is selected by the contents of the
control register. This register is written after the PCA9545A has been addressed. The LSBsof the control byte are usedto determine which channelistobe selected. Whena
channel is selected, the channel will become active after a STOP condition has been
placed on the I2 C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when
the channel is made active, so that no false conditions are generated at the time of
connection.
Remark: Several channels can be enabled at the same time. Example: B3= 0, B2=1,= 1, B0= 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus capacity.
Table 4: Control register: Write—channel selection; Read—channel statusXXXXXXX 0 channel 0 disabled channel 0 enabled
XXXXXX 0 X channel 1 disabled channel 1 enabled
XXXXX 0 XX channel 2 disabled channel 2 enabled
XXXX 0 XXX channel 3 disabled channel 3 enabled
00000000no channel selected;
power-up/reset default state
Philips Semiconductors PCA9545A
7.2.2 Interrupt handlingThe PCA9545A provides 4 interrupt inputs, one for each channel, and one open-drain
interrupt output. When an interrupt is generated by any device, it will be detected by the
PCA9545A and the interrupt output willbe driven LOW. The channel does not needtobe
active for detection of the interrupt. A bit is also set in the control register.
Bit 4 through bit 7 of the control register corresponds to channel0 through channel 3 of
the PCA9545A, respectively. Therefore, if an interrupt is generated by any device
connected to channel 1, the state of the interrupt inputs is loaded into the control register
when a read is accomplished. Likewise, an interrupt on any device connected to
channel 0 would cause bit 4 of the control register to be set on the read. The master can
then address the PCA9545A and read the contents of the control register to determine
which channel contains the device generating the interrupt. The master can then
reconfigure the PCA9545A to select this channel, and locate the device generating the
interrupt and clearit. shouldbe noted that more than one device can providean interruptona channel,soitis
up to the master to ensure that all devices on a channel are interrogated for an interrupt.
The interrupt inputs maybe usedas general purpose inputsif the interrupt functionis not
required.
If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.
Remark: Several interrupts canbe activeat the same time. Example: INT3=0, INT2=1,
INT1= 1, INT0= 0, means that there is no interrupt on channel 0 and channel 3, and
there is interrupt on channel 1 and channel2.
7.3 RESET inputThe RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOWfora minimumof tWL, the PCA9545A will resetits
registers andI2 C-bus state machine and will deselectall channels. The RESET input must
be connected to VDD through a pull-up resistor.
Table 5: Control register: Read—interruptXXX 0 XXXX no interrupt on channel0 interrupt on channel0 0 XXXXX no interrupt on channel1 interrupt on channel1 0 XXXXXX no interrupt on channel2 interrupt on channel2 XXXXXXX no interrupt on channel3 interrupt on channel3
Philips Semiconductors PCA9545A
7.4 Power-On ResetWhen poweris appliedto VDD,an internal Power-On Reset (POR) holds the PCA9545Ain reset condition until VDD has reached VPOR.At this point, the reset conditionis released
and the PCA9545A registers and I2 C-bus state machine are initialized to their default
states—all zeroes—causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V to reset the device.
7.5 Voltage translationThe pass gate transistorsof the PCA9545A are constructed such that the VDD voltage can
be used to limit the maximum voltage that will be passed from one I2 C-bus to another.
Figure7 shows the voltage characteristicsof the pass gate transistors (note that the graph
was generated using the data specified in Section 11 “Static characteristics” of this data
sheet).In order for the PCA9545Ato actasa voltage translator, the Vo(sw) voltage should
be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9545A supply voltage is
3.5 V or lower, so the PCA9545A supply voltage could be set to 3.3 V. Pull-up resistors
can then be used to bring the bus voltages to their appropriate levels (see Figure 14).
More Information canbe foundin Application Note AN262: PCA954X familyof I2C/SMBus
multiplexers and switches.
Philips Semiconductors PCA9545A Characteristics of the I2 C-busTheI2 C-busisfor 2-way, 2-line communication between different ICsor modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transferOne databitis transferred during each clock pulse. The dataon the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure8).
8.2 START and STOP conditionsBoth data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the ST ART condition (S). LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the
STOP condition (P) (see Figure9).
Philips Semiconductors PCA9545A
8.3 System configurationA device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
8.4 AcknowledgeThe number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse. slave receiver whichis addressed must generatean acknowledge after the receptionof
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse,so that the SDA lineis stable
LOW during the HIGH period of the acknowledge related clock pulse; setup and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Philips Semiconductors PCA9545A
8.5 Bus transactionsData is transmitted to the PCA9545A control register using the Write mode as shown in
Figure 12.
Data is read from PCA9545A using the Read mode as shown in Figure 13.
Philips Semiconductors PCA9545A Application design-in information
Philips Semiconductors PCA9545A
10. Limiting values[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
Table 6: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground=0V).[1]
VDD supply voltage –0.5 +7.0 V input voltage –0.5 +7.0 V input current - ±20 mA output current - ±25 mA
IDD supply current - ±100 mA
ISS ground supply current - ±100 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature –60 +150 °C
Tamb operating ambient temperature –40 +85 °C
Philips Semiconductors PCA9545A
11. Static characteristics[1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges.
[2] VDD must be lowered to 0.2 V in order to reset part.
Table 7: Static characteristicsVDD = 2.3 V to 3.6 V; VSS = 0 V; Tamb = –40 °C to +85 °C; unless otherwise specified.
See Table 8 on page 15 for VDD = 4.5 V to 5.5V.[1]
SupplyVDD supply voltage 2.3 - 3.6 V
IDD supply current operating mode; VDD= 3.6V;no load; =VDD or VSS; fSCL= 100 kHz
-10 30 μA
Istb standby current standby mode; VDD= 3.6 V; no load; =VDDor VSS 0.1 1 μA
VPOR power-on reset voltage no load; VI =VDDor VSS [2]- 1.6 2.1 V
Input SCL; input/output SDAVIL LOW-level input voltage –0.5 - 0.3VDD V
VIH HIGH-level input voltage 0.7VDD -6 V
IOL LOW-level output current VOL= 0.4V 3 7 - mA
VOL= 0.6V 6 10 - mA leakage current VI =VDDor VSS –1 - +1 μA input capacitance VI =VSS -10 13 pF
Select inputs A0, A1, INT0to INT3, RESETVIL LOW-level input voltage –0.5 - 0.3VDD V
VIH HIGH-level input voltage 0.7VDD -VDD+ 0.5 V
ILI input leakage current pin at VDD or VSS –1 - +1 μA input capacitance VI =VSS - 1.6 3 pF
Pass gateRon on-state resistance VDD= 3.67 V; VO= 0.4 V; IO =15mA 5 11 30 Ω
VDD= 2.3 V to 2.7 V; VO= 0.4V; =10mA
716 55 Ω
Vo(sw) switch output voltage Vi(sw) =VDD= 3.3 V; Io(sw)= –100μA - 1.9 - V
Vi(sw) =VDD= 3.0 V to 3.6V;
Io(sw)= –100μA
1.6 - 2.8 V
Vi(sw) =VDD= 2.5 V; Io(sw)= –100μA - 1.5 - V
Vi(sw) =VDD= 2.3 V to 2.7V;
Io(sw)= –100μA
1.1 - 2.0 V leakage current VI =VDDor VSS –1 - +1 μA
Cio input/output capacitance VI =VSS -3 5 pF
INT outputIOL LOW-level output current VOL= 0.4V 3 - - mA
IOH HIGH-level output current - - +10 μA
