PCA9544ABS-PCA9544AD Fast Delivery |IC PHOENIX CO.,LIMITED

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PCA9544ABS-PCA9544AD
4-channel I2C-bus multiplexer with interrupt logic
1. General description
The PCA9544A is a 1-of-4 bidirectional translating multiplexer, controlled via the I2 C-bus.
The SCL/SDA upstream pair fans out to four SCx/SDx downstream pairs, or channels.
Only one SCx/SDx channel is selected at a time, determined by the contents of the
programmable control register. Four interrupt inputs, INT0 to INT3, one for each of the
SCx/SDx downstream pairs, are provided. One interrupt output, INT, which acts as an
AND of the four interrupt inputs, is provided.
A power-on reset function puts the registers in their default state and initializes the I2 C-bus
state machine with no channels selected.
The pass gates of the multiplexer are constructed such that the VDD pin can be used to
limit the maximum high voltage which is passed by the PCA9544A. This allows the use of
different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V or 3.3 V parts can
communicate with 5 V parts without any additional protection. External pull-up resistors
pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
2. Features and benefits 1-of-4 bidirectional translating multiplexerI2 C-bus interface logic; compatible with SMBus 4 active LOW interrupt inputs Active LOW interrupt output 3 address pins allowing up to 8 devices on the I2 C-bus Channel selection via I2 C-bus Power-up with all multiplexer channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5V5 V tolerant Inputs0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Three packages offered: SO20, TSSOP20 and HVQFN20
PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
Rev. 5 — 23 April 2014 Product data sheet
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
3. Ordering information
3.1 Ordering options
Table 1. Ordering information
Table 2. Ordering options
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
4. Block diagram
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
5. Pinning information
5.1 Pinning
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
5.2 Pin description
[1] HVQFN20 package supply ground is connected to both VSS pin and exposed center pad. VSS pin must be
connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level
performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the
board and for proper heat conduction through the board, thermal vias must be incorporated in the PCB in
the thermal pad region.
Table 3. Pin description
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
6. Functional description
Refer to Figure 1 “Block diagram”.
6.1 Device addressing
Following a START condition the bus master must output the address of the slave it is
accessing. The address of the PCA9544A is shown in Figure 5. T o conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
6.2 Control register
Following the successful acknowledgement of the slave address, the bus master sends a
byte to the PCA9544A which is stored in the Control register. If the PCA9544A receives
multiple bytes, it saves the last byte received. This register can be written and read via the 2 C-bus.
6.2.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9544A has been addressed. The 3 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, it will become active after a STOP condition has been placed on the I2 C-bus.
This ensures that all SCx/SDx lines are in a HIGH state when the channel is made active,
so that no false conditions are generated at the time of connection.
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
6.3 Interrupt handling
The PCA9544A provides 4 interrupt inputs, one for each channel and one open-drain
interrupt output. When an interrupt is generated by any device, it is detected by the
PCA9544A and the interrupt output is driven LOW. The channel need not be active for
detection of the interrupt. A bit is also set in the control byte. Bits 7:4 of the control byte
correspond to channel 3 to channel 0 of the PCA9544A, respectively. Therefore, if an
interrupt is generated by any device connected to channel 2, the state of the interrupt
inputs is loaded into the control register when a read is accomplished. Likewise, an
interrupt on any device connected to channel 0 would cause bit 4 of the control register to
be set on the read. The master can then address the PCA9544A and read the contents of
the control byte to determine which channel contains the device generating the interrupt.
The master can then reconfigure the PCA9544A to select this channel, and locate the
device generating the interrupt and clear it. The interrupt clears when the device
originating the interrupt clears.
It should be noted that more than one device can be providing an interrupt on a channel,
so it is up to the master to ensure that all devices on a channel are interrogated for an
interrupt.
If the interrupt function is not required, the interrupt inputs may be used as
general-purpose inputs.
If unused, interrupt inputs must be connected to VDD through a pull-up resistor.
Remark: Several interrupts can be active at the same time. For example: INT3=0,
INT2= 1, INT1= 1, INT0= 0, means that there is no interrupt on channel 0 and
channel 3, and there is an interrupt on channel 1 and on channel2.
Table 4. Control register: Write — channel selection; Read — channel status
Table 5. Control register read — interrupt
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
6.4 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9544A in
a reset condition until VDD has reached VPOR. At this point, the reset condition is released
and the PCA9544A registers and I2 C-bus state machine are initialized to their default
states (all zeroes), causing all the channels to be deselected. Thereafter, VDD must be
lowered below 0.2 V for at least 5 s in order to reset the device.
6.5 Voltage translation
The pass gate transistors of the PCA9544A are constructed such that the VDD voltage can
be used to limit the maximum voltage that is passed from one I2 C-bus to another.
Figure 7 shows the voltage characteristics of the pass gate transistors (note that the graph
was generated using the data specified in Section 12 “Dynamic characteristics” of this
data sheet). In order for the PCA9544A to act as a voltage translator, the Vo(sw) voltage
should be equal to, or lower than the lowest bus voltage. For example, if the main bus was
running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be
equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at
Figure 7, we see that Vo(sw)(max) is at 2.7 V when the PCA9544A supply voltage is 3.5 V or
lower so the PCA9544A supply voltage could be set to 3.3 V. Pull-up resistors can then be
used to bring the bus voltages to their appropriate levels (see Figure 14).
More Information can be found in Application Note AN262, PCA954X family of I2 C/SMBus
multiplexers and switches.
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
7. Characteristics of the I2 C-bus
The I2 C-bus is for 2-way, 2-line communication between different ICs or modules. The two
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as control signals (see Figure 8).
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S). A
LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (see Figure9).
7.3 System configuration
A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 10).
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
7.4 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of 8 bits is followed by one acknowledge
bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the
master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also, a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
7.5 Bus transactions
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
8. Application design-in information
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
9. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal
environment can create junction temperatures which are detrimental to reliability. The maximum junction
temperature of this integrated circuit should not exceed 125C.
10. Thermal characteristics
Table 6. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to ground (VSS = 0V).[1]
Table 7. Thermal characteristics
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
11. Static characteristics
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] In order to reset part, VDD must be lowered to 0.2 V for at least 5s.
Table 8. Static characteristics at VDD =2.3 V to 3.6V
VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified. See Table 9 for VDD= 4.5 V to 5.5V.[1]
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] In order to reset part, VDD must be lowered to 0.2 V for at least 5s.
Table 9. Static characteristics at VDD =4.5 V to 5.5V
VSS =0V; Tamb= 40 C to +85 C; unless otherwise specified. See Table 8 for VDD= 2.3 V to 3.6V.[1]
NXP Semiconductors PCA9544A
4-channel I2 C-bus multiplexer with interrupt logic
12. Dynamic characteristics
[1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Cb= total capacitance of one bus line in pF.
[5] Measurements taken with 1 k pull-up resistor and 50 pF load.
Table 10. Dynamic characteristics

Partno	Mfg	Dc	Qty	Available	Descript
PCA9544ABS	NXP	N/a	41	avai	4-channel I2C-bus multiplexer with interrupt logic
PCA9544AD	NXP	N/a	15	avai	PCA9544A; 4-channel I²C multiplexer with interrupt logic